VerilogParser.jj

/**
 * JavaCC file
 */

options {
    JDK_VERSION = "1.8";
    STATIC = false;
    DEBUG_PARSER = true;
    DEBUG_LOOKAHEAD = false;
    DEBUG_TOKEN_MANAGER = false;
}

PARSER_BEGIN(VerilogParser)
package org.workcraft.plugins.circuit.jj.verilog;

import org.workcraft.plugins.circuit.verilog.*;

import java.util.*;

public class VerilogParser {

    private List<VerilogNet> createListOfNets(String name, VerilogPort.Range range) {
        List<VerilogNet> nets = new ArrayList<>();
        if (name == null) {
            nets.add(null);
        } else if (range == null) {
            nets.add(new VerilogNet(name));
        } else {
            int index = range.getTopIndex();
            while (index != range.getBottomIndex()) {
                nets.add(new VerilogNet(name, index));
                index -= range.getStep();
            }
            nets.add(new VerilogNet(name, index));
        }
        return nets;
    }
}
PARSER_END(VerilogParser)

SKIP:
{
    " "
|
    "\t"
|
    "\r"
|
    "\n"
|
    <"//" (~["\r", "\n"])*>
|
    "/*" : WITHIN_COMMENT
|
    <"`" (~["\r", "\n"])*>
}

<WITHIN_COMMENT> SKIP:
{
    "*/" : DEFAULT
|
    <~[]>
}

<WITHIN_SPECIFY> SKIP:
{
    "endspecify" : DEFAULT
|
     <~[]>
}

<WITHIN_PRIMITIVE> SKIP:
{
    "endprimitive" : DEFAULT
|
     <~[]>
}

TOKEN:
{
    <MODULE : "module">
|
    <ENDMODULE : "endmodule">
|
    <INPUT : "input">
|
    <OUTPUT : "output">
|
    <INOUT : "inout">
|
    <REG : "reg">
|
    <WIRE : "wire">
|
    <ASSIGN : "assign">
|
    <SPECIFY : "specify"> : WITHIN_SPECIFY
|
    <PRIMITIVE : "primitive"> : WITHIN_PRIMITIVE
|
    <NAME : ["A"-"Z", "a"-"z", "_"] (["A"-"Z", "a"-"z", "_", "0"-"9", "."])*>
|
    <FORMULA: "=" (~[";"])* ";">
|
    <PETRIFY_NAME : ["A"-"Z", "a"-"z", "_", "/"] ([ "A"-"Z", "a"-"z", "_", "0"-"9", ":", "/", "\\", "-"])*>
|
    <LOGIC0 : "1'b0">
|
    <LOGIC1 : "1'b1">
|
    <INTEGER : ([ "0"-"9" ])+>
|
    <DELAY: ("#" ([ "0"-"9" ])* (["."])? ([ "0"-"9" ])+) | ("#(" (~["(", ")"])* ")")>
|
    <PETRIFY_ZERO_DELAY : "// This inverter should have a short delay" <NEW_LINE_WITH_OPTIONAL_SPACES>>
|
    <MPSAT_ZERO_DELAY : "// #PRAGMA: zero delay" <NEW_LINE_WITH_OPTIONAL_SPACES>>
|
    <PETRIFY50_INIT_STATE : "// signal values at the initial state:" <NEW_LINE_WITH_OPTIONAL_SPACES> "//">
|
    <PETRIFY51_INIT_STATE : "// Initial state:" <NEW_LINE_WITH_OPTIONAL_SPACES> "//">
|
    <MPSAT_INIT_STATE : "// initial values of the signals" <NEW_LINE_WITH_OPTIONAL_SPACES> "//">
|
    <#NEW_LINE_WITH_OPTIONAL_SPACES: ([" ", "\t"])*(["\n", "\r"])+([" ", "\t"])*>
}

List<VerilogModule> parseCircuit():
{
    List<VerilogModule> modules;
}
{
    modules = parseModules()
    {
        return modules;
    }
}

List<VerilogModule> parseModules():
{
    VerilogModule module;
    List<VerilogModule> modules = new LinkedList<>();
}
{
    (
        module = parseModule()
        {
            modules.add(module);
        }
    )*
    {
        return modules;
    }
}

VerilogModule parseModule():
{
    String name;
    List<VerilogPort> ports;
    Map<String, VerilogPort> nameToPortMap = new HashMap<>();
    VerilogAssign assign;
    List<VerilogAssign> assigns = new LinkedList<>();
    VerilogInstance instance;
    List<VerilogInstance> instances = new LinkedList<>();
    Map<VerilogNet, Boolean> netStates = new HashMap<>();
}
{
    <MODULE> name = parseModuleName()
    ports = parsePorts()
    {
        for (VerilogPort port : ports) {
            nameToPortMap.putIfAbsent(port.name, port);
        }
    }
    (
        (
            assign = parseAssign()
            {
                assigns.add(assign);
            }
        |
            instance = parseInstance(nameToPortMap)
            {
                instances.add(instance);
            }
        )
    )*
    [ (<PETRIFY50_INIT_STATE> | <PETRIFY51_INIT_STATE> | <MPSAT_INIT_STATE>)
        netStates = parseInitialState()
    ]
    <ENDMODULE>
    {
        return new VerilogModule(name, ports, assigns, instances, netStates);
    }
}

String parseModuleName():
{
    Token nameToken;
}
{
    (nameToken = <NAME> | nameToken = <PETRIFY_NAME>)
    {
        return nameToken.image;
    }
}

List<VerilogPort> parsePorts():
{
    List<VerilogPort> ports;
}
{
    (
        LOOKAHEAD("(" (<INPUT> | <OUTPUT> | <INOUT>))
        ports = parseCompactPorts()
    |
        ports = parseExtendedPorts()
    )
    {
        return ports;
    }
}

List<VerilogPort> parseCompactPorts():
{
    VerilogPort port;
    List<VerilogPort> internalPorts;
    List<VerilogPort> ports = new LinkedList<>();
}
{
    "("
        (
            port = parseCompactPort() [","]
            {
                ports.add(port);
            }
        )*
    ")" ";"
    internalPorts = parseTypedPorts()
    {
        ports.addAll(internalPorts);
        return ports;
    }
}

VerilogPort parseCompactPort():
{
    VerilogPort.Type type;
    VerilogPort.Range range = null;
    Token nameToken;
}
{
    type = parsePortType() [range = parseRange()] nameToken = <NAME>
    {
        return new VerilogPort(nameToken.image, type, range);
    }
}

List<VerilogPort> parseExtendedPorts():
{
    List<String> interfacePortNames;
    List<VerilogPort> typedPorts;
}
{
    "(" interfacePortNames = parseNames() ")" ";"
    typedPorts = parseTypedPorts()
    {
        HashMap<String, VerilogPort> nameToPort = new HashMap<>();
        for (VerilogPort port : typedPorts) {
            nameToPort.put(port.name, port);
        }
        List<VerilogPort> ports = new LinkedList<>();
        for (String interfacePortName : interfacePortNames) {
            VerilogPort port = nameToPort.get(interfacePortName);
            if (port != null) {
                ports.add(port);
            }
        }
        typedPorts.removeAll(ports);
        ports.addAll(typedPorts);
        return ports;
    }
}

List<VerilogPort> parseTypedPorts():
{
    List<VerilogPort> typedPorts;
    List<VerilogPort> ports = new LinkedList<>();
}
{
    (
        typedPorts = parseTypedPortsOfOneType()
        {
            ports.addAll(typedPorts);
        }
    )*
    {
        return ports;
    }
}

List<VerilogPort> parseTypedPortsOfOneType():
{
    VerilogPort.Type type;
    VerilogPort.Range range = null;
    List<String> names;
}
{
    type = parsePortType() [range = parseRange()] names = parseNames() ";"
    {
        List<VerilogPort> ports = new ArrayList<>();
        for (String name : names) {
            VerilogPort port = new VerilogPort(name, type, range);
            ports.add(port);
        }
        return ports;
    }
}

VerilogPort.Type parsePortType():
{
}
{
        <INPUT>
        {
            return VerilogPort.Type.INPUT;
        }
    |
        <OUTPUT>
        {
            return VerilogPort.Type.OUTPUT;
        }
    |
        <INOUT>
        {
            return VerilogPort.Type.INOUT;
        }
    |
        <WIRE>
        {
    return VerilogPort.Type.WIRE;
}
}

VerilogPort.Range parseRange():
{
    Token topIndexToken;
    Token bottomIndexToken;
}
{
    "[" topIndexToken = <INTEGER> ":" bottomIndexToken = <INTEGER> "]"
    {
        Integer topIndex = Integer.parseInt(topIndexToken.image);
        Integer bottomIndex = Integer.parseInt(bottomIndexToken.image);
        return new VerilogPort.Range(topIndex, bottomIndex);
    }
}

List<String> parseNames():
{
    Token nameToken;
    List<String> names = new LinkedList<>();
}
{
    (
        nameToken = <NAME> [","]
        {
            String name = nameToken.image;
            names.add(name);
        }
    )*
    {
        return names;
    }
}

Map<VerilogNet, Boolean> parseInitialState():
{
    VerilogNet net;
    boolean state;
    Map<VerilogNet, Boolean> netStates = new HashMap<>();
}
{
    (
        (
            "!" net = parseNet()
            {
                state = false;
            }
        |
            net = parseNet()
            {
                state = true;
            }
        )
        {
           netStates.put(net, state);
        }
    )*
    {
        return netStates;
    }
}

VerilogAssign parseAssign():
{
    VerilogNet net;
    Token formulaToken;
}
{
    <ASSIGN> [<DELAY>] net = parseNet() formulaToken = <FORMULA>
    {
        String formula = formulaToken.image
                .replaceAll("^=", "")  // start of assign expression
                .replaceAll(";$", "")  // end of assign expression
                .replace("1'b0", "0")  // LOGIC0
                .replace("1'b1", "1"); // LOGIC1

        return new VerilogAssign(net, formula);
    }
}

VerilogInstance parseInstance(Map<String, VerilogPort> nameToPortMap):
{
    boolean zeroDelay = false;
    String moduleName;
    Token nameToken = null;
    List<String> parameters;
    List<VerilogConnection> connections;
}
{
    [
        (<PETRIFY_ZERO_DELAY> | <MPSAT_ZERO_DELAY>)
        {
            zeroDelay = true;
        }
    ]
    moduleName = parseModuleName()
    [nameToken = <NAME>]
    "(" connections = parseConnections(nameToPortMap) ")" ";"
    {
        String name = (nameToken == null ? null : nameToken.image);
        return new VerilogInstance(name, moduleName, connections, zeroDelay);
    }
}

List<VerilogConnection> parseConnections(Map<String, VerilogPort> nameToPortMap):
{
    List<VerilogConnection> connections;
}
{
    (
        LOOKAHEAD(".")
        connections = parseNamedConnections(nameToPortMap)
    |
        connections = parseOrderedConnections()
    )
    {
        return connections;
    }
}

List<VerilogConnection> parseNamedConnections(Map<String, VerilogPort> nameToPortMap):
{
    VerilogConnection connection;
    List<VerilogConnection> connections = new LinkedList<>();
}
{
    connection = parseNamedConnection(nameToPortMap)
    {
        connections.add(connection);
    }
    (
        "," connection = parseNamedConnection(nameToPortMap)
        {
            connections.add(connection);
        }
    )*
    {
        return connections;
    }
}

VerilogConnection parseNamedConnection(Map<String, VerilogPort> nameToPortMap):
{
    Token nameToken;
    List<VerilogNet> nets;
}
{
    "." nameToken = <NAME> "("
    (
        LOOKAHEAD("{")
        "{" nets = parseOptionalNets(nameToPortMap) "}"
    |
        nets = parseOptionalNetRange(nameToPortMap)
    )
    ")"
    {
        return new VerilogConnection(nameToken.image, nets);
    }
}

List<VerilogConnection> parseOrderedConnections():
{
    VerilogNet net;
    List<VerilogConnection> connections = new LinkedList<>();
}
{
    net = parseOptionalNet()
    {
        connections.add(new VerilogConnection(null, Collections.singletonList(net)));
    }
    (
        "," net = parseOptionalNet()
        {
            connections.add(new VerilogConnection(null, Collections.singletonList(net)));
        }
    )*
    {
        return connections;
    }
}

List<VerilogNet> parseOptionalNets(Map<String, VerilogPort> nameToPortMap):
{
    List<VerilogNet> netRange;
    List<VerilogNet> nets;
}
{
    nets = parseOptionalNetRange(nameToPortMap)
    (
        "," netRange = parseOptionalNetRange(nameToPortMap)
        {
            nets.addAll(netRange);
        }
    )*
    {
        return nets;
    }
}

List<VerilogNet> parseOptionalNetRange(Map<String, VerilogPort> nameToPortMap):
{
    Token nameToken = null;
    VerilogPort.Range range = null;
    Integer index = null;
}
{
    [
        nameToken = <NAME>
        [
                LOOKAHEAD(parseRange())
                range = parseRange()
            |
                index = parseIndex()
                {
                    range = new VerilogPort.Range(index, index);
                }
        ]
    ]
    {
        String name = nameToken == null ? null : nameToken.image;
        if ((name != null) && (range == null)) {
            VerilogPort port = nameToPortMap.get(name);
            if (port != null) {
                range = port.range;
            }
        }
        return createListOfNets(name, range);
    }
}


VerilogNet parseOptionalNet():
{
    VerilogNet net = null;
}
{
    [net = parseNet()]
    {
        return net;
    }
}

VerilogNet parseNet():
{
    Token nameToken;
    Integer index = null;
}
{
    nameToken = <NAME> [ index = parseIndex()]
    {
        return new VerilogNet(nameToken.image, index);
    }
}

Integer parseIndex():
{
    Token indexToken;
}
{
    "[" indexToken = <INTEGER> "]"
    {
        return Integer.parseInt(indexToken.image);
    }
}