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t3_hw.c
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t3_hw.c
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/*
* Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <linux/etherdevice.h>
#include "common.h"
#include "regs.h"
#include "sge_defs.h"
#include "firmware_exports.h"
static void t3_port_intr_clear(struct adapter *adapter, int idx);
/**
* t3_wait_op_done_val - wait until an operation is completed
* @adapter: the adapter performing the operation
* @reg: the register to check for completion
* @mask: a single-bit field within @reg that indicates completion
* @polarity: the value of the field when the operation is completed
* @attempts: number of check iterations
* @delay: delay in usecs between iterations
* @valp: where to store the value of the register at completion time
*
* Wait until an operation is completed by checking a bit in a register
* up to @attempts times. If @valp is not NULL the value of the register
* at the time it indicated completion is stored there. Returns 0 if the
* operation completes and -EAGAIN otherwise.
*/
int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
int polarity, int attempts, int delay, u32 *valp)
{
while (1) {
u32 val = t3_read_reg(adapter, reg);
if (!!(val & mask) == polarity) {
if (valp)
*valp = val;
return 0;
}
if (--attempts == 0)
return -EAGAIN;
if (delay)
udelay(delay);
}
}
/**
* t3_write_regs - write a bunch of registers
* @adapter: the adapter to program
* @p: an array of register address/register value pairs
* @n: the number of address/value pairs
* @offset: register address offset
*
* Takes an array of register address/register value pairs and writes each
* value to the corresponding register. Register addresses are adjusted
* by the supplied offset.
*/
void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p,
int n, unsigned int offset)
{
while (n--) {
t3_write_reg(adapter, p->reg_addr + offset, p->val);
p++;
}
}
/**
* t3_set_reg_field - set a register field to a value
* @adapter: the adapter to program
* @addr: the register address
* @mask: specifies the portion of the register to modify
* @val: the new value for the register field
*
* Sets a register field specified by the supplied mask to the
* given value.
*/
void t3_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
u32 val)
{
u32 v = t3_read_reg(adapter, addr) & ~mask;
t3_write_reg(adapter, addr, v | val);
t3_read_reg(adapter, addr); /* flush */
}
/**
* t3_read_indirect - read indirectly addressed registers
* @adap: the adapter
* @addr_reg: register holding the indirect address
* @data_reg: register holding the value of the indirect register
* @vals: where the read register values are stored
* @start_idx: index of first indirect register to read
* @nregs: how many indirect registers to read
*
* Reads registers that are accessed indirectly through an address/data
* register pair.
*/
static void t3_read_indirect(struct adapter *adap, unsigned int addr_reg,
unsigned int data_reg, u32 *vals,
unsigned int nregs, unsigned int start_idx)
{
while (nregs--) {
t3_write_reg(adap, addr_reg, start_idx);
*vals++ = t3_read_reg(adap, data_reg);
start_idx++;
}
}
/**
* t3_mc7_bd_read - read from MC7 through backdoor accesses
* @mc7: identifies MC7 to read from
* @start: index of first 64-bit word to read
* @n: number of 64-bit words to read
* @buf: where to store the read result
*
* Read n 64-bit words from MC7 starting at word start, using backdoor
* accesses.
*/
int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
u64 *buf)
{
static const int shift[] = { 0, 0, 16, 24 };
static const int step[] = { 0, 32, 16, 8 };
unsigned int size64 = mc7->size / 8; /* # of 64-bit words */
struct adapter *adap = mc7->adapter;
if (start >= size64 || start + n > size64)
return -EINVAL;
start *= (8 << mc7->width);
while (n--) {
int i;
u64 val64 = 0;
for (i = (1 << mc7->width) - 1; i >= 0; --i) {
int attempts = 10;
u32 val;
t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR, start);
t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0);
val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);
while ((val & F_BUSY) && attempts--)
val = t3_read_reg(adap,
mc7->offset + A_MC7_BD_OP);
if (val & F_BUSY)
return -EIO;
val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);
if (mc7->width == 0) {
val64 = t3_read_reg(adap,
mc7->offset +
A_MC7_BD_DATA0);
val64 |= (u64) val << 32;
} else {
if (mc7->width > 1)
val >>= shift[mc7->width];
val64 |= (u64) val << (step[mc7->width] * i);
}
start += 8;
}
*buf++ = val64;
}
return 0;
}
/*
* Initialize MI1.
*/
static void mi1_init(struct adapter *adap, const struct adapter_info *ai)
{
u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1;
u32 val = F_PREEN | V_CLKDIV(clkdiv);
t3_write_reg(adap, A_MI1_CFG, val);
}
#define MDIO_ATTEMPTS 20
/*
* MI1 read/write operations for clause 22 PHYs.
*/
static int t3_mi1_read(struct net_device *dev, int phy_addr, int mmd_addr,
u16 reg_addr)
{
struct port_info *pi = netdev_priv(dev);
struct adapter *adapter = pi->adapter;
int ret;
u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);
mutex_lock(&adapter->mdio_lock);
t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
t3_write_reg(adapter, A_MI1_ADDR, addr);
t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2));
ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
if (!ret)
ret = t3_read_reg(adapter, A_MI1_DATA);
mutex_unlock(&adapter->mdio_lock);
return ret;
}
static int t3_mi1_write(struct net_device *dev, int phy_addr, int mmd_addr,
u16 reg_addr, u16 val)
{
struct port_info *pi = netdev_priv(dev);
struct adapter *adapter = pi->adapter;
int ret;
u32 addr = V_REGADDR(reg_addr) | V_PHYADDR(phy_addr);
mutex_lock(&adapter->mdio_lock);
t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), V_ST(1));
t3_write_reg(adapter, A_MI1_ADDR, addr);
t3_write_reg(adapter, A_MI1_DATA, val);
t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
mutex_unlock(&adapter->mdio_lock);
return ret;
}
static const struct mdio_ops mi1_mdio_ops = {
.read = t3_mi1_read,
.write = t3_mi1_write,
.mode_support = MDIO_SUPPORTS_C22
};
/*
* Performs the address cycle for clause 45 PHYs.
* Must be called with the MDIO_LOCK held.
*/
static int mi1_wr_addr(struct adapter *adapter, int phy_addr, int mmd_addr,
int reg_addr)
{
u32 addr = V_REGADDR(mmd_addr) | V_PHYADDR(phy_addr);
t3_set_reg_field(adapter, A_MI1_CFG, V_ST(M_ST), 0);
t3_write_reg(adapter, A_MI1_ADDR, addr);
t3_write_reg(adapter, A_MI1_DATA, reg_addr);
t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
return t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
MDIO_ATTEMPTS, 10);
}
/*
* MI1 read/write operations for indirect-addressed PHYs.
*/
static int mi1_ext_read(struct net_device *dev, int phy_addr, int mmd_addr,
u16 reg_addr)
{
struct port_info *pi = netdev_priv(dev);
struct adapter *adapter = pi->adapter;
int ret;
mutex_lock(&adapter->mdio_lock);
ret = mi1_wr_addr(adapter, phy_addr, mmd_addr, reg_addr);
if (!ret) {
t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3));
ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
MDIO_ATTEMPTS, 10);
if (!ret)
ret = t3_read_reg(adapter, A_MI1_DATA);
}
mutex_unlock(&adapter->mdio_lock);
return ret;
}
static int mi1_ext_write(struct net_device *dev, int phy_addr, int mmd_addr,
u16 reg_addr, u16 val)
{
struct port_info *pi = netdev_priv(dev);
struct adapter *adapter = pi->adapter;
int ret;
mutex_lock(&adapter->mdio_lock);
ret = mi1_wr_addr(adapter, phy_addr, mmd_addr, reg_addr);
if (!ret) {
t3_write_reg(adapter, A_MI1_DATA, val);
t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
MDIO_ATTEMPTS, 10);
}
mutex_unlock(&adapter->mdio_lock);
return ret;
}
static const struct mdio_ops mi1_mdio_ext_ops = {
.read = mi1_ext_read,
.write = mi1_ext_write,
.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22
};
/**
* t3_mdio_change_bits - modify the value of a PHY register
* @phy: the PHY to operate on
* @mmd: the device address
* @reg: the register address
* @clear: what part of the register value to mask off
* @set: what part of the register value to set
*
* Changes the value of a PHY register by applying a mask to its current
* value and ORing the result with a new value.
*/
int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
unsigned int set)
{
int ret;
unsigned int val;
ret = t3_mdio_read(phy, mmd, reg, &val);
if (!ret) {
val &= ~clear;
ret = t3_mdio_write(phy, mmd, reg, val | set);
}
return ret;
}
/**
* t3_phy_reset - reset a PHY block
* @phy: the PHY to operate on
* @mmd: the device address of the PHY block to reset
* @wait: how long to wait for the reset to complete in 1ms increments
*
* Resets a PHY block and optionally waits for the reset to complete.
* @mmd should be 0 for 10/100/1000 PHYs and the device address to reset
* for 10G PHYs.
*/
int t3_phy_reset(struct cphy *phy, int mmd, int wait)
{
int err;
unsigned int ctl;
err = t3_mdio_change_bits(phy, mmd, MDIO_CTRL1, MDIO_CTRL1_LPOWER,
MDIO_CTRL1_RESET);
if (err || !wait)
return err;
do {
err = t3_mdio_read(phy, mmd, MDIO_CTRL1, &ctl);
if (err)
return err;
ctl &= MDIO_CTRL1_RESET;
if (ctl)
msleep(1);
} while (ctl && --wait);
return ctl ? -1 : 0;
}
/**
* t3_phy_advertise - set the PHY advertisement registers for autoneg
* @phy: the PHY to operate on
* @advert: bitmap of capabilities the PHY should advertise
*
* Sets a 10/100/1000 PHY's advertisement registers to advertise the
* requested capabilities.
*/
int t3_phy_advertise(struct cphy *phy, unsigned int advert)
{
int err;
unsigned int val = 0;
err = t3_mdio_read(phy, MDIO_DEVAD_NONE, MII_CTRL1000, &val);
if (err)
return err;
val &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
if (advert & ADVERTISED_1000baseT_Half)
val |= ADVERTISE_1000HALF;
if (advert & ADVERTISED_1000baseT_Full)
val |= ADVERTISE_1000FULL;
err = t3_mdio_write(phy, MDIO_DEVAD_NONE, MII_CTRL1000, val);
if (err)
return err;
val = 1;
if (advert & ADVERTISED_10baseT_Half)
val |= ADVERTISE_10HALF;
if (advert & ADVERTISED_10baseT_Full)
val |= ADVERTISE_10FULL;
if (advert & ADVERTISED_100baseT_Half)
val |= ADVERTISE_100HALF;
if (advert & ADVERTISED_100baseT_Full)
val |= ADVERTISE_100FULL;
if (advert & ADVERTISED_Pause)
val |= ADVERTISE_PAUSE_CAP;
if (advert & ADVERTISED_Asym_Pause)
val |= ADVERTISE_PAUSE_ASYM;
return t3_mdio_write(phy, MDIO_DEVAD_NONE, MII_ADVERTISE, val);
}
/**
* t3_phy_advertise_fiber - set fiber PHY advertisement register
* @phy: the PHY to operate on
* @advert: bitmap of capabilities the PHY should advertise
*
* Sets a fiber PHY's advertisement register to advertise the
* requested capabilities.
*/
int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert)
{
unsigned int val = 0;
if (advert & ADVERTISED_1000baseT_Half)
val |= ADVERTISE_1000XHALF;
if (advert & ADVERTISED_1000baseT_Full)
val |= ADVERTISE_1000XFULL;
if (advert & ADVERTISED_Pause)
val |= ADVERTISE_1000XPAUSE;
if (advert & ADVERTISED_Asym_Pause)
val |= ADVERTISE_1000XPSE_ASYM;
return t3_mdio_write(phy, MDIO_DEVAD_NONE, MII_ADVERTISE, val);
}
/**
* t3_set_phy_speed_duplex - force PHY speed and duplex
* @phy: the PHY to operate on
* @speed: requested PHY speed
* @duplex: requested PHY duplex
*
* Force a 10/100/1000 PHY's speed and duplex. This also disables
* auto-negotiation except for GigE, where auto-negotiation is mandatory.
*/
int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex)
{
int err;
unsigned int ctl;
err = t3_mdio_read(phy, MDIO_DEVAD_NONE, MII_BMCR, &ctl);
if (err)
return err;
if (speed >= 0) {
ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
if (speed == SPEED_100)
ctl |= BMCR_SPEED100;
else if (speed == SPEED_1000)
ctl |= BMCR_SPEED1000;
}
if (duplex >= 0) {
ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE);
if (duplex == DUPLEX_FULL)
ctl |= BMCR_FULLDPLX;
}
if (ctl & BMCR_SPEED1000) /* auto-negotiation required for GigE */
ctl |= BMCR_ANENABLE;
return t3_mdio_write(phy, MDIO_DEVAD_NONE, MII_BMCR, ctl);
}
int t3_phy_lasi_intr_enable(struct cphy *phy)
{
return t3_mdio_write(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL,
MDIO_PMA_LASI_LSALARM);
}
int t3_phy_lasi_intr_disable(struct cphy *phy)
{
return t3_mdio_write(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_CTRL, 0);
}
int t3_phy_lasi_intr_clear(struct cphy *phy)
{
u32 val;
return t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);
}
int t3_phy_lasi_intr_handler(struct cphy *phy)
{
unsigned int status;
int err = t3_mdio_read(phy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT,
&status);
if (err)
return err;
return (status & MDIO_PMA_LASI_LSALARM) ? cphy_cause_link_change : 0;
}
static const struct adapter_info t3_adap_info[] = {
{1, 1, 0,
F_GPIO2_OEN | F_GPIO4_OEN |
F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0,
&mi1_mdio_ops, "Chelsio PE9000"},
{1, 1, 0,
F_GPIO2_OEN | F_GPIO4_OEN |
F_GPIO2_OUT_VAL | F_GPIO4_OUT_VAL, { S_GPIO3, S_GPIO5 }, 0,
&mi1_mdio_ops, "Chelsio T302"},
{1, 0, 0,
F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN | F_GPIO10_OEN |
F_GPIO11_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
{ 0 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
&mi1_mdio_ext_ops, "Chelsio T310"},
{1, 1, 0,
F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO5_OEN | F_GPIO6_OEN |
F_GPIO7_OEN | F_GPIO10_OEN | F_GPIO11_OEN | F_GPIO1_OUT_VAL |
F_GPIO5_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
{ S_GPIO9, S_GPIO3 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
&mi1_mdio_ext_ops, "Chelsio T320"},
{},
{},
{1, 0, 0,
F_GPIO1_OEN | F_GPIO2_OEN | F_GPIO4_OEN | F_GPIO6_OEN | F_GPIO7_OEN |
F_GPIO10_OEN | F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL | F_GPIO10_OUT_VAL,
{ S_GPIO9 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
&mi1_mdio_ext_ops, "Chelsio T310" },
{1, 0, 0,
F_GPIO1_OEN | F_GPIO6_OEN | F_GPIO7_OEN |
F_GPIO1_OUT_VAL | F_GPIO6_OUT_VAL,
{ S_GPIO9 }, SUPPORTED_10000baseT_Full | SUPPORTED_AUI,
&mi1_mdio_ext_ops, "Chelsio N320E-G2" },
};
/*
* Return the adapter_info structure with a given index. Out-of-range indices
* return NULL.
*/
const struct adapter_info *t3_get_adapter_info(unsigned int id)
{
return id < ARRAY_SIZE(t3_adap_info) ? &t3_adap_info[id] : NULL;
}
struct port_type_info {
int (*phy_prep)(struct cphy *phy, struct adapter *adapter,
int phy_addr, const struct mdio_ops *ops);
};
static const struct port_type_info port_types[] = {
{ NULL },
{ t3_ael1002_phy_prep },
{ t3_vsc8211_phy_prep },
{ NULL},
{ t3_xaui_direct_phy_prep },
{ t3_ael2005_phy_prep },
{ t3_qt2045_phy_prep },
{ t3_ael1006_phy_prep },
{ NULL },
{ t3_aq100x_phy_prep },
{ t3_ael2020_phy_prep },
};
#define VPD_ENTRY(name, len) \
u8 name##_kword[2]; u8 name##_len; u8 name##_data[len]
/*
* Partial EEPROM Vital Product Data structure. Includes only the ID and
* VPD-R sections.
*/
struct t3_vpd {
u8 id_tag;
u8 id_len[2];
u8 id_data[16];
u8 vpdr_tag;
u8 vpdr_len[2];
VPD_ENTRY(pn, 16); /* part number */
VPD_ENTRY(ec, 16); /* EC level */
VPD_ENTRY(sn, SERNUM_LEN); /* serial number */
VPD_ENTRY(na, 12); /* MAC address base */
VPD_ENTRY(cclk, 6); /* core clock */
VPD_ENTRY(mclk, 6); /* mem clock */
VPD_ENTRY(uclk, 6); /* uP clk */
VPD_ENTRY(mdc, 6); /* MDIO clk */
VPD_ENTRY(mt, 2); /* mem timing */
VPD_ENTRY(xaui0cfg, 6); /* XAUI0 config */
VPD_ENTRY(xaui1cfg, 6); /* XAUI1 config */
VPD_ENTRY(port0, 2); /* PHY0 complex */
VPD_ENTRY(port1, 2); /* PHY1 complex */
VPD_ENTRY(port2, 2); /* PHY2 complex */
VPD_ENTRY(port3, 2); /* PHY3 complex */
VPD_ENTRY(rv, 1); /* csum */
u32 pad; /* for multiple-of-4 sizing and alignment */
};
#define EEPROM_STAT_ADDR 0x4000
#define VPD_BASE 0xc00
/**
* t3_seeprom_wp - enable/disable EEPROM write protection
* @adapter: the adapter
* @enable: 1 to enable write protection, 0 to disable it
*
* Enables or disables write protection on the serial EEPROM.
*/
int t3_seeprom_wp(struct adapter *adapter, int enable)
{
u32 data = enable ? 0xc : 0;
int ret;
/* EEPROM_STAT_ADDR is outside VPD area, use pci_write_vpd_any() */
ret = pci_write_vpd_any(adapter->pdev, EEPROM_STAT_ADDR, sizeof(u32),
&data);
return ret < 0 ? ret : 0;
}
static int vpdstrtouint(char *s, u8 len, unsigned int base, unsigned int *val)
{
char tok[256];
memcpy(tok, s, len);
tok[len] = 0;
return kstrtouint(strim(tok), base, val);
}
static int vpdstrtou16(char *s, u8 len, unsigned int base, u16 *val)
{
char tok[256];
memcpy(tok, s, len);
tok[len] = 0;
return kstrtou16(strim(tok), base, val);
}
/**
* get_vpd_params - read VPD parameters from VPD EEPROM
* @adapter: adapter to read
* @p: where to store the parameters
*
* Reads card parameters stored in VPD EEPROM.
*/
static int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
{
struct t3_vpd vpd;
u8 base_val = 0;
int addr, ret;
/*
* Card information is normally at VPD_BASE but some early cards had
* it at 0.
*/
ret = pci_read_vpd(adapter->pdev, VPD_BASE, 1, &base_val);
if (ret < 0)
return ret;
addr = base_val == PCI_VPD_LRDT_ID_STRING ? VPD_BASE : 0;
ret = pci_read_vpd(adapter->pdev, addr, sizeof(vpd), &vpd);
if (ret < 0)
return ret;
ret = vpdstrtouint(vpd.cclk_data, vpd.cclk_len, 10, &p->cclk);
if (ret)
return ret;
ret = vpdstrtouint(vpd.mclk_data, vpd.mclk_len, 10, &p->mclk);
if (ret)
return ret;
ret = vpdstrtouint(vpd.uclk_data, vpd.uclk_len, 10, &p->uclk);
if (ret)
return ret;
ret = vpdstrtouint(vpd.mdc_data, vpd.mdc_len, 10, &p->mdc);
if (ret)
return ret;
ret = vpdstrtouint(vpd.mt_data, vpd.mt_len, 10, &p->mem_timing);
if (ret)
return ret;
memcpy(p->sn, vpd.sn_data, SERNUM_LEN);
/* Old eeproms didn't have port information */
if (adapter->params.rev == 0 && !vpd.port0_data[0]) {
p->port_type[0] = uses_xaui(adapter) ? 1 : 2;
p->port_type[1] = uses_xaui(adapter) ? 6 : 2;
} else {
p->port_type[0] = hex_to_bin(vpd.port0_data[0]);
p->port_type[1] = hex_to_bin(vpd.port1_data[0]);
ret = vpdstrtou16(vpd.xaui0cfg_data, vpd.xaui0cfg_len, 16,
&p->xauicfg[0]);
if (ret)
return ret;
ret = vpdstrtou16(vpd.xaui1cfg_data, vpd.xaui1cfg_len, 16,
&p->xauicfg[1]);
if (ret)
return ret;
}
ret = hex2bin(p->eth_base, vpd.na_data, 6);
if (ret < 0)
return -EINVAL;
return 0;
}
/* serial flash and firmware constants */
enum {
SF_ATTEMPTS = 5, /* max retries for SF1 operations */
SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
SF_SIZE = SF_SEC_SIZE * 8, /* serial flash size */
/* flash command opcodes */
SF_PROG_PAGE = 2, /* program page */
SF_WR_DISABLE = 4, /* disable writes */
SF_RD_STATUS = 5, /* read status register */
SF_WR_ENABLE = 6, /* enable writes */
SF_RD_DATA_FAST = 0xb, /* read flash */
SF_ERASE_SECTOR = 0xd8, /* erase sector */
FW_FLASH_BOOT_ADDR = 0x70000, /* start address of FW in flash */
FW_VERS_ADDR = 0x7fffc, /* flash address holding FW version */
FW_MIN_SIZE = 8 /* at least version and csum */
};
/**
* sf1_read - read data from the serial flash
* @adapter: the adapter
* @byte_cnt: number of bytes to read
* @cont: whether another operation will be chained
* @valp: where to store the read data
*
* Reads up to 4 bytes of data from the serial flash. The location of
* the read needs to be specified prior to calling this by issuing the
* appropriate commands to the serial flash.
*/
static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
u32 *valp)
{
int ret;
if (!byte_cnt || byte_cnt > 4)
return -EINVAL;
if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
return -EBUSY;
t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
ret = t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10);
if (!ret)
*valp = t3_read_reg(adapter, A_SF_DATA);
return ret;
}
/**
* sf1_write - write data to the serial flash
* @adapter: the adapter
* @byte_cnt: number of bytes to write
* @cont: whether another operation will be chained
* @val: value to write
*
* Writes up to 4 bytes of data to the serial flash. The location of
* the write needs to be specified prior to calling this by issuing the
* appropriate commands to the serial flash.
*/
static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
u32 val)
{
if (!byte_cnt || byte_cnt > 4)
return -EINVAL;
if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
return -EBUSY;
t3_write_reg(adapter, A_SF_DATA, val);
t3_write_reg(adapter, A_SF_OP,
V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
return t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10);
}
/**
* flash_wait_op - wait for a flash operation to complete
* @adapter: the adapter
* @attempts: max number of polls of the status register
* @delay: delay between polls in ms
*
* Wait for a flash operation to complete by polling the status register.
*/
static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
{
int ret;
u32 status;
while (1) {
if ((ret = sf1_write(adapter, 1, 1, SF_RD_STATUS)) != 0 ||
(ret = sf1_read(adapter, 1, 0, &status)) != 0)
return ret;
if (!(status & 1))
return 0;
if (--attempts == 0)
return -EAGAIN;
if (delay)
msleep(delay);
}
}
/**
* t3_read_flash - read words from serial flash
* @adapter: the adapter
* @addr: the start address for the read
* @nwords: how many 32-bit words to read
* @data: where to store the read data
* @byte_oriented: whether to store data as bytes or as words
*
* Read the specified number of 32-bit words from the serial flash.
* If @byte_oriented is set the read data is stored as a byte array
* (i.e., big-endian), otherwise as 32-bit words in the platform's
* natural endianness.
*/
static int t3_read_flash(struct adapter *adapter, unsigned int addr,
unsigned int nwords, u32 *data, int byte_oriented)
{
int ret;
if (addr + nwords * sizeof(u32) > SF_SIZE || (addr & 3))
return -EINVAL;
addr = swab32(addr) | SF_RD_DATA_FAST;
if ((ret = sf1_write(adapter, 4, 1, addr)) != 0 ||
(ret = sf1_read(adapter, 1, 1, data)) != 0)
return ret;
for (; nwords; nwords--, data++) {
ret = sf1_read(adapter, 4, nwords > 1, data);
if (ret)
return ret;
if (byte_oriented)
*data = htonl(*data);
}
return 0;
}
/**
* t3_write_flash - write up to a page of data to the serial flash
* @adapter: the adapter
* @addr: the start address to write
* @n: length of data to write
* @data: the data to write
*
* Writes up to a page of data (256 bytes) to the serial flash starting
* at the given address.
*/
static int t3_write_flash(struct adapter *adapter, unsigned int addr,
unsigned int n, const u8 *data)
{
int ret;
u32 buf[64];
unsigned int i, c, left, val, offset = addr & 0xff;
if (addr + n > SF_SIZE || offset + n > 256)
return -EINVAL;
val = swab32(addr) | SF_PROG_PAGE;
if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
(ret = sf1_write(adapter, 4, 1, val)) != 0)
return ret;
for (left = n; left; left -= c) {
c = min(left, 4U);
for (val = 0, i = 0; i < c; ++i)
val = (val << 8) + *data++;
ret = sf1_write(adapter, c, c != left, val);
if (ret)
return ret;
}
if ((ret = flash_wait_op(adapter, 5, 1)) != 0)
return ret;
/* Read the page to verify the write succeeded */
ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
if (ret)
return ret;
if (memcmp(data - n, (u8 *) buf + offset, n))
return -EIO;
return 0;
}
/**
* t3_get_tp_version - read the tp sram version
* @adapter: the adapter
* @vers: where to place the version
*
* Reads the protocol sram version from sram.
*/
int t3_get_tp_version(struct adapter *adapter, u32 *vers)
{
int ret;
/* Get version loaded in SRAM */
t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0);
ret = t3_wait_op_done(adapter, A_TP_EMBED_OP_FIELD0,
1, 1, 5, 1);
if (ret)
return ret;
*vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
return 0;
}
/**
* t3_check_tpsram_version - read the tp sram version
* @adapter: the adapter
*
* Reads the protocol sram version from flash.
*/
int t3_check_tpsram_version(struct adapter *adapter)
{
int ret;
u32 vers;
unsigned int major, minor;
if (adapter->params.rev == T3_REV_A)
return 0;
ret = t3_get_tp_version(adapter, &vers);
if (ret)
return ret;
major = G_TP_VERSION_MAJOR(vers);
minor = G_TP_VERSION_MINOR(vers);
if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR)
return 0;
else {
CH_ERR(adapter, "found wrong TP version (%u.%u), "
"driver compiled for version %d.%d\n", major, minor,
TP_VERSION_MAJOR, TP_VERSION_MINOR);
}
return -EINVAL;
}
/**
* t3_check_tpsram - check if provided protocol SRAM
* is compatible with this driver
* @adapter: the adapter
* @tp_sram: the firmware image to write
* @size: image size
*
* Checks if an adapter's tp sram is compatible with the driver.
* Returns 0 if the versions are compatible, a negative error otherwise.
*/
int t3_check_tpsram(struct adapter *adapter, const u8 *tp_sram,
unsigned int size)
{
u32 csum;
unsigned int i;
const __be32 *p = (const __be32 *)tp_sram;
/* Verify checksum */
for (csum = 0, i = 0; i < size / sizeof(csum); i++)
csum += ntohl(p[i]);
if (csum != 0xffffffff) {
CH_ERR(adapter, "corrupted protocol SRAM image, checksum %u\n",
csum);
return -EINVAL;
}
return 0;
}
enum fw_version_type {
FW_VERSION_N3,
FW_VERSION_T3
};
/**
* t3_get_fw_version - read the firmware version
* @adapter: the adapter
* @vers: where to place the version
*
* Reads the FW version from flash.
*/
int t3_get_fw_version(struct adapter *adapter, u32 *vers)
{
return t3_read_flash(adapter, FW_VERS_ADDR, 1, vers, 0);
}
/**
* t3_check_fw_version - check if the FW is compatible with this driver
* @adapter: the adapter
*
* Checks if an adapter's FW is compatible with the driver. Returns 0
* if the versions are compatible, a negative error otherwise.
*/
int t3_check_fw_version(struct adapter *adapter)
{
int ret;
u32 vers;
unsigned int type, major, minor;