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qman.c
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qman.c
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/* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "qman_priv.h"
#define DQRR_MAXFILL 15
#define EQCR_ITHRESH 4 /* if EQCR congests, interrupt threshold */
#define IRQNAME "QMan portal %d"
#define MAX_IRQNAME 16 /* big enough for "QMan portal %d" */
#define QMAN_POLL_LIMIT 32
#define QMAN_PIRQ_DQRR_ITHRESH 12
#define QMAN_DQRR_IT_MAX 15
#define QMAN_ITP_MAX 0xFFF
#define QMAN_PIRQ_MR_ITHRESH 4
#define QMAN_PIRQ_IPERIOD 100
/* Portal register assists */
#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
/* Cache-inhibited register offsets */
#define QM_REG_EQCR_PI_CINH 0x3000
#define QM_REG_EQCR_CI_CINH 0x3040
#define QM_REG_EQCR_ITR 0x3080
#define QM_REG_DQRR_PI_CINH 0x3100
#define QM_REG_DQRR_CI_CINH 0x3140
#define QM_REG_DQRR_ITR 0x3180
#define QM_REG_DQRR_DCAP 0x31C0
#define QM_REG_DQRR_SDQCR 0x3200
#define QM_REG_DQRR_VDQCR 0x3240
#define QM_REG_DQRR_PDQCR 0x3280
#define QM_REG_MR_PI_CINH 0x3300
#define QM_REG_MR_CI_CINH 0x3340
#define QM_REG_MR_ITR 0x3380
#define QM_REG_CFG 0x3500
#define QM_REG_ISR 0x3600
#define QM_REG_IER 0x3640
#define QM_REG_ISDR 0x3680
#define QM_REG_IIR 0x36C0
#define QM_REG_ITPR 0x3740
/* Cache-enabled register offsets */
#define QM_CL_EQCR 0x0000
#define QM_CL_DQRR 0x1000
#define QM_CL_MR 0x2000
#define QM_CL_EQCR_PI_CENA 0x3000
#define QM_CL_EQCR_CI_CENA 0x3040
#define QM_CL_DQRR_PI_CENA 0x3100
#define QM_CL_DQRR_CI_CENA 0x3140
#define QM_CL_MR_PI_CENA 0x3300
#define QM_CL_MR_CI_CENA 0x3340
#define QM_CL_CR 0x3800
#define QM_CL_RR0 0x3900
#define QM_CL_RR1 0x3940
#else
/* Cache-inhibited register offsets */
#define QM_REG_EQCR_PI_CINH 0x0000
#define QM_REG_EQCR_CI_CINH 0x0004
#define QM_REG_EQCR_ITR 0x0008
#define QM_REG_DQRR_PI_CINH 0x0040
#define QM_REG_DQRR_CI_CINH 0x0044
#define QM_REG_DQRR_ITR 0x0048
#define QM_REG_DQRR_DCAP 0x0050
#define QM_REG_DQRR_SDQCR 0x0054
#define QM_REG_DQRR_VDQCR 0x0058
#define QM_REG_DQRR_PDQCR 0x005c
#define QM_REG_MR_PI_CINH 0x0080
#define QM_REG_MR_CI_CINH 0x0084
#define QM_REG_MR_ITR 0x0088
#define QM_REG_CFG 0x0100
#define QM_REG_ISR 0x0e00
#define QM_REG_IER 0x0e04
#define QM_REG_ISDR 0x0e08
#define QM_REG_IIR 0x0e0c
#define QM_REG_ITPR 0x0e14
/* Cache-enabled register offsets */
#define QM_CL_EQCR 0x0000
#define QM_CL_DQRR 0x1000
#define QM_CL_MR 0x2000
#define QM_CL_EQCR_PI_CENA 0x3000
#define QM_CL_EQCR_CI_CENA 0x3100
#define QM_CL_DQRR_PI_CENA 0x3200
#define QM_CL_DQRR_CI_CENA 0x3300
#define QM_CL_MR_PI_CENA 0x3400
#define QM_CL_MR_CI_CENA 0x3500
#define QM_CL_CR 0x3800
#define QM_CL_RR0 0x3900
#define QM_CL_RR1 0x3940
#endif
/*
* BTW, the drivers (and h/w programming model) already obtain the required
* synchronisation for portal accesses and data-dependencies. Use of barrier()s
* or other order-preserving primitives simply degrade performance. Hence the
* use of the __raw_*() interfaces, which simply ensure that the compiler treats
* the portal registers as volatile
*/
/* Cache-enabled ring access */
#define qm_cl(base, idx) ((void *)base + ((idx) << 6))
/*
* Portal modes.
* Enum types;
* pmode == production mode
* cmode == consumption mode,
* dmode == h/w dequeue mode.
* Enum values use 3 letter codes. First letter matches the portal mode,
* remaining two letters indicate;
* ci == cache-inhibited portal register
* ce == cache-enabled portal register
* vb == in-band valid-bit (cache-enabled)
* dc == DCA (Discrete Consumption Acknowledgment), DQRR-only
* As for "enum qm_dqrr_dmode", it should be self-explanatory.
*/
enum qm_eqcr_pmode { /* matches QCSP_CFG::EPM */
qm_eqcr_pci = 0, /* PI index, cache-inhibited */
qm_eqcr_pce = 1, /* PI index, cache-enabled */
qm_eqcr_pvb = 2 /* valid-bit */
};
enum qm_dqrr_dmode { /* matches QCSP_CFG::DP */
qm_dqrr_dpush = 0, /* SDQCR + VDQCR */
qm_dqrr_dpull = 1 /* PDQCR */
};
enum qm_dqrr_pmode { /* s/w-only */
qm_dqrr_pci, /* reads DQRR_PI_CINH */
qm_dqrr_pce, /* reads DQRR_PI_CENA */
qm_dqrr_pvb /* reads valid-bit */
};
enum qm_dqrr_cmode { /* matches QCSP_CFG::DCM */
qm_dqrr_cci = 0, /* CI index, cache-inhibited */
qm_dqrr_cce = 1, /* CI index, cache-enabled */
qm_dqrr_cdc = 2 /* Discrete Consumption Acknowledgment */
};
enum qm_mr_pmode { /* s/w-only */
qm_mr_pci, /* reads MR_PI_CINH */
qm_mr_pce, /* reads MR_PI_CENA */
qm_mr_pvb /* reads valid-bit */
};
enum qm_mr_cmode { /* matches QCSP_CFG::MM */
qm_mr_cci = 0, /* CI index, cache-inhibited */
qm_mr_cce = 1 /* CI index, cache-enabled */
};
/* --- Portal structures --- */
#define QM_EQCR_SIZE 8
#define QM_DQRR_SIZE 16
#define QM_MR_SIZE 8
/* "Enqueue Command" */
struct qm_eqcr_entry {
u8 _ncw_verb; /* writes to this are non-coherent */
u8 dca;
__be16 seqnum;
u8 __reserved[4];
__be32 fqid; /* 24-bit */
__be32 tag;
struct qm_fd fd;
u8 __reserved3[32];
} __packed __aligned(8);
#define QM_EQCR_VERB_VBIT 0x80
#define QM_EQCR_VERB_CMD_MASK 0x61 /* but only one value; */
#define QM_EQCR_VERB_CMD_ENQUEUE 0x01
#define QM_EQCR_SEQNUM_NESN 0x8000 /* Advance NESN */
#define QM_EQCR_SEQNUM_NLIS 0x4000 /* More fragments to come */
#define QM_EQCR_SEQNUM_SEQMASK 0x3fff /* sequence number goes here */
struct qm_eqcr {
struct qm_eqcr_entry *ring, *cursor;
u8 ci, available, ithresh, vbit;
#ifdef CONFIG_FSL_DPAA_CHECKING
u32 busy;
enum qm_eqcr_pmode pmode;
#endif
};
struct qm_dqrr {
const struct qm_dqrr_entry *ring, *cursor;
u8 pi, ci, fill, ithresh, vbit;
#ifdef CONFIG_FSL_DPAA_CHECKING
enum qm_dqrr_dmode dmode;
enum qm_dqrr_pmode pmode;
enum qm_dqrr_cmode cmode;
#endif
};
struct qm_mr {
union qm_mr_entry *ring, *cursor;
u8 pi, ci, fill, ithresh, vbit;
#ifdef CONFIG_FSL_DPAA_CHECKING
enum qm_mr_pmode pmode;
enum qm_mr_cmode cmode;
#endif
};
/* MC (Management Command) command */
/* "FQ" command layout */
struct qm_mcc_fq {
u8 _ncw_verb;
u8 __reserved1[3];
__be32 fqid; /* 24-bit */
u8 __reserved2[56];
} __packed;
/* "CGR" command layout */
struct qm_mcc_cgr {
u8 _ncw_verb;
u8 __reserved1[30];
u8 cgid;
u8 __reserved2[32];
};
#define QM_MCC_VERB_VBIT 0x80
#define QM_MCC_VERB_MASK 0x7f /* where the verb contains; */
#define QM_MCC_VERB_INITFQ_PARKED 0x40
#define QM_MCC_VERB_INITFQ_SCHED 0x41
#define QM_MCC_VERB_QUERYFQ 0x44
#define QM_MCC_VERB_QUERYFQ_NP 0x45 /* "non-programmable" fields */
#define QM_MCC_VERB_QUERYWQ 0x46
#define QM_MCC_VERB_QUERYWQ_DEDICATED 0x47
#define QM_MCC_VERB_ALTER_SCHED 0x48 /* Schedule FQ */
#define QM_MCC_VERB_ALTER_FE 0x49 /* Force Eligible FQ */
#define QM_MCC_VERB_ALTER_RETIRE 0x4a /* Retire FQ */
#define QM_MCC_VERB_ALTER_OOS 0x4b /* Take FQ out of service */
#define QM_MCC_VERB_ALTER_FQXON 0x4d /* FQ XON */
#define QM_MCC_VERB_ALTER_FQXOFF 0x4e /* FQ XOFF */
#define QM_MCC_VERB_INITCGR 0x50
#define QM_MCC_VERB_MODIFYCGR 0x51
#define QM_MCC_VERB_CGRTESTWRITE 0x52
#define QM_MCC_VERB_QUERYCGR 0x58
#define QM_MCC_VERB_QUERYCONGESTION 0x59
union qm_mc_command {
struct {
u8 _ncw_verb; /* writes to this are non-coherent */
u8 __reserved[63];
};
struct qm_mcc_initfq initfq;
struct qm_mcc_initcgr initcgr;
struct qm_mcc_fq fq;
struct qm_mcc_cgr cgr;
};
/* MC (Management Command) result */
/* "Query FQ" */
struct qm_mcr_queryfq {
u8 verb;
u8 result;
u8 __reserved1[8];
struct qm_fqd fqd; /* the FQD fields are here */
u8 __reserved2[30];
} __packed;
/* "Alter FQ State Commands" */
struct qm_mcr_alterfq {
u8 verb;
u8 result;
u8 fqs; /* Frame Queue Status */
u8 __reserved1[61];
};
#define QM_MCR_VERB_RRID 0x80
#define QM_MCR_VERB_MASK QM_MCC_VERB_MASK
#define QM_MCR_VERB_INITFQ_PARKED QM_MCC_VERB_INITFQ_PARKED
#define QM_MCR_VERB_INITFQ_SCHED QM_MCC_VERB_INITFQ_SCHED
#define QM_MCR_VERB_QUERYFQ QM_MCC_VERB_QUERYFQ
#define QM_MCR_VERB_QUERYFQ_NP QM_MCC_VERB_QUERYFQ_NP
#define QM_MCR_VERB_QUERYWQ QM_MCC_VERB_QUERYWQ
#define QM_MCR_VERB_QUERYWQ_DEDICATED QM_MCC_VERB_QUERYWQ_DEDICATED
#define QM_MCR_VERB_ALTER_SCHED QM_MCC_VERB_ALTER_SCHED
#define QM_MCR_VERB_ALTER_FE QM_MCC_VERB_ALTER_FE
#define QM_MCR_VERB_ALTER_RETIRE QM_MCC_VERB_ALTER_RETIRE
#define QM_MCR_VERB_ALTER_OOS QM_MCC_VERB_ALTER_OOS
#define QM_MCR_RESULT_NULL 0x00
#define QM_MCR_RESULT_OK 0xf0
#define QM_MCR_RESULT_ERR_FQID 0xf1
#define QM_MCR_RESULT_ERR_FQSTATE 0xf2
#define QM_MCR_RESULT_ERR_NOTEMPTY 0xf3 /* OOS fails if FQ is !empty */
#define QM_MCR_RESULT_ERR_BADCHANNEL 0xf4
#define QM_MCR_RESULT_PENDING 0xf8
#define QM_MCR_RESULT_ERR_BADCOMMAND 0xff
#define QM_MCR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */
#define QM_MCR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */
#define QM_MCR_TIMEOUT 10000 /* us */
union qm_mc_result {
struct {
u8 verb;
u8 result;
u8 __reserved1[62];
};
struct qm_mcr_queryfq queryfq;
struct qm_mcr_alterfq alterfq;
struct qm_mcr_querycgr querycgr;
struct qm_mcr_querycongestion querycongestion;
struct qm_mcr_querywq querywq;
struct qm_mcr_queryfq_np queryfq_np;
};
struct qm_mc {
union qm_mc_command *cr;
union qm_mc_result *rr;
u8 rridx, vbit;
#ifdef CONFIG_FSL_DPAA_CHECKING
enum {
/* Can be _mc_start()ed */
qman_mc_idle,
/* Can be _mc_commit()ed or _mc_abort()ed */
qman_mc_user,
/* Can only be _mc_retry()ed */
qman_mc_hw
} state;
#endif
};
struct qm_addr {
void *ce; /* cache-enabled */
__be32 *ce_be; /* same value as above but for direct access */
void __iomem *ci; /* cache-inhibited */
};
struct qm_portal {
/*
* In the non-CONFIG_FSL_DPAA_CHECKING case, the following stuff up to
* and including 'mc' fits within a cacheline (yay!). The 'config' part
* is setup-only, so isn't a cause for a concern. In other words, don't
* rearrange this structure on a whim, there be dragons ...
*/
struct qm_addr addr;
struct qm_eqcr eqcr;
struct qm_dqrr dqrr;
struct qm_mr mr;
struct qm_mc mc;
} ____cacheline_aligned;
/* Cache-inhibited register access. */
static inline u32 qm_in(struct qm_portal *p, u32 offset)
{
return ioread32be(p->addr.ci + offset);
}
static inline void qm_out(struct qm_portal *p, u32 offset, u32 val)
{
iowrite32be(val, p->addr.ci + offset);
}
/* Cache Enabled Portal Access */
static inline void qm_cl_invalidate(struct qm_portal *p, u32 offset)
{
dpaa_invalidate(p->addr.ce + offset);
}
static inline void qm_cl_touch_ro(struct qm_portal *p, u32 offset)
{
dpaa_touch_ro(p->addr.ce + offset);
}
static inline u32 qm_ce_in(struct qm_portal *p, u32 offset)
{
return be32_to_cpu(*(p->addr.ce_be + (offset/4)));
}
/* --- EQCR API --- */
#define EQCR_SHIFT ilog2(sizeof(struct qm_eqcr_entry))
#define EQCR_CARRY (uintptr_t)(QM_EQCR_SIZE << EQCR_SHIFT)
/* Bit-wise logic to wrap a ring pointer by clearing the "carry bit" */
static struct qm_eqcr_entry *eqcr_carryclear(struct qm_eqcr_entry *p)
{
uintptr_t addr = (uintptr_t)p;
addr &= ~EQCR_CARRY;
return (struct qm_eqcr_entry *)addr;
}
/* Bit-wise logic to convert a ring pointer to a ring index */
static int eqcr_ptr2idx(struct qm_eqcr_entry *e)
{
return ((uintptr_t)e >> EQCR_SHIFT) & (QM_EQCR_SIZE - 1);
}
/* Increment the 'cursor' ring pointer, taking 'vbit' into account */
static inline void eqcr_inc(struct qm_eqcr *eqcr)
{
/* increment to the next EQCR pointer and handle overflow and 'vbit' */
struct qm_eqcr_entry *partial = eqcr->cursor + 1;
eqcr->cursor = eqcr_carryclear(partial);
if (partial != eqcr->cursor)
eqcr->vbit ^= QM_EQCR_VERB_VBIT;
}
static inline int qm_eqcr_init(struct qm_portal *portal,
enum qm_eqcr_pmode pmode,
unsigned int eq_stash_thresh,
int eq_stash_prio)
{
struct qm_eqcr *eqcr = &portal->eqcr;
u32 cfg;
u8 pi;
eqcr->ring = portal->addr.ce + QM_CL_EQCR;
eqcr->ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
eqcr->cursor = eqcr->ring + pi;
eqcr->vbit = (qm_in(portal, QM_REG_EQCR_PI_CINH) & QM_EQCR_SIZE) ?
QM_EQCR_VERB_VBIT : 0;
eqcr->available = QM_EQCR_SIZE - 1 -
dpaa_cyc_diff(QM_EQCR_SIZE, eqcr->ci, pi);
eqcr->ithresh = qm_in(portal, QM_REG_EQCR_ITR);
#ifdef CONFIG_FSL_DPAA_CHECKING
eqcr->busy = 0;
eqcr->pmode = pmode;
#endif
cfg = (qm_in(portal, QM_REG_CFG) & 0x00ffffff) |
(eq_stash_thresh << 28) | /* QCSP_CFG: EST */
(eq_stash_prio << 26) | /* QCSP_CFG: EP */
((pmode & 0x3) << 24); /* QCSP_CFG::EPM */
qm_out(portal, QM_REG_CFG, cfg);
return 0;
}
static inline void qm_eqcr_finish(struct qm_portal *portal)
{
struct qm_eqcr *eqcr = &portal->eqcr;
u8 pi = qm_in(portal, QM_REG_EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
u8 ci = qm_in(portal, QM_REG_EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
DPAA_ASSERT(!eqcr->busy);
if (pi != eqcr_ptr2idx(eqcr->cursor))
pr_crit("losing uncommitted EQCR entries\n");
if (ci != eqcr->ci)
pr_crit("missing existing EQCR completions\n");
if (eqcr->ci != eqcr_ptr2idx(eqcr->cursor))
pr_crit("EQCR destroyed unquiesced\n");
}
static inline struct qm_eqcr_entry *qm_eqcr_start_no_stash(struct qm_portal
*portal)
{
struct qm_eqcr *eqcr = &portal->eqcr;
DPAA_ASSERT(!eqcr->busy);
if (!eqcr->available)
return NULL;
#ifdef CONFIG_FSL_DPAA_CHECKING
eqcr->busy = 1;
#endif
dpaa_zero(eqcr->cursor);
return eqcr->cursor;
}
static inline struct qm_eqcr_entry *qm_eqcr_start_stash(struct qm_portal
*portal)
{
struct qm_eqcr *eqcr = &portal->eqcr;
u8 diff, old_ci;
DPAA_ASSERT(!eqcr->busy);
if (!eqcr->available) {
old_ci = eqcr->ci;
eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) &
(QM_EQCR_SIZE - 1);
diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
eqcr->available += diff;
if (!diff)
return NULL;
}
#ifdef CONFIG_FSL_DPAA_CHECKING
eqcr->busy = 1;
#endif
dpaa_zero(eqcr->cursor);
return eqcr->cursor;
}
static inline void eqcr_commit_checks(struct qm_eqcr *eqcr)
{
DPAA_ASSERT(eqcr->busy);
DPAA_ASSERT(!(be32_to_cpu(eqcr->cursor->fqid) & ~QM_FQID_MASK));
DPAA_ASSERT(eqcr->available >= 1);
}
static inline void qm_eqcr_pvb_commit(struct qm_portal *portal, u8 myverb)
{
struct qm_eqcr *eqcr = &portal->eqcr;
struct qm_eqcr_entry *eqcursor;
eqcr_commit_checks(eqcr);
DPAA_ASSERT(eqcr->pmode == qm_eqcr_pvb);
dma_wmb();
eqcursor = eqcr->cursor;
eqcursor->_ncw_verb = myverb | eqcr->vbit;
dpaa_flush(eqcursor);
eqcr_inc(eqcr);
eqcr->available--;
#ifdef CONFIG_FSL_DPAA_CHECKING
eqcr->busy = 0;
#endif
}
static inline void qm_eqcr_cce_prefetch(struct qm_portal *portal)
{
qm_cl_touch_ro(portal, QM_CL_EQCR_CI_CENA);
}
static inline u8 qm_eqcr_cce_update(struct qm_portal *portal)
{
struct qm_eqcr *eqcr = &portal->eqcr;
u8 diff, old_ci = eqcr->ci;
eqcr->ci = qm_ce_in(portal, QM_CL_EQCR_CI_CENA) & (QM_EQCR_SIZE - 1);
qm_cl_invalidate(portal, QM_CL_EQCR_CI_CENA);
diff = dpaa_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
eqcr->available += diff;
return diff;
}
static inline void qm_eqcr_set_ithresh(struct qm_portal *portal, u8 ithresh)
{
struct qm_eqcr *eqcr = &portal->eqcr;
eqcr->ithresh = ithresh;
qm_out(portal, QM_REG_EQCR_ITR, ithresh);
}
static inline u8 qm_eqcr_get_avail(struct qm_portal *portal)
{
struct qm_eqcr *eqcr = &portal->eqcr;
return eqcr->available;
}
static inline u8 qm_eqcr_get_fill(struct qm_portal *portal)
{
struct qm_eqcr *eqcr = &portal->eqcr;
return QM_EQCR_SIZE - 1 - eqcr->available;
}
/* --- DQRR API --- */
#define DQRR_SHIFT ilog2(sizeof(struct qm_dqrr_entry))
#define DQRR_CARRY (uintptr_t)(QM_DQRR_SIZE << DQRR_SHIFT)
static const struct qm_dqrr_entry *dqrr_carryclear(
const struct qm_dqrr_entry *p)
{
uintptr_t addr = (uintptr_t)p;
addr &= ~DQRR_CARRY;
return (const struct qm_dqrr_entry *)addr;
}
static inline int dqrr_ptr2idx(const struct qm_dqrr_entry *e)
{
return ((uintptr_t)e >> DQRR_SHIFT) & (QM_DQRR_SIZE - 1);
}
static const struct qm_dqrr_entry *dqrr_inc(const struct qm_dqrr_entry *e)
{
return dqrr_carryclear(e + 1);
}
static inline void qm_dqrr_set_maxfill(struct qm_portal *portal, u8 mf)
{
qm_out(portal, QM_REG_CFG, (qm_in(portal, QM_REG_CFG) & 0xff0fffff) |
((mf & (QM_DQRR_SIZE - 1)) << 20));
}
static inline int qm_dqrr_init(struct qm_portal *portal,
const struct qm_portal_config *config,
enum qm_dqrr_dmode dmode,
enum qm_dqrr_pmode pmode,
enum qm_dqrr_cmode cmode, u8 max_fill)
{
struct qm_dqrr *dqrr = &portal->dqrr;
u32 cfg;
/* Make sure the DQRR will be idle when we enable */
qm_out(portal, QM_REG_DQRR_SDQCR, 0);
qm_out(portal, QM_REG_DQRR_VDQCR, 0);
qm_out(portal, QM_REG_DQRR_PDQCR, 0);
dqrr->ring = portal->addr.ce + QM_CL_DQRR;
dqrr->pi = qm_in(portal, QM_REG_DQRR_PI_CINH) & (QM_DQRR_SIZE - 1);
dqrr->ci = qm_in(portal, QM_REG_DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
dqrr->cursor = dqrr->ring + dqrr->ci;
dqrr->fill = dpaa_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi);
dqrr->vbit = (qm_in(portal, QM_REG_DQRR_PI_CINH) & QM_DQRR_SIZE) ?
QM_DQRR_VERB_VBIT : 0;
dqrr->ithresh = qm_in(portal, QM_REG_DQRR_ITR);
#ifdef CONFIG_FSL_DPAA_CHECKING
dqrr->dmode = dmode;
dqrr->pmode = pmode;
dqrr->cmode = cmode;
#endif
/* Invalidate every ring entry before beginning */
for (cfg = 0; cfg < QM_DQRR_SIZE; cfg++)
dpaa_invalidate(qm_cl(dqrr->ring, cfg));
cfg = (qm_in(portal, QM_REG_CFG) & 0xff000f00) |
((max_fill & (QM_DQRR_SIZE - 1)) << 20) | /* DQRR_MF */
((dmode & 1) << 18) | /* DP */
((cmode & 3) << 16) | /* DCM */
0xa0 | /* RE+SE */
(0 ? 0x40 : 0) | /* Ignore RP */
(0 ? 0x10 : 0); /* Ignore SP */
qm_out(portal, QM_REG_CFG, cfg);
qm_dqrr_set_maxfill(portal, max_fill);
return 0;
}
static inline void qm_dqrr_finish(struct qm_portal *portal)
{
#ifdef CONFIG_FSL_DPAA_CHECKING
struct qm_dqrr *dqrr = &portal->dqrr;
if (dqrr->cmode != qm_dqrr_cdc &&
dqrr->ci != dqrr_ptr2idx(dqrr->cursor))
pr_crit("Ignoring completed DQRR entries\n");
#endif
}
static inline const struct qm_dqrr_entry *qm_dqrr_current(
struct qm_portal *portal)
{
struct qm_dqrr *dqrr = &portal->dqrr;
if (!dqrr->fill)
return NULL;
return dqrr->cursor;
}
static inline u8 qm_dqrr_next(struct qm_portal *portal)
{
struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->fill);
dqrr->cursor = dqrr_inc(dqrr->cursor);
return --dqrr->fill;
}
static inline void qm_dqrr_pvb_update(struct qm_portal *portal)
{
struct qm_dqrr *dqrr = &portal->dqrr;
struct qm_dqrr_entry *res = qm_cl(dqrr->ring, dqrr->pi);
DPAA_ASSERT(dqrr->pmode == qm_dqrr_pvb);
#ifndef CONFIG_FSL_PAMU
/*
* If PAMU is not available we need to invalidate the cache.
* When PAMU is available the cache is updated by stash
*/
dpaa_invalidate_touch_ro(res);
#endif
if ((res->verb & QM_DQRR_VERB_VBIT) == dqrr->vbit) {
dqrr->pi = (dqrr->pi + 1) & (QM_DQRR_SIZE - 1);
if (!dqrr->pi)
dqrr->vbit ^= QM_DQRR_VERB_VBIT;
dqrr->fill++;
}
}
static inline void qm_dqrr_cdc_consume_1ptr(struct qm_portal *portal,
const struct qm_dqrr_entry *dq,
int park)
{
__maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
int idx = dqrr_ptr2idx(dq);
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
DPAA_ASSERT((dqrr->ring + idx) == dq);
DPAA_ASSERT(idx < QM_DQRR_SIZE);
qm_out(portal, QM_REG_DQRR_DCAP, (0 << 8) | /* DQRR_DCAP::S */
((park ? 1 : 0) << 6) | /* DQRR_DCAP::PK */
idx); /* DQRR_DCAP::DCAP_CI */
}
static inline void qm_dqrr_cdc_consume_n(struct qm_portal *portal, u32 bitmask)
{
__maybe_unused struct qm_dqrr *dqrr = &portal->dqrr;
DPAA_ASSERT(dqrr->cmode == qm_dqrr_cdc);
qm_out(portal, QM_REG_DQRR_DCAP, (1 << 8) | /* DQRR_DCAP::S */
(bitmask << 16)); /* DQRR_DCAP::DCAP_CI */
}
static inline void qm_dqrr_sdqcr_set(struct qm_portal *portal, u32 sdqcr)
{
qm_out(portal, QM_REG_DQRR_SDQCR, sdqcr);
}
static inline void qm_dqrr_vdqcr_set(struct qm_portal *portal, u32 vdqcr)
{
qm_out(portal, QM_REG_DQRR_VDQCR, vdqcr);
}
static inline int qm_dqrr_set_ithresh(struct qm_portal *portal, u8 ithresh)
{
if (ithresh > QMAN_DQRR_IT_MAX)
return -EINVAL;
qm_out(portal, QM_REG_DQRR_ITR, ithresh);
return 0;
}
/* --- MR API --- */
#define MR_SHIFT ilog2(sizeof(union qm_mr_entry))
#define MR_CARRY (uintptr_t)(QM_MR_SIZE << MR_SHIFT)
static union qm_mr_entry *mr_carryclear(union qm_mr_entry *p)
{
uintptr_t addr = (uintptr_t)p;
addr &= ~MR_CARRY;
return (union qm_mr_entry *)addr;
}
static inline int mr_ptr2idx(const union qm_mr_entry *e)
{
return ((uintptr_t)e >> MR_SHIFT) & (QM_MR_SIZE - 1);
}
static inline union qm_mr_entry *mr_inc(union qm_mr_entry *e)
{
return mr_carryclear(e + 1);
}
static inline int qm_mr_init(struct qm_portal *portal, enum qm_mr_pmode pmode,
enum qm_mr_cmode cmode)
{
struct qm_mr *mr = &portal->mr;
u32 cfg;
mr->ring = portal->addr.ce + QM_CL_MR;
mr->pi = qm_in(portal, QM_REG_MR_PI_CINH) & (QM_MR_SIZE - 1);
mr->ci = qm_in(portal, QM_REG_MR_CI_CINH) & (QM_MR_SIZE - 1);
mr->cursor = mr->ring + mr->ci;
mr->fill = dpaa_cyc_diff(QM_MR_SIZE, mr->ci, mr->pi);
mr->vbit = (qm_in(portal, QM_REG_MR_PI_CINH) & QM_MR_SIZE)
? QM_MR_VERB_VBIT : 0;
mr->ithresh = qm_in(portal, QM_REG_MR_ITR);
#ifdef CONFIG_FSL_DPAA_CHECKING
mr->pmode = pmode;
mr->cmode = cmode;
#endif
cfg = (qm_in(portal, QM_REG_CFG) & 0xfffff0ff) |
((cmode & 1) << 8); /* QCSP_CFG:MM */
qm_out(portal, QM_REG_CFG, cfg);
return 0;
}
static inline void qm_mr_finish(struct qm_portal *portal)
{
struct qm_mr *mr = &portal->mr;
if (mr->ci != mr_ptr2idx(mr->cursor))
pr_crit("Ignoring completed MR entries\n");
}
static inline const union qm_mr_entry *qm_mr_current(struct qm_portal *portal)
{
struct qm_mr *mr = &portal->mr;
if (!mr->fill)
return NULL;
return mr->cursor;
}
static inline int qm_mr_next(struct qm_portal *portal)
{
struct qm_mr *mr = &portal->mr;
DPAA_ASSERT(mr->fill);
mr->cursor = mr_inc(mr->cursor);
return --mr->fill;
}
static inline void qm_mr_pvb_update(struct qm_portal *portal)
{
struct qm_mr *mr = &portal->mr;
union qm_mr_entry *res = qm_cl(mr->ring, mr->pi);
DPAA_ASSERT(mr->pmode == qm_mr_pvb);
if ((res->verb & QM_MR_VERB_VBIT) == mr->vbit) {
mr->pi = (mr->pi + 1) & (QM_MR_SIZE - 1);
if (!mr->pi)
mr->vbit ^= QM_MR_VERB_VBIT;
mr->fill++;
res = mr_inc(res);
}
dpaa_invalidate_touch_ro(res);
}
static inline void qm_mr_cci_consume(struct qm_portal *portal, u8 num)
{
struct qm_mr *mr = &portal->mr;
DPAA_ASSERT(mr->cmode == qm_mr_cci);
mr->ci = (mr->ci + num) & (QM_MR_SIZE - 1);
qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
}
static inline void qm_mr_cci_consume_to_current(struct qm_portal *portal)
{
struct qm_mr *mr = &portal->mr;
DPAA_ASSERT(mr->cmode == qm_mr_cci);
mr->ci = mr_ptr2idx(mr->cursor);
qm_out(portal, QM_REG_MR_CI_CINH, mr->ci);
}
static inline void qm_mr_set_ithresh(struct qm_portal *portal, u8 ithresh)
{
qm_out(portal, QM_REG_MR_ITR, ithresh);
}
/* --- Management command API --- */
static inline int qm_mc_init(struct qm_portal *portal)
{
u8 rr0, rr1;
struct qm_mc *mc = &portal->mc;
mc->cr = portal->addr.ce + QM_CL_CR;
mc->rr = portal->addr.ce + QM_CL_RR0;
/*
* The expected valid bit polarity for the next CR command is 0
* if RR1 contains a valid response, and is 1 if RR0 contains a
* valid response. If both RR contain all 0, this indicates either
* that no command has been executed since reset (in which case the
* expected valid bit polarity is 1)
*/
rr0 = mc->rr->verb;
rr1 = (mc->rr+1)->verb;
if ((rr0 == 0 && rr1 == 0) || rr0 != 0)
mc->rridx = 1;
else
mc->rridx = 0;
mc->vbit = mc->rridx ? QM_MCC_VERB_VBIT : 0;
#ifdef CONFIG_FSL_DPAA_CHECKING
mc->state = qman_mc_idle;
#endif
return 0;
}
static inline void qm_mc_finish(struct qm_portal *portal)
{
#ifdef CONFIG_FSL_DPAA_CHECKING
struct qm_mc *mc = &portal->mc;
DPAA_ASSERT(mc->state == qman_mc_idle);
if (mc->state != qman_mc_idle)
pr_crit("Losing incomplete MC command\n");
#endif
}
static inline union qm_mc_command *qm_mc_start(struct qm_portal *portal)
{
struct qm_mc *mc = &portal->mc;
DPAA_ASSERT(mc->state == qman_mc_idle);
#ifdef CONFIG_FSL_DPAA_CHECKING
mc->state = qman_mc_user;
#endif
dpaa_zero(mc->cr);
return mc->cr;
}
static inline void qm_mc_commit(struct qm_portal *portal, u8 myverb)
{
struct qm_mc *mc = &portal->mc;
union qm_mc_result *rr = mc->rr + mc->rridx;
DPAA_ASSERT(mc->state == qman_mc_user);
dma_wmb();
mc->cr->_ncw_verb = myverb | mc->vbit;
dpaa_flush(mc->cr);
dpaa_invalidate_touch_ro(rr);
#ifdef CONFIG_FSL_DPAA_CHECKING
mc->state = qman_mc_hw;
#endif
}
static inline union qm_mc_result *qm_mc_result(struct qm_portal *portal)
{
struct qm_mc *mc = &portal->mc;
union qm_mc_result *rr = mc->rr + mc->rridx;
DPAA_ASSERT(mc->state == qman_mc_hw);
/*
* The inactive response register's verb byte always returns zero until
* its command is submitted and completed. This includes the valid-bit,
* in case you were wondering...
*/
if (!rr->verb) {
dpaa_invalidate_touch_ro(rr);
return NULL;
}
mc->rridx ^= 1;
mc->vbit ^= QM_MCC_VERB_VBIT;
#ifdef CONFIG_FSL_DPAA_CHECKING
mc->state = qman_mc_idle;
#endif
return rr;
}
static inline int qm_mc_result_timeout(struct qm_portal *portal,
union qm_mc_result **mcr)
{
int timeout = QM_MCR_TIMEOUT;
do {
*mcr = qm_mc_result(portal);
if (*mcr)
break;
udelay(1);
} while (--timeout);
return timeout;
}
static inline void fq_set(struct qman_fq *fq, u32 mask)
{
fq->flags |= mask;
}
static inline void fq_clear(struct qman_fq *fq, u32 mask)
{
fq->flags &= ~mask;
}
static inline int fq_isset(struct qman_fq *fq, u32 mask)
{
return fq->flags & mask;
}
static inline int fq_isclear(struct qman_fq *fq, u32 mask)
{
return !(fq->flags & mask);
}
struct qman_portal {
struct qm_portal p;
/* PORTAL_BITS_*** - dynamic, strictly internal */
unsigned long bits;
/* interrupt sources processed by portal_isr(), configurable */
unsigned long irq_sources;
u32 use_eqcr_ci_stashing;
/* only 1 volatile dequeue at a time */
struct qman_fq *vdqcr_owned;
u32 sdqcr;
/* probing time config params for cpu-affine portals */
const struct qm_portal_config *config;
/* 2-element array. cgrs[0] is mask, cgrs[1] is snapshot. */
struct qman_cgrs *cgrs;
/* linked-list of CSCN handlers. */
struct list_head cgr_cbs;
/* list lock */
spinlock_t cgr_lock;
struct work_struct congestion_work;
struct work_struct mr_work;
char irqname[MAX_IRQNAME];
};
static cpumask_t affine_mask;