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omap4-l4.dtsi
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omap4-l4.dtsi
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// SPDX-License-Identifier: GPL-2.0
&l4_cfg { /* 0x4a000000 */
compatible = "ti,omap4-l4-cfg", "simple-bus";
reg = <0x4a000000 0x800>,
<0x4a000800 0x800>,
<0x4a001000 0x1000>;
reg-names = "ap", "la", "ia0";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
<0x00080000 0x4a080000 0x080000>, /* segment 1 */
<0x00100000 0x4a100000 0x080000>, /* segment 2 */
<0x00180000 0x4a180000 0x080000>, /* segment 3 */
<0x00200000 0x4a200000 0x080000>, /* segment 4 */
<0x00280000 0x4a280000 0x080000>, /* segment 5 */
<0x00300000 0x4a300000 0x080000>; /* segment 6 */
segment@0 { /* 0x4a000000 */
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
<0x00001000 0x00001000 0x001000>, /* ap 1 */
<0x00000800 0x00000800 0x000800>, /* ap 2 */
<0x00002000 0x00002000 0x001000>, /* ap 3 */
<0x00003000 0x00003000 0x001000>, /* ap 4 */
<0x00004000 0x00004000 0x001000>, /* ap 5 */
<0x00005000 0x00005000 0x001000>, /* ap 6 */
<0x00056000 0x00056000 0x001000>, /* ap 7 */
<0x00057000 0x00057000 0x001000>, /* ap 8 */
<0x0005c000 0x0005c000 0x001000>, /* ap 9 */
<0x00058000 0x00058000 0x004000>, /* ap 10 */
<0x00062000 0x00062000 0x001000>, /* ap 11 */
<0x00063000 0x00063000 0x001000>, /* ap 12 */
<0x00008000 0x00008000 0x002000>, /* ap 23 */
<0x0000a000 0x0000a000 0x001000>, /* ap 24 */
<0x00066000 0x00066000 0x001000>, /* ap 25 */
<0x00067000 0x00067000 0x001000>, /* ap 26 */
<0x0005e000 0x0005e000 0x002000>, /* ap 80 */
<0x00060000 0x00060000 0x001000>, /* ap 81 */
<0x00064000 0x00064000 0x001000>, /* ap 86 */
<0x00065000 0x00065000 0x001000>; /* ap 87 */
target-module@2000 { /* 0x4a002000, ap 3 06.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "ctrl_module_core";
reg = <0x2000 0x4>,
<0x2010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2000 0x1000>;
omap4_scm_core: scm@0 {
compatible = "ti,omap4-scm-core", "simple-bus";
reg = <0x0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x1000>;
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
};
omap_control_usb2phy: control-phy@300 {
compatible = "ti,control-phy-usb2";
reg = <0x300 0x4>;
reg-names = "power";
};
omap_control_usbotg: control-phy@33c {
compatible = "ti,control-phy-otghs";
reg = <0x33c 0x4>;
reg-names = "otghs_control";
};
};
};
target-module@4000 { /* 0x4a004000, ap 5 02.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x4000 0x4>;
reg-names = "rev";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4000 0x1000>;
cm1: cm1@0 {
compatible = "ti,omap4-cm1", "simple-bus";
reg = <0x0 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x2000>;
cm1_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm1_clockdomains: clockdomains {
};
};
};
target-module@8000 { /* 0x4a008000, ap 23 32.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x8000 0x4>;
reg-names = "rev";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x8000 0x2000>;
cm2: cm2@0 {
compatible = "ti,omap4-cm2", "simple-bus";
reg = <0x0 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x2000>;
cm2_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm2_clockdomains: clockdomains {
};
};
};
target-module@56000 { /* 0x4a056000, ap 7 0a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x56000 0x4>,
<0x5602c 0x4>,
<0x56028 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (V, P, C): core, core_pwrdm, l3_dma_clkdm */
clocks = <&l3_dma_clkctrl OMAP4_DMA_SYSTEM_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x56000 0x1000>;
sdma: dma-controller@0 {
compatible = "ti,omap4430-sdma", "ti,omap-sdma";
reg = <0x0 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
dma-channels = <32>;
dma-requests = <127>;
};
};
target-module@58000 { /* 0x4a058000, ap 10 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x58000 0x4>,
<0x58010 0x4>,
<0x58014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x58000 0x5000>;
hsi: hsi@0 {
compatible = "ti,omap4-hsi";
reg = <0x0 0x4000>,
<0x5000 0x1000>;
reg-names = "sys", "gdd";
clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
clock-names = "hsi_fck";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gdd_mpu";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x4000>;
hsi_port1: hsi-port@2000 {
compatible = "ti,omap4-hsi-port";
reg = <0x2000 0x800>,
<0x2800 0x800>;
reg-names = "tx", "rx";
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
};
hsi_port2: hsi-port@3000 {
compatible = "ti,omap4-hsi-port";
reg = <0x3000 0x800>,
<0x3800 0x800>;
reg-names = "tx", "rx";
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x5e000 0x2000>;
};
target-module@62000 { /* 0x4a062000, ap 11 16.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x62000 0x4>,
<0x62010 0x4>,
<0x62014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
clocks = <&l3_init_clkctrl OMAP4_USB_TLL_HS_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x62000 0x1000>;
usbhstll: usbhstll@0 {
compatible = "ti,usbhs-tll";
reg = <0x0 0x1000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@64000 { /* 0x4a064000, ap 86 1e.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x64000 0x4>,
<0x64010 0x4>,
<0x64014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
clocks = <&l3_init_clkctrl OMAP4_USB_HOST_HS_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x64000 0x1000>;
usbhshost: usbhshost@0 {
compatible = "ti,usbhs-host";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x1000>;
clocks = <&init_60m_fclk>,
<&xclk60mhsp1_ck>,
<&xclk60mhsp2_ck>;
clock-names = "refclk_60m_int",
"refclk_60m_ext_p1",
"refclk_60m_ext_p2";
usbhsohci: ohci@800 {
compatible = "ti,ohci-omap3";
reg = <0x800 0x400>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
remote-wakeup-connected;
};
usbhsehci: ehci@c00 {
compatible = "ti,ehci-omap";
reg = <0xc00 0x400>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
target-module@66000 { /* 0x4a066000, ap 25 26.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x66000 0x4>,
<0x66010 0x4>,
<0x66014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): iva, tesla_pwrdm, tesla_clkdm */
clocks = <&tesla_clkctrl OMAP4_DSP_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_tesla 1>;
reset-names = "rstctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x66000 0x1000>;
mmu_dsp: mmu@0 {
compatible = "ti,omap4-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
};
};
};
segment@80000 { /* 0x4a080000 */
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
<0x0005a000 0x000da000 0x001000>, /* ap 14 */
<0x0005b000 0x000db000 0x001000>, /* ap 15 */
<0x0005c000 0x000dc000 0x001000>, /* ap 16 */
<0x0005d000 0x000dd000 0x001000>, /* ap 17 */
<0x0005e000 0x000de000 0x001000>, /* ap 18 */
<0x00060000 0x000e0000 0x001000>, /* ap 19 */
<0x00061000 0x000e1000 0x001000>, /* ap 20 */
<0x00074000 0x000f4000 0x001000>, /* ap 27 */
<0x00075000 0x000f5000 0x001000>, /* ap 28 */
<0x00076000 0x000f6000 0x001000>, /* ap 29 */
<0x00077000 0x000f7000 0x001000>, /* ap 30 */
<0x00036000 0x000b6000 0x001000>, /* ap 69 */
<0x00037000 0x000b7000 0x001000>, /* ap 70 */
<0x0004d000 0x000cd000 0x001000>, /* ap 78 */
<0x0004e000 0x000ce000 0x001000>, /* ap 79 */
<0x00029000 0x000a9000 0x001000>, /* ap 82 */
<0x0002a000 0x000aa000 0x001000>, /* ap 83 */
<0x0002b000 0x000ab000 0x001000>, /* ap 84 */
<0x0002c000 0x000ac000 0x001000>, /* ap 85 */
<0x0002d000 0x000ad000 0x001000>, /* ap 88 */
<0x0002e000 0x000ae000 0x001000>; /* ap 89 */
target-module@29000 { /* 0x4a0a9000, ap 82 04.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x29000 0x1000>;
};
target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2b400 0x4>,
<0x2b404 0x4>,
<0x2b408 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2b000 0x1000>;
usb_otg_hs: usb_otg_hs@0 {
compatible = "ti,omap4-musb";
reg = <0x0 0x7ff>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc", "dma";
usb-phy = <&usb2_phy>;
phys = <&usb2_phy>;
phy-names = "usb2-phy";
multipoint = <1>;
num-eps = <16>;
ram-bits = <12>;
ctrl-module = <&omap_control_usbotg>;
};
};
target-module@2d000 { /* 0x4a0ad000, ap 88 0c.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2d000 0x4>,
<0x2d010 0x4>,
<0x2d014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (V, P, C): core, l3init_pwrdm, l3_init_clkdm */
clocks = <&l3_init_clkctrl OMAP4_OCP2SCP_USB_PHY_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2d000 0x1000>;
ocp2scp@0 {
compatible = "ti,omap-ocp2scp";
reg = <0x0 0x1f>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x1000>;
usb2_phy: usb2phy@80 {
compatible = "ti,omap-usb2";
reg = <0x80 0x58>;
ctrl-module = <&omap_control_usb2phy>;
clocks = <&usb_phy_cm_clk32k>;
clock-names = "wkupclk";
#phy-cells = <0>;
};
};
};
/* d2d mdm */
target-module@36000 { /* 0x4a0b6000, ap 69 60.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x36000 0x4>,
<0x36010 0x4>,
<0x36014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x36000 0x1000>;
};
/* d2d mpu */
target-module@4d000 { /* 0x4a0cd000, ap 78 58.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4d000 0x4>,
<0x4d010 0x4>,
<0x4d014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (V, P, C): core, core_pwrdm, d2d_clkdm */
clocks = <&d2d_clkctrl OMAP4_C2C_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4d000 0x1000>;
};
target-module@59000 { /* 0x4a0d9000, ap 13 1a.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
reg = <0x59038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_MPU_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x59000 0x1000>;
smartreflex_mpu: smartreflex@0 {
compatible = "ti,omap4-smartreflex-mpu";
reg = <0x0 0x80>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@5b000 { /* 0x4a0db000, ap 15 08.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
reg = <0x5b038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_IVA_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x5b000 0x1000>;
smartreflex_iva: smartreflex@0 {
compatible = "ti,omap4-smartreflex-iva";
reg = <0x0 0x80>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@5d000 { /* 0x4a0dd000, ap 17 22.0 */
compatible = "ti,sysc-omap4-sr", "ti,sysc";
reg = <0x5d038 0x4>;
reg-names = "sysc";
ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): core, always_on_core_pwrdm, l4_ao_clkdm */
clocks = <&l4_ao_clkctrl OMAP4_SMARTREFLEX_CORE_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x5d000 0x1000>;
smartreflex_core: smartreflex@0 {
compatible = "ti,omap4-smartreflex-core";
reg = <0x0 0x80>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
};
};
target-module@60000 { /* 0x4a0e0000, ap 19 1c.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x60000 0x1000>;
};
target-module@74000 { /* 0x4a0f4000, ap 27 24.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x74000 0x4>,
<0x74010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
clocks = <&l4_cfg_clkctrl OMAP4_MAILBOX_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x74000 0x1000>;
mailbox: mailbox@0 {
compatible = "ti,omap4-mailbox";
reg = <0x0 0x200>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
#mbox-cells = <1>;
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
mbox_ipu: mbox-ipu {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
mbox_dsp: mbox-dsp {
ti,mbox-tx = <3 0 0>;
ti,mbox-rx = <2 0 0>;
};
};
};
target-module@76000 { /* 0x4a0f6000, ap 29 3a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x76000 0x4>,
<0x76010 0x4>,
<0x76014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
clocks = <&l4_cfg_clkctrl OMAP4_SPINLOCK_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x76000 0x1000>;
hwspinlock: spinlock@0 {
compatible = "ti,omap4-hwspinlock";
reg = <0x0 0x1000>;
#hwlock-cells = <1>;
};
};
};
segment@100000 { /* 0x4a100000 */
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00100000 0x001000>, /* ap 21 */
<0x00001000 0x00101000 0x001000>, /* ap 22 */
<0x00002000 0x00102000 0x001000>, /* ap 61 */
<0x00003000 0x00103000 0x001000>, /* ap 62 */
<0x00008000 0x00108000 0x001000>, /* ap 63 */
<0x00009000 0x00109000 0x001000>, /* ap 64 */
<0x0000a000 0x0010a000 0x001000>, /* ap 65 */
<0x0000b000 0x0010b000 0x001000>; /* ap 66 */
target-module@0 { /* 0x4a100000, ap 21 2a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "ctrl_module_pad_core";
reg = <0x0 0x4>,
<0x10 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): core, core_pwrdm, l4_cfg_clkdm */
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x1000>;
omap4_pmx_core: pinmux@40 {
compatible = "ti,omap4-padconf",
"pinctrl-single";
reg = <0x40 0x0196>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
omap4_padconf_global: omap4_padconf_global@5a0 {
compatible = "syscon",
"simple-bus";
reg = <0x5a0 0x170>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5a0 0x170>;
pbias_regulator: pbias_regulator@60 {
compatible = "ti,pbias-omap4", "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap4_padconf_global>;
pbias_mmc_reg: pbias_mmc_omap4 {
regulator-name = "pbias_mmc_omap4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
};
};
target-module@2000 { /* 0x4a102000, ap 61 3c.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2000 0x1000>;
};
target-module@8000 { /* 0x4a108000, ap 63 62.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x8000 0x1000>;
};
target-module@a000 { /* 0x4a10a000, ap 65 50.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xa000 0x4>,
<0xa010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-delay-us = <2>;
/* Domains (V, P, C): core, cam_pwrdm, iss_clkdm */
clocks = <&iss_clkctrl OMAP4_FDIF_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xa000 0x1000>;
/* No child device binding or driver in mainline */
};
};
segment@180000 { /* 0x4a180000 */
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
segment@200000 { /* 0x4a200000 */
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 31 */
<0x0001f000 0x0021f000 0x001000>, /* ap 32 */
<0x0000a000 0x0020a000 0x001000>, /* ap 33 */
<0x0000b000 0x0020b000 0x001000>, /* ap 34 */
<0x00004000 0x00204000 0x001000>, /* ap 35 */
<0x00005000 0x00205000 0x001000>, /* ap 36 */
<0x00006000 0x00206000 0x001000>, /* ap 37 */
<0x00007000 0x00207000 0x001000>, /* ap 38 */
<0x00012000 0x00212000 0x001000>, /* ap 39 */
<0x00013000 0x00213000 0x001000>, /* ap 40 */
<0x0000c000 0x0020c000 0x001000>, /* ap 41 */
<0x0000d000 0x0020d000 0x001000>, /* ap 42 */
<0x00010000 0x00210000 0x001000>, /* ap 43 */
<0x00011000 0x00211000 0x001000>, /* ap 44 */
<0x00016000 0x00216000 0x001000>, /* ap 45 */
<0x00017000 0x00217000 0x001000>, /* ap 46 */
<0x00014000 0x00214000 0x001000>, /* ap 47 */
<0x00015000 0x00215000 0x001000>, /* ap 48 */
<0x00018000 0x00218000 0x001000>, /* ap 49 */
<0x00019000 0x00219000 0x001000>, /* ap 50 */
<0x00020000 0x00220000 0x001000>, /* ap 51 */
<0x00021000 0x00221000 0x001000>, /* ap 52 */
<0x00026000 0x00226000 0x001000>, /* ap 53 */
<0x00027000 0x00227000 0x001000>, /* ap 54 */
<0x00028000 0x00228000 0x001000>, /* ap 55 */
<0x00029000 0x00229000 0x001000>, /* ap 56 */
<0x0002a000 0x0022a000 0x001000>, /* ap 57 */
<0x0002b000 0x0022b000 0x001000>, /* ap 58 */
<0x0001c000 0x0021c000 0x001000>, /* ap 59 */
<0x0001d000 0x0021d000 0x001000>; /* ap 60 */
target-module@4000 { /* 0x4a204000, ap 35 42.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4000 0x1000>;
};
target-module@6000 { /* 0x4a206000, ap 37 4a.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x6000 0x1000>;
};
target-module@a000 { /* 0x4a20a000, ap 33 2c.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xa000 0x1000>;
};
target-module@c000 { /* 0x4a20c000, ap 41 20.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xc000 0x1000>;
};
target-module@10000 { /* 0x4a210000, ap 43 52.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x10000 0x1000>;
};
target-module@12000 { /* 0x4a212000, ap 39 18.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x12000 0x1000>;
};
target-module@14000 { /* 0x4a214000, ap 47 30.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x14000 0x1000>;
};
target-module@16000 { /* 0x4a216000, ap 45 28.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x16000 0x1000>;
};
target-module@18000 { /* 0x4a218000, ap 49 38.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x18000 0x1000>;
};
target-module@1c000 { /* 0x4a21c000, ap 59 5a.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1c000 0x1000>;
};
target-module@1e000 { /* 0x4a21e000, ap 31 10.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e000 0x1000>;
};
target-module@20000 { /* 0x4a220000, ap 51 40.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20000 0x1000>;
};
target-module@26000 { /* 0x4a226000, ap 53 34.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x26000 0x1000>;
};
target-module@28000 { /* 0x4a228000, ap 55 2e.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x28000 0x1000>;
};
target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2a000 0x1000>;
};
};
segment@280000 { /* 0x4a280000 */
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
};
l4_cfg_segment_300000: segment@300000 { /* 0x4a300000 */
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
<0x00040000 0x00340000 0x001000>, /* ap 68 */
<0x00020000 0x00320000 0x004000>, /* ap 71 */
<0x00024000 0x00324000 0x002000>, /* ap 72 */
<0x00026000 0x00326000 0x001000>, /* ap 73 */
<0x00027000 0x00327000 0x001000>, /* ap 74 */
<0x00028000 0x00328000 0x001000>, /* ap 75 */
<0x00029000 0x00329000 0x001000>, /* ap 76 */
<0x00030000 0x00330000 0x010000>, /* ap 77 */
<0x0002a000 0x0032a000 0x002000>, /* ap 90 */
<0x0002c000 0x0032c000 0x004000>; /* ap 91 */
l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x00020000>,
<0x00020000 0x00020000 0x00004000>,
<0x00024000 0x00024000 0x00002000>,
<0x00026000 0x00026000 0x00001000>,
<0x00027000 0x00027000 0x00001000>,
<0x00028000 0x00028000 0x00001000>,
<0x00029000 0x00029000 0x00001000>,
<0x0002a000 0x0002a000 0x00002000>,
<0x0002c000 0x0002c000 0x00004000>,
<0x00030000 0x00030000 0x00010000>;
};
};
};
&l4_wkup { /* 0x4a300000 */
compatible = "ti,omap4-l4-wkup", "simple-bus";
reg = <0x4a300000 0x800>,
<0x4a300800 0x800>,
<0x4a301000 0x1000>;
reg-names = "ap", "la", "ia0";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x4a300000 0x010000>, /* segment 0 */
<0x00010000 0x4a310000 0x010000>, /* segment 1 */
<0x00020000 0x4a320000 0x010000>; /* segment 2 */
segment@0 { /* 0x4a300000 */
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
<0x00001000 0x00001000 0x001000>, /* ap 1 */
<0x00000800 0x00000800 0x000800>, /* ap 2 */
<0x00006000 0x00006000 0x002000>, /* ap 3 */
<0x00008000 0x00008000 0x001000>, /* ap 4 */
<0x0000a000 0x0000a000 0x001000>, /* ap 15 */
<0x0000b000 0x0000b000 0x001000>, /* ap 16 */
<0x00004000 0x00004000 0x001000>, /* ap 17 */
<0x00005000 0x00005000 0x001000>, /* ap 18 */
<0x0000c000 0x0000c000 0x001000>, /* ap 19 */
<0x0000d000 0x0000d000 0x001000>; /* ap 20 */
target-module@4000 { /* 0x4a304000, ap 17 24.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4000 0x4>,
<0x4004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
/* Domains (V, P, C): wakeup, wkup_pwrdm, l4_wkup_clkdm */
clocks = <&l4_wkup_clkctrl OMAP4_COUNTER_32K_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4000 0x1000>;
counter32k: counter@0 {
compatible = "ti,omap-counter32k";
reg = <0x0 0x20>;
};
};
target-module@6000 { /* 0x4a306000, ap 3 08.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x6000 0x4>;
reg-names = "rev";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x6000 0x2000>;