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udc-xilinx.c
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udc-xilinx.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx USB peripheral controller driver
*
* Copyright (C) 2004 by Thomas Rathbone
* Copyright (C) 2005 by HP Labs
* Copyright (C) 2005 by David Brownell
* Copyright (C) 2010 - 2014 Xilinx, Inc.
*
* Some parts of this driver code is based on the driver for at91-series
* USB peripheral controller (at91_udc.c).
*/
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/of_irq.h>
#include <linux/prefetch.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
/* Register offsets for the USB device.*/
#define XUSB_EP0_CONFIG_OFFSET 0x0000 /* EP0 Config Reg Offset */
#define XUSB_SETUP_PKT_ADDR_OFFSET 0x0080 /* Setup Packet Address */
#define XUSB_ADDRESS_OFFSET 0x0100 /* Address Register */
#define XUSB_CONTROL_OFFSET 0x0104 /* Control Register */
#define XUSB_STATUS_OFFSET 0x0108 /* Status Register */
#define XUSB_FRAMENUM_OFFSET 0x010C /* Frame Number Register */
#define XUSB_IER_OFFSET 0x0110 /* Interrupt Enable Register */
#define XUSB_BUFFREADY_OFFSET 0x0114 /* Buffer Ready Register */
#define XUSB_TESTMODE_OFFSET 0x0118 /* Test Mode Register */
#define XUSB_DMA_RESET_OFFSET 0x0200 /* DMA Soft Reset Register */
#define XUSB_DMA_CONTROL_OFFSET 0x0204 /* DMA Control Register */
#define XUSB_DMA_DSAR_ADDR_OFFSET 0x0208 /* DMA source Address Reg */
#define XUSB_DMA_DDAR_ADDR_OFFSET 0x020C /* DMA destination Addr Reg */
#define XUSB_DMA_LENGTH_OFFSET 0x0210 /* DMA Length Register */
#define XUSB_DMA_STATUS_OFFSET 0x0214 /* DMA Status Register */
/* Endpoint Configuration Space offsets */
#define XUSB_EP_CFGSTATUS_OFFSET 0x00 /* Endpoint Config Status */
#define XUSB_EP_BUF0COUNT_OFFSET 0x08 /* Buffer 0 Count */
#define XUSB_EP_BUF1COUNT_OFFSET 0x0C /* Buffer 1 Count */
#define XUSB_CONTROL_USB_READY_MASK 0x80000000 /* USB ready Mask */
#define XUSB_CONTROL_USB_RMTWAKE_MASK 0x40000000 /* Remote wake up mask */
/* Interrupt register related masks.*/
#define XUSB_STATUS_GLOBAL_INTR_MASK 0x80000000 /* Global Intr Enable */
#define XUSB_STATUS_DMADONE_MASK 0x04000000 /* DMA done Mask */
#define XUSB_STATUS_DMAERR_MASK 0x02000000 /* DMA Error Mask */
#define XUSB_STATUS_DMABUSY_MASK 0x80000000 /* DMA Error Mask */
#define XUSB_STATUS_RESUME_MASK 0x01000000 /* USB Resume Mask */
#define XUSB_STATUS_RESET_MASK 0x00800000 /* USB Reset Mask */
#define XUSB_STATUS_SUSPEND_MASK 0x00400000 /* USB Suspend Mask */
#define XUSB_STATUS_DISCONNECT_MASK 0x00200000 /* USB Disconnect Mask */
#define XUSB_STATUS_FIFO_BUFF_RDY_MASK 0x00100000 /* FIFO Buff Ready Mask */
#define XUSB_STATUS_FIFO_BUFF_FREE_MASK 0x00080000 /* FIFO Buff Free Mask */
#define XUSB_STATUS_SETUP_PACKET_MASK 0x00040000 /* Setup packet received */
#define XUSB_STATUS_EP1_BUFF2_COMP_MASK 0x00000200 /* EP 1 Buff 2 Processed */
#define XUSB_STATUS_EP1_BUFF1_COMP_MASK 0x00000002 /* EP 1 Buff 1 Processed */
#define XUSB_STATUS_EP0_BUFF2_COMP_MASK 0x00000100 /* EP 0 Buff 2 Processed */
#define XUSB_STATUS_EP0_BUFF1_COMP_MASK 0x00000001 /* EP 0 Buff 1 Processed */
#define XUSB_STATUS_HIGH_SPEED_MASK 0x00010000 /* USB Speed Mask */
/* Suspend,Reset,Suspend and Disconnect Mask */
#define XUSB_STATUS_INTR_EVENT_MASK 0x01E00000
/* Buffers completion Mask */
#define XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK 0x0000FEFF
/* Mask for buffer 0 and buffer 1 completion for all Endpoints */
#define XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK 0x00000101
#define XUSB_STATUS_EP_BUFF2_SHIFT 8 /* EP buffer offset */
/* Endpoint Configuration Status Register */
#define XUSB_EP_CFG_VALID_MASK 0x80000000 /* Endpoint Valid bit */
#define XUSB_EP_CFG_STALL_MASK 0x40000000 /* Endpoint Stall bit */
#define XUSB_EP_CFG_DATA_TOGGLE_MASK 0x08000000 /* Endpoint Data toggle */
/* USB device specific global configuration constants.*/
#define XUSB_MAX_ENDPOINTS 8 /* Maximum End Points */
#define XUSB_EP_NUMBER_ZERO 0 /* End point Zero */
/* DPRAM is the source address for DMA transfer */
#define XUSB_DMA_READ_FROM_DPRAM 0x80000000
#define XUSB_DMA_DMASR_BUSY 0x80000000 /* DMA busy */
#define XUSB_DMA_DMASR_ERROR 0x40000000 /* DMA Error */
/*
* When this bit is set, the DMA buffer ready bit is set by hardware upon
* DMA transfer completion.
*/
#define XUSB_DMA_BRR_CTRL 0x40000000 /* DMA bufready ctrl bit */
/* Phase States */
#define SETUP_PHASE 0x0000 /* Setup Phase */
#define DATA_PHASE 0x0001 /* Data Phase */
#define STATUS_PHASE 0x0002 /* Status Phase */
#define EP0_MAX_PACKET 64 /* Endpoint 0 maximum packet length */
#define STATUSBUFF_SIZE 2 /* Buffer size for GET_STATUS command */
#define EPNAME_SIZE 4 /* Buffer size for endpoint name */
/* container_of helper macros */
#define to_udc(g) container_of((g), struct xusb_udc, gadget)
#define to_xusb_ep(ep) container_of((ep), struct xusb_ep, ep_usb)
#define to_xusb_req(req) container_of((req), struct xusb_req, usb_req)
/**
* struct xusb_req - Xilinx USB device request structure
* @usb_req: Linux usb request structure
* @queue: usb device request queue
* @ep: pointer to xusb_endpoint structure
*/
struct xusb_req {
struct usb_request usb_req;
struct list_head queue;
struct xusb_ep *ep;
};
/**
* struct xusb_ep - USB end point structure.
* @ep_usb: usb endpoint instance
* @queue: endpoint message queue
* @udc: xilinx usb peripheral driver instance pointer
* @desc: pointer to the usb endpoint descriptor
* @rambase: the endpoint buffer address
* @offset: the endpoint register offset value
* @name: name of the endpoint
* @epnumber: endpoint number
* @maxpacket: maximum packet size the endpoint can store
* @buffer0count: the size of the packet recieved in the first buffer
* @buffer1count: the size of the packet received in the second buffer
* @curbufnum: current buffer of endpoint that will be processed next
* @buffer0ready: the busy state of first buffer
* @buffer1ready: the busy state of second buffer
* @is_in: endpoint direction (IN or OUT)
* @is_iso: endpoint type(isochronous or non isochronous)
*/
struct xusb_ep {
struct usb_ep ep_usb;
struct list_head queue;
struct xusb_udc *udc;
const struct usb_endpoint_descriptor *desc;
u32 rambase;
u32 offset;
char name[4];
u16 epnumber;
u16 maxpacket;
u16 buffer0count;
u16 buffer1count;
u8 curbufnum;
bool buffer0ready;
bool buffer1ready;
bool is_in;
bool is_iso;
};
/**
* struct xusb_udc - USB peripheral driver structure
* @gadget: USB gadget driver instance
* @ep: an array of endpoint structures
* @driver: pointer to the usb gadget driver instance
* @setup: usb_ctrlrequest structure for control requests
* @req: pointer to dummy request for get status command
* @dev: pointer to device structure in gadget
* @usb_state: device in suspended state or not
* @remote_wkp: remote wakeup enabled by host
* @setupseqtx: tx status
* @setupseqrx: rx status
* @addr: the usb device base address
* @lock: instance of spinlock
* @dma_enabled: flag indicating whether the dma is included in the system
* @read_fn: function pointer to read device registers
* @write_fn: function pointer to write to device registers
*/
struct xusb_udc {
struct usb_gadget gadget;
struct xusb_ep ep[8];
struct usb_gadget_driver *driver;
struct usb_ctrlrequest setup;
struct xusb_req *req;
struct device *dev;
u32 usb_state;
u32 remote_wkp;
u32 setupseqtx;
u32 setupseqrx;
void __iomem *addr;
spinlock_t lock;
bool dma_enabled;
unsigned int (*read_fn)(void __iomem *);
void (*write_fn)(void __iomem *, u32, u32);
};
/* Endpoint buffer start addresses in the core */
static u32 rambase[8] = { 0x22, 0x1000, 0x1100, 0x1200, 0x1300, 0x1400, 0x1500,
0x1600 };
static const char driver_name[] = "xilinx-udc";
static const char ep0name[] = "ep0";
/* Control endpoint configuration.*/
static const struct usb_endpoint_descriptor config_bulk_out_desc = {
.bLength = USB_DT_ENDPOINT_SIZE,
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = USB_DIR_OUT,
.bmAttributes = USB_ENDPOINT_XFER_BULK,
.wMaxPacketSize = cpu_to_le16(EP0_MAX_PACKET),
};
/**
* xudc_write32 - little endian write to device registers
* @addr: base addr of device registers
* @offset: register offset
* @val: data to be written
*/
static void xudc_write32(void __iomem *addr, u32 offset, u32 val)
{
iowrite32(val, addr + offset);
}
/**
* xudc_read32 - little endian read from device registers
* @addr: addr of device register
* Return: value at addr
*/
static unsigned int xudc_read32(void __iomem *addr)
{
return ioread32(addr);
}
/**
* xudc_write32_be - big endian write to device registers
* @addr: base addr of device registers
* @offset: register offset
* @val: data to be written
*/
static void xudc_write32_be(void __iomem *addr, u32 offset, u32 val)
{
iowrite32be(val, addr + offset);
}
/**
* xudc_read32_be - big endian read from device registers
* @addr: addr of device register
* Return: value at addr
*/
static unsigned int xudc_read32_be(void __iomem *addr)
{
return ioread32be(addr);
}
/**
* xudc_wrstatus - Sets up the usb device status stages.
* @udc: pointer to the usb device controller structure.
*/
static void xudc_wrstatus(struct xusb_udc *udc)
{
struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO];
u32 epcfgreg;
epcfgreg = udc->read_fn(udc->addr + ep0->offset)|
XUSB_EP_CFG_DATA_TOGGLE_MASK;
udc->write_fn(udc->addr, ep0->offset, epcfgreg);
udc->write_fn(udc->addr, ep0->offset + XUSB_EP_BUF0COUNT_OFFSET, 0);
udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
}
/**
* xudc_epconfig - Configures the given endpoint.
* @ep: pointer to the usb device endpoint structure.
* @udc: pointer to the usb peripheral controller structure.
*
* This function configures a specific endpoint with the given configuration
* data.
*/
static void xudc_epconfig(struct xusb_ep *ep, struct xusb_udc *udc)
{
u32 epcfgreg;
/*
* Configure the end point direction, type, Max Packet Size and the
* EP buffer location.
*/
epcfgreg = ((ep->is_in << 29) | (ep->is_iso << 28) |
(ep->ep_usb.maxpacket << 15) | (ep->rambase));
udc->write_fn(udc->addr, ep->offset, epcfgreg);
/* Set the Buffer count and the Buffer ready bits.*/
udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF0COUNT_OFFSET,
ep->buffer0count);
udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF1COUNT_OFFSET,
ep->buffer1count);
if (ep->buffer0ready)
udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
1 << ep->epnumber);
if (ep->buffer1ready)
udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT));
}
/**
* xudc_start_dma - Starts DMA transfer.
* @ep: pointer to the usb device endpoint structure.
* @src: DMA source address.
* @dst: DMA destination address.
* @length: number of bytes to transfer.
*
* Return: 0 on success, error code on failure
*
* This function starts DMA transfer by writing to DMA source,
* destination and lenth registers.
*/
static int xudc_start_dma(struct xusb_ep *ep, dma_addr_t src,
dma_addr_t dst, u32 length)
{
struct xusb_udc *udc = ep->udc;
int rc = 0;
u32 timeout = 500;
u32 reg;
/*
* Set the addresses in the DMA source and
* destination registers and then set the length
* into the DMA length register.
*/
udc->write_fn(udc->addr, XUSB_DMA_DSAR_ADDR_OFFSET, src);
udc->write_fn(udc->addr, XUSB_DMA_DDAR_ADDR_OFFSET, dst);
udc->write_fn(udc->addr, XUSB_DMA_LENGTH_OFFSET, length);
/*
* Wait till DMA transaction is complete and
* check whether the DMA transaction was
* successful.
*/
do {
reg = udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET);
if (!(reg & XUSB_DMA_DMASR_BUSY))
break;
/*
* We can't sleep here, because it's also called from
* interrupt context.
*/
timeout--;
if (!timeout) {
dev_err(udc->dev, "DMA timeout\n");
return -ETIMEDOUT;
}
udelay(1);
} while (1);
if ((udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET) &
XUSB_DMA_DMASR_ERROR) == XUSB_DMA_DMASR_ERROR){
dev_err(udc->dev, "DMA Error\n");
rc = -EINVAL;
}
return rc;
}
/**
* xudc_dma_send - Sends IN data using DMA.
* @ep: pointer to the usb device endpoint structure.
* @req: pointer to the usb request structure.
* @buffer: pointer to data to be sent.
* @length: number of bytes to send.
*
* Return: 0 on success, -EAGAIN if no buffer is free and error
* code on failure.
*
* This function sends data using DMA.
*/
static int xudc_dma_send(struct xusb_ep *ep, struct xusb_req *req,
u8 *buffer, u32 length)
{
u32 *eprambase;
dma_addr_t src;
dma_addr_t dst;
struct xusb_udc *udc = ep->udc;
src = req->usb_req.dma + req->usb_req.actual;
if (req->usb_req.length)
dma_sync_single_for_device(udc->dev, src,
length, DMA_TO_DEVICE);
if (!ep->curbufnum && !ep->buffer0ready) {
/* Get the Buffer address and copy the transmit data.*/
eprambase = (u32 __force *)(udc->addr + ep->rambase);
dst = virt_to_phys(eprambase);
udc->write_fn(udc->addr, ep->offset +
XUSB_EP_BUF0COUNT_OFFSET, length);
udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
XUSB_DMA_BRR_CTRL | (1 << ep->epnumber));
ep->buffer0ready = 1;
ep->curbufnum = 1;
} else if (ep->curbufnum && !ep->buffer1ready) {
/* Get the Buffer address and copy the transmit data.*/
eprambase = (u32 __force *)(udc->addr + ep->rambase +
ep->ep_usb.maxpacket);
dst = virt_to_phys(eprambase);
udc->write_fn(udc->addr, ep->offset +
XUSB_EP_BUF1COUNT_OFFSET, length);
udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
XUSB_DMA_BRR_CTRL | (1 << (ep->epnumber +
XUSB_STATUS_EP_BUFF2_SHIFT)));
ep->buffer1ready = 1;
ep->curbufnum = 0;
} else {
/* None of ping pong buffers are ready currently .*/
return -EAGAIN;
}
return xudc_start_dma(ep, src, dst, length);
}
/**
* xudc_dma_receive - Receives OUT data using DMA.
* @ep: pointer to the usb device endpoint structure.
* @req: pointer to the usb request structure.
* @buffer: pointer to storage buffer of received data.
* @length: number of bytes to receive.
*
* Return: 0 on success, -EAGAIN if no buffer is free and error
* code on failure.
*
* This function receives data using DMA.
*/
static int xudc_dma_receive(struct xusb_ep *ep, struct xusb_req *req,
u8 *buffer, u32 length)
{
u32 *eprambase;
dma_addr_t src;
dma_addr_t dst;
struct xusb_udc *udc = ep->udc;
dst = req->usb_req.dma + req->usb_req.actual;
if (!ep->curbufnum && !ep->buffer0ready) {
/* Get the Buffer address and copy the transmit data */
eprambase = (u32 __force *)(udc->addr + ep->rambase);
src = virt_to_phys(eprambase);
udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM |
(1 << ep->epnumber));
ep->buffer0ready = 1;
ep->curbufnum = 1;
} else if (ep->curbufnum && !ep->buffer1ready) {
/* Get the Buffer address and copy the transmit data */
eprambase = (u32 __force *)(udc->addr +
ep->rambase + ep->ep_usb.maxpacket);
src = virt_to_phys(eprambase);
udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM |
(1 << (ep->epnumber +
XUSB_STATUS_EP_BUFF2_SHIFT)));
ep->buffer1ready = 1;
ep->curbufnum = 0;
} else {
/* None of the ping-pong buffers are ready currently */
return -EAGAIN;
}
return xudc_start_dma(ep, src, dst, length);
}
/**
* xudc_eptxrx - Transmits or receives data to or from an endpoint.
* @ep: pointer to the usb endpoint configuration structure.
* @req: pointer to the usb request structure.
* @bufferptr: pointer to buffer containing the data to be sent.
* @bufferlen: The number of data bytes to be sent.
*
* Return: 0 on success, -EAGAIN if no buffer is free.
*
* This function copies the transmit/receive data to/from the end point buffer
* and enables the buffer for transmission/reception.
*/
static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req,
u8 *bufferptr, u32 bufferlen)
{
u32 *eprambase;
u32 bytestosend;
int rc = 0;
struct xusb_udc *udc = ep->udc;
bytestosend = bufferlen;
if (udc->dma_enabled) {
if (ep->is_in)
rc = xudc_dma_send(ep, req, bufferptr, bufferlen);
else
rc = xudc_dma_receive(ep, req, bufferptr, bufferlen);
return rc;
}
/* Put the transmit buffer into the correct ping-pong buffer.*/
if (!ep->curbufnum && !ep->buffer0ready) {
/* Get the Buffer address and copy the transmit data.*/
eprambase = (u32 __force *)(udc->addr + ep->rambase);
if (ep->is_in) {
memcpy(eprambase, bufferptr, bytestosend);
udc->write_fn(udc->addr, ep->offset +
XUSB_EP_BUF0COUNT_OFFSET, bufferlen);
} else {
memcpy(bufferptr, eprambase, bytestosend);
}
/*
* Enable the buffer for transmission.
*/
udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
1 << ep->epnumber);
ep->buffer0ready = 1;
ep->curbufnum = 1;
} else if (ep->curbufnum && !ep->buffer1ready) {
/* Get the Buffer address and copy the transmit data.*/
eprambase = (u32 __force *)(udc->addr + ep->rambase +
ep->ep_usb.maxpacket);
if (ep->is_in) {
memcpy(eprambase, bufferptr, bytestosend);
udc->write_fn(udc->addr, ep->offset +
XUSB_EP_BUF1COUNT_OFFSET, bufferlen);
} else {
memcpy(bufferptr, eprambase, bytestosend);
}
/*
* Enable the buffer for transmission.
*/
udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT));
ep->buffer1ready = 1;
ep->curbufnum = 0;
} else {
/* None of the ping-pong buffers are ready currently */
return -EAGAIN;
}
return rc;
}
/**
* xudc_done - Exeutes the endpoint data transfer completion tasks.
* @ep: pointer to the usb device endpoint structure.
* @req: pointer to the usb request structure.
* @status: Status of the data transfer.
*
* Deletes the message from the queue and updates data transfer completion
* status.
*/
static void xudc_done(struct xusb_ep *ep, struct xusb_req *req, int status)
{
struct xusb_udc *udc = ep->udc;
list_del_init(&req->queue);
if (req->usb_req.status == -EINPROGRESS)
req->usb_req.status = status;
else
status = req->usb_req.status;
if (status && status != -ESHUTDOWN)
dev_dbg(udc->dev, "%s done %p, status %d\n",
ep->ep_usb.name, req, status);
/* unmap request if DMA is present*/
if (udc->dma_enabled && ep->epnumber && req->usb_req.length)
usb_gadget_unmap_request(&udc->gadget, &req->usb_req,
ep->is_in);
if (req->usb_req.complete) {
spin_unlock(&udc->lock);
req->usb_req.complete(&ep->ep_usb, &req->usb_req);
spin_lock(&udc->lock);
}
}
/**
* xudc_read_fifo - Reads the data from the given endpoint buffer.
* @ep: pointer to the usb device endpoint structure.
* @req: pointer to the usb request structure.
*
* Return: 0 if request is completed and -EAGAIN if not completed.
*
* Pulls OUT packet data from the endpoint buffer.
*/
static int xudc_read_fifo(struct xusb_ep *ep, struct xusb_req *req)
{
u8 *buf;
u32 is_short, count, bufferspace;
u8 bufoffset;
u8 two_pkts = 0;
int ret;
int retval = -EAGAIN;
struct xusb_udc *udc = ep->udc;
if (ep->buffer0ready && ep->buffer1ready) {
dev_dbg(udc->dev, "Packet NOT ready!\n");
return retval;
}
top:
if (ep->curbufnum)
bufoffset = XUSB_EP_BUF1COUNT_OFFSET;
else
bufoffset = XUSB_EP_BUF0COUNT_OFFSET;
count = udc->read_fn(udc->addr + ep->offset + bufoffset);
if (!ep->buffer0ready && !ep->buffer1ready)
two_pkts = 1;
buf = req->usb_req.buf + req->usb_req.actual;
prefetchw(buf);
bufferspace = req->usb_req.length - req->usb_req.actual;
is_short = count < ep->ep_usb.maxpacket;
if (unlikely(!bufferspace)) {
/*
* This happens when the driver's buffer
* is smaller than what the host sent.
* discard the extra data.
*/
if (req->usb_req.status != -EOVERFLOW)
dev_dbg(udc->dev, "%s overflow %d\n",
ep->ep_usb.name, count);
req->usb_req.status = -EOVERFLOW;
xudc_done(ep, req, -EOVERFLOW);
return 0;
}
ret = xudc_eptxrx(ep, req, buf, count);
switch (ret) {
case 0:
req->usb_req.actual += min(count, bufferspace);
dev_dbg(udc->dev, "read %s, %d bytes%s req %p %d/%d\n",
ep->ep_usb.name, count, is_short ? "/S" : "", req,
req->usb_req.actual, req->usb_req.length);
bufferspace -= count;
/* Completion */
if ((req->usb_req.actual == req->usb_req.length) || is_short) {
if (udc->dma_enabled && req->usb_req.length)
dma_sync_single_for_cpu(udc->dev,
req->usb_req.dma,
req->usb_req.actual,
DMA_FROM_DEVICE);
xudc_done(ep, req, 0);
return 0;
}
if (two_pkts) {
two_pkts = 0;
goto top;
}
break;
case -EAGAIN:
dev_dbg(udc->dev, "receive busy\n");
break;
case -EINVAL:
case -ETIMEDOUT:
/* DMA error, dequeue the request */
xudc_done(ep, req, -ECONNRESET);
retval = 0;
break;
}
return retval;
}
/**
* xudc_write_fifo - Writes data into the given endpoint buffer.
* @ep: pointer to the usb device endpoint structure.
* @req: pointer to the usb request structure.
*
* Return: 0 if request is completed and -EAGAIN if not completed.
*
* Loads endpoint buffer for an IN packet.
*/
static int xudc_write_fifo(struct xusb_ep *ep, struct xusb_req *req)
{
u32 max;
u32 length;
int ret;
int retval = -EAGAIN;
struct xusb_udc *udc = ep->udc;
int is_last, is_short = 0;
u8 *buf;
max = le16_to_cpu(ep->desc->wMaxPacketSize);
buf = req->usb_req.buf + req->usb_req.actual;
prefetch(buf);
length = req->usb_req.length - req->usb_req.actual;
length = min(length, max);
ret = xudc_eptxrx(ep, req, buf, length);
switch (ret) {
case 0:
req->usb_req.actual += length;
if (unlikely(length != max)) {
is_last = is_short = 1;
} else {
if (likely(req->usb_req.length !=
req->usb_req.actual) || req->usb_req.zero)
is_last = 0;
else
is_last = 1;
}
dev_dbg(udc->dev, "%s: wrote %s %d bytes%s%s %d left %p\n",
__func__, ep->ep_usb.name, length, is_last ? "/L" : "",
is_short ? "/S" : "",
req->usb_req.length - req->usb_req.actual, req);
/* completion */
if (is_last) {
xudc_done(ep, req, 0);
retval = 0;
}
break;
case -EAGAIN:
dev_dbg(udc->dev, "Send busy\n");
break;
case -EINVAL:
case -ETIMEDOUT:
/* DMA error, dequeue the request */
xudc_done(ep, req, -ECONNRESET);
retval = 0;
break;
}
return retval;
}
/**
* xudc_nuke - Cleans up the data transfer message list.
* @ep: pointer to the usb device endpoint structure.
* @status: Status of the data transfer.
*/
static void xudc_nuke(struct xusb_ep *ep, int status)
{
struct xusb_req *req;
while (!list_empty(&ep->queue)) {
req = list_first_entry(&ep->queue, struct xusb_req, queue);
xudc_done(ep, req, status);
}
}
/**
* xudc_ep_set_halt - Stalls/unstalls the given endpoint.
* @_ep: pointer to the usb device endpoint structure.
* @value: value to indicate stall/unstall.
*
* Return: 0 for success and error value on failure
*/
static int xudc_ep_set_halt(struct usb_ep *_ep, int value)
{
struct xusb_ep *ep = to_xusb_ep(_ep);
struct xusb_udc *udc;
unsigned long flags;
u32 epcfgreg;
if (!_ep || (!ep->desc && ep->epnumber)) {
pr_debug("%s: bad ep or descriptor\n", __func__);
return -EINVAL;
}
udc = ep->udc;
if (ep->is_in && (!list_empty(&ep->queue)) && value) {
dev_dbg(udc->dev, "requests pending can't halt\n");
return -EAGAIN;
}
if (ep->buffer0ready || ep->buffer1ready) {
dev_dbg(udc->dev, "HW buffers busy can't halt\n");
return -EAGAIN;
}
spin_lock_irqsave(&udc->lock, flags);
if (value) {
/* Stall the device.*/
epcfgreg = udc->read_fn(udc->addr + ep->offset);
epcfgreg |= XUSB_EP_CFG_STALL_MASK;
udc->write_fn(udc->addr, ep->offset, epcfgreg);
} else {
/* Unstall the device.*/
epcfgreg = udc->read_fn(udc->addr + ep->offset);
epcfgreg &= ~XUSB_EP_CFG_STALL_MASK;
udc->write_fn(udc->addr, ep->offset, epcfgreg);
if (ep->epnumber) {
/* Reset the toggle bit.*/
epcfgreg = udc->read_fn(ep->udc->addr + ep->offset);
epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK;
udc->write_fn(udc->addr, ep->offset, epcfgreg);
}
}
spin_unlock_irqrestore(&udc->lock, flags);
return 0;
}
/**
* __xudc_ep_enable - Enables the given endpoint.
* @ep: pointer to the xusb endpoint structure.
* @desc: pointer to usb endpoint descriptor.
*
* Return: 0 for success and error value on failure
*/
static int __xudc_ep_enable(struct xusb_ep *ep,
const struct usb_endpoint_descriptor *desc)
{
struct xusb_udc *udc = ep->udc;
u32 tmp;
u32 epcfg;
u32 ier;
u16 maxpacket;
ep->is_in = ((desc->bEndpointAddress & USB_DIR_IN) != 0);
/* Bit 3...0:endpoint number */
ep->epnumber = (desc->bEndpointAddress & 0x0f);
ep->desc = desc;
ep->ep_usb.desc = desc;
tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
ep->ep_usb.maxpacket = maxpacket = le16_to_cpu(desc->wMaxPacketSize);
switch (tmp) {
case USB_ENDPOINT_XFER_CONTROL:
dev_dbg(udc->dev, "only one control endpoint\n");
/* NON- ISO */
ep->is_iso = 0;
return -EINVAL;
case USB_ENDPOINT_XFER_INT:
/* NON- ISO */
ep->is_iso = 0;
if (maxpacket > 64) {
dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket);
return -EINVAL;
}
break;
case USB_ENDPOINT_XFER_BULK:
/* NON- ISO */
ep->is_iso = 0;
if (!(is_power_of_2(maxpacket) && maxpacket >= 8 &&
maxpacket <= 512)) {
dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket);
return -EINVAL;
}
break;
case USB_ENDPOINT_XFER_ISOC:
/* ISO */
ep->is_iso = 1;
break;
}
ep->buffer0ready = false;
ep->buffer1ready = false;
ep->curbufnum = 0;
ep->rambase = rambase[ep->epnumber];
xudc_epconfig(ep, udc);
dev_dbg(udc->dev, "Enable Endpoint %d max pkt is %d\n",
ep->epnumber, maxpacket);
/* Enable the End point.*/
epcfg = udc->read_fn(udc->addr + ep->offset);
epcfg |= XUSB_EP_CFG_VALID_MASK;
udc->write_fn(udc->addr, ep->offset, epcfg);
if (ep->epnumber)
ep->rambase <<= 2;
/* Enable buffer completion interrupts for endpoint */
ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
ier |= (XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK << ep->epnumber);
udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier);
/* for OUT endpoint set buffers ready to receive */
if (ep->epnumber && !ep->is_in) {
udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
1 << ep->epnumber);
ep->buffer0ready = true;
udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
(1 << (ep->epnumber +
XUSB_STATUS_EP_BUFF2_SHIFT)));
ep->buffer1ready = true;
}
return 0;
}
/**
* xudc_ep_enable - Enables the given endpoint.
* @_ep: pointer to the usb endpoint structure.
* @desc: pointer to usb endpoint descriptor.
*
* Return: 0 for success and error value on failure
*/
static int xudc_ep_enable(struct usb_ep *_ep,
const struct usb_endpoint_descriptor *desc)
{
struct xusb_ep *ep;
struct xusb_udc *udc;
unsigned long flags;
int ret;
if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
pr_debug("%s: bad ep or descriptor\n", __func__);
return -EINVAL;
}
ep = to_xusb_ep(_ep);
udc = ep->udc;
if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
dev_dbg(udc->dev, "bogus device state\n");
return -ESHUTDOWN;
}
spin_lock_irqsave(&udc->lock, flags);
ret = __xudc_ep_enable(ep, desc);
spin_unlock_irqrestore(&udc->lock, flags);
return ret;
}
/**
* xudc_ep_disable - Disables the given endpoint.
* @_ep: pointer to the usb endpoint structure.
*
* Return: 0 for success and error value on failure
*/
static int xudc_ep_disable(struct usb_ep *_ep)
{
struct xusb_ep *ep;
unsigned long flags;
u32 epcfg;
struct xusb_udc *udc;
if (!_ep) {
pr_debug("%s: invalid ep\n", __func__);
return -EINVAL;
}
ep = to_xusb_ep(_ep);
udc = ep->udc;
spin_lock_irqsave(&udc->lock, flags);
xudc_nuke(ep, -ESHUTDOWN);
/* Restore the endpoint's pristine config */
ep->desc = NULL;
ep->ep_usb.desc = NULL;
dev_dbg(udc->dev, "USB Ep %d disable\n ", ep->epnumber);
/* Disable the endpoint.*/
epcfg = udc->read_fn(udc->addr + ep->offset);
epcfg &= ~XUSB_EP_CFG_VALID_MASK;
udc->write_fn(udc->addr, ep->offset, epcfg);
spin_unlock_irqrestore(&udc->lock, flags);
return 0;
}
/**
* xudc_ep_alloc_request - Initializes the request queue.
* @_ep: pointer to the usb endpoint structure.
* @gfp_flags: Flags related to the request call.
*
* Return: pointer to request structure on success and a NULL on failure.
*/
static struct usb_request *xudc_ep_alloc_request(struct usb_ep *_ep,
gfp_t gfp_flags)
{
struct xusb_ep *ep = to_xusb_ep(_ep);
struct xusb_req *req;
req = kzalloc(sizeof(*req), gfp_flags);
if (!req)
return NULL;
req->ep = ep;
INIT_LIST_HEAD(&req->queue);
return &req->usb_req;
}
/**
* xudc_free_request - Releases the request from queue.
* @_ep: pointer to the usb device endpoint structure.
* @_req: pointer to the usb request structure.
*/
static void xudc_free_request(struct usb_ep *_ep, struct usb_request *_req)
{
struct xusb_req *req = to_xusb_req(_req);
kfree(req);
}
/**
* __xudc_ep0_queue - Adds the request to endpoint 0 queue.
* @ep0: pointer to the xusb endpoint 0 structure.
* @req: pointer to the xusb request structure.
*
* Return: 0 for success and error value on failure
*/
static int __xudc_ep0_queue(struct xusb_ep *ep0, struct xusb_req *req)
{
struct xusb_udc *udc = ep0->udc;
u32 length;
u8 *corebuf;