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rcar-dmac.c
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rcar-dmac.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Renesas R-Car Gen2/Gen3 DMA Controller Driver
*
* Copyright (C) 2014-2019 Renesas Electronics Inc.
*
* Author: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*/
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_dma.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include "../dmaengine.h"
/*
* struct rcar_dmac_xfer_chunk - Descriptor for a hardware transfer
* @node: entry in the parent's chunks list
* @src_addr: device source address
* @dst_addr: device destination address
* @size: transfer size in bytes
*/
struct rcar_dmac_xfer_chunk {
struct list_head node;
dma_addr_t src_addr;
dma_addr_t dst_addr;
u32 size;
};
/*
* struct rcar_dmac_hw_desc - Hardware descriptor for a transfer chunk
* @sar: value of the SAR register (source address)
* @dar: value of the DAR register (destination address)
* @tcr: value of the TCR register (transfer count)
*/
struct rcar_dmac_hw_desc {
u32 sar;
u32 dar;
u32 tcr;
u32 reserved;
} __attribute__((__packed__));
/*
* struct rcar_dmac_desc - R-Car Gen2 DMA Transfer Descriptor
* @async_tx: base DMA asynchronous transaction descriptor
* @direction: direction of the DMA transfer
* @xfer_shift: log2 of the transfer size
* @chcr: value of the channel configuration register for this transfer
* @node: entry in the channel's descriptors lists
* @chunks: list of transfer chunks for this transfer
* @running: the transfer chunk being currently processed
* @nchunks: number of transfer chunks for this transfer
* @hwdescs.use: whether the transfer descriptor uses hardware descriptors
* @hwdescs.mem: hardware descriptors memory for the transfer
* @hwdescs.dma: device address of the hardware descriptors memory
* @hwdescs.size: size of the hardware descriptors in bytes
* @size: transfer size in bytes
* @cyclic: when set indicates that the DMA transfer is cyclic
*/
struct rcar_dmac_desc {
struct dma_async_tx_descriptor async_tx;
enum dma_transfer_direction direction;
unsigned int xfer_shift;
u32 chcr;
struct list_head node;
struct list_head chunks;
struct rcar_dmac_xfer_chunk *running;
unsigned int nchunks;
struct {
bool use;
struct rcar_dmac_hw_desc *mem;
dma_addr_t dma;
size_t size;
} hwdescs;
unsigned int size;
bool cyclic;
};
#define to_rcar_dmac_desc(d) container_of(d, struct rcar_dmac_desc, async_tx)
/*
* struct rcar_dmac_desc_page - One page worth of descriptors
* @node: entry in the channel's pages list
* @descs: array of DMA descriptors
* @chunks: array of transfer chunk descriptors
*/
struct rcar_dmac_desc_page {
struct list_head node;
union {
struct rcar_dmac_desc descs[0];
struct rcar_dmac_xfer_chunk chunks[0];
};
};
#define RCAR_DMAC_DESCS_PER_PAGE \
((PAGE_SIZE - offsetof(struct rcar_dmac_desc_page, descs)) / \
sizeof(struct rcar_dmac_desc))
#define RCAR_DMAC_XFER_CHUNKS_PER_PAGE \
((PAGE_SIZE - offsetof(struct rcar_dmac_desc_page, chunks)) / \
sizeof(struct rcar_dmac_xfer_chunk))
/*
* struct rcar_dmac_chan_slave - Slave configuration
* @slave_addr: slave memory address
* @xfer_size: size (in bytes) of hardware transfers
*/
struct rcar_dmac_chan_slave {
phys_addr_t slave_addr;
unsigned int xfer_size;
};
/*
* struct rcar_dmac_chan_map - Map of slave device phys to dma address
* @addr: slave dma address
* @dir: direction of mapping
* @slave: slave configuration that is mapped
*/
struct rcar_dmac_chan_map {
dma_addr_t addr;
enum dma_data_direction dir;
struct rcar_dmac_chan_slave slave;
};
/*
* struct rcar_dmac_chan - R-Car Gen2 DMA Controller Channel
* @chan: base DMA channel object
* @iomem: channel I/O memory base
* @index: index of this channel in the controller
* @irq: channel IRQ
* @src: slave memory address and size on the source side
* @dst: slave memory address and size on the destination side
* @mid_rid: hardware MID/RID for the DMA client using this channel
* @lock: protects the channel CHCR register and the desc members
* @desc.free: list of free descriptors
* @desc.pending: list of pending descriptors (submitted with tx_submit)
* @desc.active: list of active descriptors (activated with issue_pending)
* @desc.done: list of completed descriptors
* @desc.wait: list of descriptors waiting for an ack
* @desc.running: the descriptor being processed (a member of the active list)
* @desc.chunks_free: list of free transfer chunk descriptors
* @desc.pages: list of pages used by allocated descriptors
*/
struct rcar_dmac_chan {
struct dma_chan chan;
void __iomem *iomem;
unsigned int index;
int irq;
struct rcar_dmac_chan_slave src;
struct rcar_dmac_chan_slave dst;
struct rcar_dmac_chan_map map;
int mid_rid;
spinlock_t lock;
struct {
struct list_head free;
struct list_head pending;
struct list_head active;
struct list_head done;
struct list_head wait;
struct rcar_dmac_desc *running;
struct list_head chunks_free;
struct list_head pages;
} desc;
};
#define to_rcar_dmac_chan(c) container_of(c, struct rcar_dmac_chan, chan)
/*
* struct rcar_dmac - R-Car Gen2 DMA Controller
* @engine: base DMA engine object
* @dev: the hardware device
* @iomem: remapped I/O memory base
* @n_channels: number of available channels
* @channels: array of DMAC channels
* @channels_mask: bitfield of which DMA channels are managed by this driver
* @modules: bitmask of client modules in use
*/
struct rcar_dmac {
struct dma_device engine;
struct device *dev;
void __iomem *iomem;
unsigned int n_channels;
struct rcar_dmac_chan *channels;
u32 channels_mask;
DECLARE_BITMAP(modules, 256);
};
#define to_rcar_dmac(d) container_of(d, struct rcar_dmac, engine)
/*
* struct rcar_dmac_of_data - This driver's OF data
* @chan_offset_base: DMAC channels base offset
* @chan_offset_stride: DMAC channels offset stride
*/
struct rcar_dmac_of_data {
u32 chan_offset_base;
u32 chan_offset_stride;
};
/* -----------------------------------------------------------------------------
* Registers
*/
#define RCAR_DMAISTA 0x0020
#define RCAR_DMASEC 0x0030
#define RCAR_DMAOR 0x0060
#define RCAR_DMAOR_PRI_FIXED (0 << 8)
#define RCAR_DMAOR_PRI_ROUND_ROBIN (3 << 8)
#define RCAR_DMAOR_AE (1 << 2)
#define RCAR_DMAOR_DME (1 << 0)
#define RCAR_DMACHCLR 0x0080
#define RCAR_DMADPSEC 0x00a0
#define RCAR_DMASAR 0x0000
#define RCAR_DMADAR 0x0004
#define RCAR_DMATCR 0x0008
#define RCAR_DMATCR_MASK 0x00ffffff
#define RCAR_DMATSR 0x0028
#define RCAR_DMACHCR 0x000c
#define RCAR_DMACHCR_CAE (1 << 31)
#define RCAR_DMACHCR_CAIE (1 << 30)
#define RCAR_DMACHCR_DPM_DISABLED (0 << 28)
#define RCAR_DMACHCR_DPM_ENABLED (1 << 28)
#define RCAR_DMACHCR_DPM_REPEAT (2 << 28)
#define RCAR_DMACHCR_DPM_INFINITE (3 << 28)
#define RCAR_DMACHCR_RPT_SAR (1 << 27)
#define RCAR_DMACHCR_RPT_DAR (1 << 26)
#define RCAR_DMACHCR_RPT_TCR (1 << 25)
#define RCAR_DMACHCR_DPB (1 << 22)
#define RCAR_DMACHCR_DSE (1 << 19)
#define RCAR_DMACHCR_DSIE (1 << 18)
#define RCAR_DMACHCR_TS_1B ((0 << 20) | (0 << 3))
#define RCAR_DMACHCR_TS_2B ((0 << 20) | (1 << 3))
#define RCAR_DMACHCR_TS_4B ((0 << 20) | (2 << 3))
#define RCAR_DMACHCR_TS_16B ((0 << 20) | (3 << 3))
#define RCAR_DMACHCR_TS_32B ((1 << 20) | (0 << 3))
#define RCAR_DMACHCR_TS_64B ((1 << 20) | (1 << 3))
#define RCAR_DMACHCR_TS_8B ((1 << 20) | (3 << 3))
#define RCAR_DMACHCR_DM_FIXED (0 << 14)
#define RCAR_DMACHCR_DM_INC (1 << 14)
#define RCAR_DMACHCR_DM_DEC (2 << 14)
#define RCAR_DMACHCR_SM_FIXED (0 << 12)
#define RCAR_DMACHCR_SM_INC (1 << 12)
#define RCAR_DMACHCR_SM_DEC (2 << 12)
#define RCAR_DMACHCR_RS_AUTO (4 << 8)
#define RCAR_DMACHCR_RS_DMARS (8 << 8)
#define RCAR_DMACHCR_IE (1 << 2)
#define RCAR_DMACHCR_TE (1 << 1)
#define RCAR_DMACHCR_DE (1 << 0)
#define RCAR_DMATCRB 0x0018
#define RCAR_DMATSRB 0x0038
#define RCAR_DMACHCRB 0x001c
#define RCAR_DMACHCRB_DCNT(n) ((n) << 24)
#define RCAR_DMACHCRB_DPTR_MASK (0xff << 16)
#define RCAR_DMACHCRB_DPTR_SHIFT 16
#define RCAR_DMACHCRB_DRST (1 << 15)
#define RCAR_DMACHCRB_DTS (1 << 8)
#define RCAR_DMACHCRB_SLM_NORMAL (0 << 4)
#define RCAR_DMACHCRB_SLM_CLK(n) ((8 | (n)) << 4)
#define RCAR_DMACHCRB_PRI(n) ((n) << 0)
#define RCAR_DMARS 0x0040
#define RCAR_DMABUFCR 0x0048
#define RCAR_DMABUFCR_MBU(n) ((n) << 16)
#define RCAR_DMABUFCR_ULB(n) ((n) << 0)
#define RCAR_DMADPBASE 0x0050
#define RCAR_DMADPBASE_MASK 0xfffffff0
#define RCAR_DMADPBASE_SEL (1 << 0)
#define RCAR_DMADPCR 0x0054
#define RCAR_DMADPCR_DIPT(n) ((n) << 24)
#define RCAR_DMAFIXSAR 0x0010
#define RCAR_DMAFIXDAR 0x0014
#define RCAR_DMAFIXDPBASE 0x0060
/* Hardcode the MEMCPY transfer size to 4 bytes. */
#define RCAR_DMAC_MEMCPY_XFER_SIZE 4
/* -----------------------------------------------------------------------------
* Device access
*/
static void rcar_dmac_write(struct rcar_dmac *dmac, u32 reg, u32 data)
{
if (reg == RCAR_DMAOR)
writew(data, dmac->iomem + reg);
else
writel(data, dmac->iomem + reg);
}
static u32 rcar_dmac_read(struct rcar_dmac *dmac, u32 reg)
{
if (reg == RCAR_DMAOR)
return readw(dmac->iomem + reg);
else
return readl(dmac->iomem + reg);
}
static u32 rcar_dmac_chan_read(struct rcar_dmac_chan *chan, u32 reg)
{
if (reg == RCAR_DMARS)
return readw(chan->iomem + reg);
else
return readl(chan->iomem + reg);
}
static void rcar_dmac_chan_write(struct rcar_dmac_chan *chan, u32 reg, u32 data)
{
if (reg == RCAR_DMARS)
writew(data, chan->iomem + reg);
else
writel(data, chan->iomem + reg);
}
/* -----------------------------------------------------------------------------
* Initialization and configuration
*/
static bool rcar_dmac_chan_is_busy(struct rcar_dmac_chan *chan)
{
u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
return !!(chcr & (RCAR_DMACHCR_DE | RCAR_DMACHCR_TE));
}
static void rcar_dmac_chan_start_xfer(struct rcar_dmac_chan *chan)
{
struct rcar_dmac_desc *desc = chan->desc.running;
u32 chcr = desc->chcr;
WARN_ON_ONCE(rcar_dmac_chan_is_busy(chan));
if (chan->mid_rid >= 0)
rcar_dmac_chan_write(chan, RCAR_DMARS, chan->mid_rid);
if (desc->hwdescs.use) {
struct rcar_dmac_xfer_chunk *chunk =
list_first_entry(&desc->chunks,
struct rcar_dmac_xfer_chunk, node);
dev_dbg(chan->chan.device->dev,
"chan%u: queue desc %p: %u@%pad\n",
chan->index, desc, desc->nchunks, &desc->hwdescs.dma);
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR,
chunk->src_addr >> 32);
rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR,
chunk->dst_addr >> 32);
rcar_dmac_chan_write(chan, RCAR_DMAFIXDPBASE,
desc->hwdescs.dma >> 32);
#endif
rcar_dmac_chan_write(chan, RCAR_DMADPBASE,
(desc->hwdescs.dma & 0xfffffff0) |
RCAR_DMADPBASE_SEL);
rcar_dmac_chan_write(chan, RCAR_DMACHCRB,
RCAR_DMACHCRB_DCNT(desc->nchunks - 1) |
RCAR_DMACHCRB_DRST);
/*
* Errata: When descriptor memory is accessed through an IOMMU
* the DMADAR register isn't initialized automatically from the
* first descriptor at beginning of transfer by the DMAC like it
* should. Initialize it manually with the destination address
* of the first chunk.
*/
rcar_dmac_chan_write(chan, RCAR_DMADAR,
chunk->dst_addr & 0xffffffff);
/*
* Program the descriptor stage interrupt to occur after the end
* of the first stage.
*/
rcar_dmac_chan_write(chan, RCAR_DMADPCR, RCAR_DMADPCR_DIPT(1));
chcr |= RCAR_DMACHCR_RPT_SAR | RCAR_DMACHCR_RPT_DAR
| RCAR_DMACHCR_RPT_TCR | RCAR_DMACHCR_DPB;
/*
* If the descriptor isn't cyclic enable normal descriptor mode
* and the transfer completion interrupt.
*/
if (!desc->cyclic)
chcr |= RCAR_DMACHCR_DPM_ENABLED | RCAR_DMACHCR_IE;
/*
* If the descriptor is cyclic and has a callback enable the
* descriptor stage interrupt in infinite repeat mode.
*/
else if (desc->async_tx.callback)
chcr |= RCAR_DMACHCR_DPM_INFINITE | RCAR_DMACHCR_DSIE;
/*
* Otherwise just select infinite repeat mode without any
* interrupt.
*/
else
chcr |= RCAR_DMACHCR_DPM_INFINITE;
} else {
struct rcar_dmac_xfer_chunk *chunk = desc->running;
dev_dbg(chan->chan.device->dev,
"chan%u: queue chunk %p: %u@%pad -> %pad\n",
chan->index, chunk, chunk->size, &chunk->src_addr,
&chunk->dst_addr);
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
rcar_dmac_chan_write(chan, RCAR_DMAFIXSAR,
chunk->src_addr >> 32);
rcar_dmac_chan_write(chan, RCAR_DMAFIXDAR,
chunk->dst_addr >> 32);
#endif
rcar_dmac_chan_write(chan, RCAR_DMASAR,
chunk->src_addr & 0xffffffff);
rcar_dmac_chan_write(chan, RCAR_DMADAR,
chunk->dst_addr & 0xffffffff);
rcar_dmac_chan_write(chan, RCAR_DMATCR,
chunk->size >> desc->xfer_shift);
chcr |= RCAR_DMACHCR_DPM_DISABLED | RCAR_DMACHCR_IE;
}
rcar_dmac_chan_write(chan, RCAR_DMACHCR,
chcr | RCAR_DMACHCR_DE | RCAR_DMACHCR_CAIE);
}
static int rcar_dmac_init(struct rcar_dmac *dmac)
{
u16 dmaor;
/* Clear all channels and enable the DMAC globally. */
rcar_dmac_write(dmac, RCAR_DMACHCLR, dmac->channels_mask);
rcar_dmac_write(dmac, RCAR_DMAOR,
RCAR_DMAOR_PRI_FIXED | RCAR_DMAOR_DME);
dmaor = rcar_dmac_read(dmac, RCAR_DMAOR);
if ((dmaor & (RCAR_DMAOR_AE | RCAR_DMAOR_DME)) != RCAR_DMAOR_DME) {
dev_warn(dmac->dev, "DMAOR initialization failed.\n");
return -EIO;
}
return 0;
}
/* -----------------------------------------------------------------------------
* Descriptors submission
*/
static dma_cookie_t rcar_dmac_tx_submit(struct dma_async_tx_descriptor *tx)
{
struct rcar_dmac_chan *chan = to_rcar_dmac_chan(tx->chan);
struct rcar_dmac_desc *desc = to_rcar_dmac_desc(tx);
unsigned long flags;
dma_cookie_t cookie;
spin_lock_irqsave(&chan->lock, flags);
cookie = dma_cookie_assign(tx);
dev_dbg(chan->chan.device->dev, "chan%u: submit #%d@%p\n",
chan->index, tx->cookie, desc);
list_add_tail(&desc->node, &chan->desc.pending);
desc->running = list_first_entry(&desc->chunks,
struct rcar_dmac_xfer_chunk, node);
spin_unlock_irqrestore(&chan->lock, flags);
return cookie;
}
/* -----------------------------------------------------------------------------
* Descriptors allocation and free
*/
/*
* rcar_dmac_desc_alloc - Allocate a page worth of DMA descriptors
* @chan: the DMA channel
* @gfp: allocation flags
*/
static int rcar_dmac_desc_alloc(struct rcar_dmac_chan *chan, gfp_t gfp)
{
struct rcar_dmac_desc_page *page;
unsigned long flags;
LIST_HEAD(list);
unsigned int i;
page = (void *)get_zeroed_page(gfp);
if (!page)
return -ENOMEM;
for (i = 0; i < RCAR_DMAC_DESCS_PER_PAGE; ++i) {
struct rcar_dmac_desc *desc = &page->descs[i];
dma_async_tx_descriptor_init(&desc->async_tx, &chan->chan);
desc->async_tx.tx_submit = rcar_dmac_tx_submit;
INIT_LIST_HEAD(&desc->chunks);
list_add_tail(&desc->node, &list);
}
spin_lock_irqsave(&chan->lock, flags);
list_splice_tail(&list, &chan->desc.free);
list_add_tail(&page->node, &chan->desc.pages);
spin_unlock_irqrestore(&chan->lock, flags);
return 0;
}
/*
* rcar_dmac_desc_put - Release a DMA transfer descriptor
* @chan: the DMA channel
* @desc: the descriptor
*
* Put the descriptor and its transfer chunk descriptors back in the channel's
* free descriptors lists. The descriptor's chunks list will be reinitialized to
* an empty list as a result.
*
* The descriptor must have been removed from the channel's lists before calling
* this function.
*/
static void rcar_dmac_desc_put(struct rcar_dmac_chan *chan,
struct rcar_dmac_desc *desc)
{
unsigned long flags;
spin_lock_irqsave(&chan->lock, flags);
list_splice_tail_init(&desc->chunks, &chan->desc.chunks_free);
list_add(&desc->node, &chan->desc.free);
spin_unlock_irqrestore(&chan->lock, flags);
}
static void rcar_dmac_desc_recycle_acked(struct rcar_dmac_chan *chan)
{
struct rcar_dmac_desc *desc, *_desc;
unsigned long flags;
LIST_HEAD(list);
/*
* We have to temporarily move all descriptors from the wait list to a
* local list as iterating over the wait list, even with
* list_for_each_entry_safe, isn't safe if we release the channel lock
* around the rcar_dmac_desc_put() call.
*/
spin_lock_irqsave(&chan->lock, flags);
list_splice_init(&chan->desc.wait, &list);
spin_unlock_irqrestore(&chan->lock, flags);
list_for_each_entry_safe(desc, _desc, &list, node) {
if (async_tx_test_ack(&desc->async_tx)) {
list_del(&desc->node);
rcar_dmac_desc_put(chan, desc);
}
}
if (list_empty(&list))
return;
/* Put the remaining descriptors back in the wait list. */
spin_lock_irqsave(&chan->lock, flags);
list_splice(&list, &chan->desc.wait);
spin_unlock_irqrestore(&chan->lock, flags);
}
/*
* rcar_dmac_desc_get - Allocate a descriptor for a DMA transfer
* @chan: the DMA channel
*
* Locking: This function must be called in a non-atomic context.
*
* Return: A pointer to the allocated descriptor or NULL if no descriptor can
* be allocated.
*/
static struct rcar_dmac_desc *rcar_dmac_desc_get(struct rcar_dmac_chan *chan)
{
struct rcar_dmac_desc *desc;
unsigned long flags;
int ret;
/* Recycle acked descriptors before attempting allocation. */
rcar_dmac_desc_recycle_acked(chan);
spin_lock_irqsave(&chan->lock, flags);
while (list_empty(&chan->desc.free)) {
/*
* No free descriptors, allocate a page worth of them and try
* again, as someone else could race us to get the newly
* allocated descriptors. If the allocation fails return an
* error.
*/
spin_unlock_irqrestore(&chan->lock, flags);
ret = rcar_dmac_desc_alloc(chan, GFP_NOWAIT);
if (ret < 0)
return NULL;
spin_lock_irqsave(&chan->lock, flags);
}
desc = list_first_entry(&chan->desc.free, struct rcar_dmac_desc, node);
list_del(&desc->node);
spin_unlock_irqrestore(&chan->lock, flags);
return desc;
}
/*
* rcar_dmac_xfer_chunk_alloc - Allocate a page worth of transfer chunks
* @chan: the DMA channel
* @gfp: allocation flags
*/
static int rcar_dmac_xfer_chunk_alloc(struct rcar_dmac_chan *chan, gfp_t gfp)
{
struct rcar_dmac_desc_page *page;
unsigned long flags;
LIST_HEAD(list);
unsigned int i;
page = (void *)get_zeroed_page(gfp);
if (!page)
return -ENOMEM;
for (i = 0; i < RCAR_DMAC_XFER_CHUNKS_PER_PAGE; ++i) {
struct rcar_dmac_xfer_chunk *chunk = &page->chunks[i];
list_add_tail(&chunk->node, &list);
}
spin_lock_irqsave(&chan->lock, flags);
list_splice_tail(&list, &chan->desc.chunks_free);
list_add_tail(&page->node, &chan->desc.pages);
spin_unlock_irqrestore(&chan->lock, flags);
return 0;
}
/*
* rcar_dmac_xfer_chunk_get - Allocate a transfer chunk for a DMA transfer
* @chan: the DMA channel
*
* Locking: This function must be called in a non-atomic context.
*
* Return: A pointer to the allocated transfer chunk descriptor or NULL if no
* descriptor can be allocated.
*/
static struct rcar_dmac_xfer_chunk *
rcar_dmac_xfer_chunk_get(struct rcar_dmac_chan *chan)
{
struct rcar_dmac_xfer_chunk *chunk;
unsigned long flags;
int ret;
spin_lock_irqsave(&chan->lock, flags);
while (list_empty(&chan->desc.chunks_free)) {
/*
* No free descriptors, allocate a page worth of them and try
* again, as someone else could race us to get the newly
* allocated descriptors. If the allocation fails return an
* error.
*/
spin_unlock_irqrestore(&chan->lock, flags);
ret = rcar_dmac_xfer_chunk_alloc(chan, GFP_NOWAIT);
if (ret < 0)
return NULL;
spin_lock_irqsave(&chan->lock, flags);
}
chunk = list_first_entry(&chan->desc.chunks_free,
struct rcar_dmac_xfer_chunk, node);
list_del(&chunk->node);
spin_unlock_irqrestore(&chan->lock, flags);
return chunk;
}
static void rcar_dmac_realloc_hwdesc(struct rcar_dmac_chan *chan,
struct rcar_dmac_desc *desc, size_t size)
{
/*
* dma_alloc_coherent() allocates memory in page size increments. To
* avoid reallocating the hardware descriptors when the allocated size
* wouldn't change align the requested size to a multiple of the page
* size.
*/
size = PAGE_ALIGN(size);
if (desc->hwdescs.size == size)
return;
if (desc->hwdescs.mem) {
dma_free_coherent(chan->chan.device->dev, desc->hwdescs.size,
desc->hwdescs.mem, desc->hwdescs.dma);
desc->hwdescs.mem = NULL;
desc->hwdescs.size = 0;
}
if (!size)
return;
desc->hwdescs.mem = dma_alloc_coherent(chan->chan.device->dev, size,
&desc->hwdescs.dma, GFP_NOWAIT);
if (!desc->hwdescs.mem)
return;
desc->hwdescs.size = size;
}
static int rcar_dmac_fill_hwdesc(struct rcar_dmac_chan *chan,
struct rcar_dmac_desc *desc)
{
struct rcar_dmac_xfer_chunk *chunk;
struct rcar_dmac_hw_desc *hwdesc;
rcar_dmac_realloc_hwdesc(chan, desc, desc->nchunks * sizeof(*hwdesc));
hwdesc = desc->hwdescs.mem;
if (!hwdesc)
return -ENOMEM;
list_for_each_entry(chunk, &desc->chunks, node) {
hwdesc->sar = chunk->src_addr;
hwdesc->dar = chunk->dst_addr;
hwdesc->tcr = chunk->size >> desc->xfer_shift;
hwdesc++;
}
return 0;
}
/* -----------------------------------------------------------------------------
* Stop and reset
*/
static void rcar_dmac_chcr_de_barrier(struct rcar_dmac_chan *chan)
{
u32 chcr;
unsigned int i;
/*
* Ensure that the setting of the DE bit is actually 0 after
* clearing it.
*/
for (i = 0; i < 1024; i++) {
chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
if (!(chcr & RCAR_DMACHCR_DE))
return;
udelay(1);
}
dev_err(chan->chan.device->dev, "CHCR DE check error\n");
}
static void rcar_dmac_clear_chcr_de(struct rcar_dmac_chan *chan)
{
u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
/* set DE=0 and flush remaining data */
rcar_dmac_chan_write(chan, RCAR_DMACHCR, (chcr & ~RCAR_DMACHCR_DE));
/* make sure all remaining data was flushed */
rcar_dmac_chcr_de_barrier(chan);
}
static void rcar_dmac_chan_halt(struct rcar_dmac_chan *chan)
{
u32 chcr = rcar_dmac_chan_read(chan, RCAR_DMACHCR);
chcr &= ~(RCAR_DMACHCR_DSE | RCAR_DMACHCR_DSIE | RCAR_DMACHCR_IE |
RCAR_DMACHCR_TE | RCAR_DMACHCR_DE |
RCAR_DMACHCR_CAE | RCAR_DMACHCR_CAIE);
rcar_dmac_chan_write(chan, RCAR_DMACHCR, chcr);
rcar_dmac_chcr_de_barrier(chan);
}
static void rcar_dmac_chan_reinit(struct rcar_dmac_chan *chan)
{
struct rcar_dmac_desc *desc, *_desc;
unsigned long flags;
LIST_HEAD(descs);
spin_lock_irqsave(&chan->lock, flags);
/* Move all non-free descriptors to the local lists. */
list_splice_init(&chan->desc.pending, &descs);
list_splice_init(&chan->desc.active, &descs);
list_splice_init(&chan->desc.done, &descs);
list_splice_init(&chan->desc.wait, &descs);
chan->desc.running = NULL;
spin_unlock_irqrestore(&chan->lock, flags);
list_for_each_entry_safe(desc, _desc, &descs, node) {
list_del(&desc->node);
rcar_dmac_desc_put(chan, desc);
}
}
static void rcar_dmac_stop_all_chan(struct rcar_dmac *dmac)
{
unsigned int i;
/* Stop all channels. */
for (i = 0; i < dmac->n_channels; ++i) {
struct rcar_dmac_chan *chan = &dmac->channels[i];
if (!(dmac->channels_mask & BIT(i)))
continue;
/* Stop and reinitialize the channel. */
spin_lock_irq(&chan->lock);
rcar_dmac_chan_halt(chan);
spin_unlock_irq(&chan->lock);
}
}
static int rcar_dmac_chan_pause(struct dma_chan *chan)
{
unsigned long flags;
struct rcar_dmac_chan *rchan = to_rcar_dmac_chan(chan);
spin_lock_irqsave(&rchan->lock, flags);
rcar_dmac_clear_chcr_de(rchan);
spin_unlock_irqrestore(&rchan->lock, flags);
return 0;
}
/* -----------------------------------------------------------------------------
* Descriptors preparation
*/
static void rcar_dmac_chan_configure_desc(struct rcar_dmac_chan *chan,
struct rcar_dmac_desc *desc)
{
static const u32 chcr_ts[] = {
RCAR_DMACHCR_TS_1B, RCAR_DMACHCR_TS_2B,
RCAR_DMACHCR_TS_4B, RCAR_DMACHCR_TS_8B,
RCAR_DMACHCR_TS_16B, RCAR_DMACHCR_TS_32B,
RCAR_DMACHCR_TS_64B,
};
unsigned int xfer_size;
u32 chcr;
switch (desc->direction) {
case DMA_DEV_TO_MEM:
chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_FIXED
| RCAR_DMACHCR_RS_DMARS;
xfer_size = chan->src.xfer_size;
break;
case DMA_MEM_TO_DEV:
chcr = RCAR_DMACHCR_DM_FIXED | RCAR_DMACHCR_SM_INC
| RCAR_DMACHCR_RS_DMARS;
xfer_size = chan->dst.xfer_size;
break;
case DMA_MEM_TO_MEM:
default:
chcr = RCAR_DMACHCR_DM_INC | RCAR_DMACHCR_SM_INC
| RCAR_DMACHCR_RS_AUTO;
xfer_size = RCAR_DMAC_MEMCPY_XFER_SIZE;
break;
}
desc->xfer_shift = ilog2(xfer_size);
desc->chcr = chcr | chcr_ts[desc->xfer_shift];
}
/*
* rcar_dmac_chan_prep_sg - prepare transfer descriptors from an SG list
*
* Common routine for public (MEMCPY) and slave DMA. The MEMCPY case is also
* converted to scatter-gather to guarantee consistent locking and a correct
* list manipulation. For slave DMA direction carries the usual meaning, and,
* logically, the SG list is RAM and the addr variable contains slave address,
* e.g., the FIFO I/O register. For MEMCPY direction equals DMA_MEM_TO_MEM
* and the SG list contains only one element and points at the source buffer.
*/
static struct dma_async_tx_descriptor *
rcar_dmac_chan_prep_sg(struct rcar_dmac_chan *chan, struct scatterlist *sgl,
unsigned int sg_len, dma_addr_t dev_addr,
enum dma_transfer_direction dir, unsigned long dma_flags,
bool cyclic)
{
struct rcar_dmac_xfer_chunk *chunk;
struct rcar_dmac_desc *desc;
struct scatterlist *sg;
unsigned int nchunks = 0;
unsigned int max_chunk_size;
unsigned int full_size = 0;
bool cross_boundary = false;
unsigned int i;
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
u32 high_dev_addr;
u32 high_mem_addr;
#endif
desc = rcar_dmac_desc_get(chan);
if (!desc)
return NULL;
desc->async_tx.flags = dma_flags;
desc->async_tx.cookie = -EBUSY;
desc->cyclic = cyclic;
desc->direction = dir;
rcar_dmac_chan_configure_desc(chan, desc);
max_chunk_size = RCAR_DMATCR_MASK << desc->xfer_shift;
/*
* Allocate and fill the transfer chunk descriptors. We own the only
* reference to the DMA descriptor, there's no need for locking.
*/
for_each_sg(sgl, sg, sg_len, i) {
dma_addr_t mem_addr = sg_dma_address(sg);
unsigned int len = sg_dma_len(sg);
full_size += len;
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
if (i == 0) {
high_dev_addr = dev_addr >> 32;
high_mem_addr = mem_addr >> 32;
}
if ((dev_addr >> 32 != high_dev_addr) ||
(mem_addr >> 32 != high_mem_addr))
cross_boundary = true;
#endif
while (len) {
unsigned int size = min(len, max_chunk_size);
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
/*
* Prevent individual transfers from crossing 4GB
* boundaries.
*/
if (dev_addr >> 32 != (dev_addr + size - 1) >> 32) {
size = ALIGN(dev_addr, 1ULL << 32) - dev_addr;
cross_boundary = true;
}
if (mem_addr >> 32 != (mem_addr + size - 1) >> 32) {
size = ALIGN(mem_addr, 1ULL << 32) - mem_addr;
cross_boundary = true;
}
#endif
chunk = rcar_dmac_xfer_chunk_get(chan);
if (!chunk) {
rcar_dmac_desc_put(chan, desc);
return NULL;
}
if (dir == DMA_DEV_TO_MEM) {
chunk->src_addr = dev_addr;
chunk->dst_addr = mem_addr;
} else {
chunk->src_addr = mem_addr;
chunk->dst_addr = dev_addr;
}
chunk->size = size;
dev_dbg(chan->chan.device->dev,
"chan%u: chunk %p/%p sgl %u@%p, %u/%u %pad -> %pad\n",
chan->index, chunk, desc, i, sg, size, len,
&chunk->src_addr, &chunk->dst_addr);
mem_addr += size;
if (dir == DMA_MEM_TO_MEM)
dev_addr += size;
len -= size;
list_add_tail(&chunk->node, &desc->chunks);
nchunks++;
}