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cmd.c
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cmd.c
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/*
* Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <linux/highmem.h>
#include <linux/module.h>
#include <linux/errno.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/random.h>
#include <linux/io-mapping.h>
#include <linux/mlx5/driver.h>
#include <linux/mlx5/eq.h>
#include <linux/debugfs.h>
#include "mlx5_core.h"
#include "lib/eq.h"
enum {
CMD_IF_REV = 5,
};
enum {
CMD_MODE_POLLING,
CMD_MODE_EVENTS
};
enum {
MLX5_CMD_DELIVERY_STAT_OK = 0x0,
MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
};
static struct mlx5_cmd_work_ent *
cmd_alloc_ent(struct mlx5_cmd *cmd, struct mlx5_cmd_msg *in,
struct mlx5_cmd_msg *out, void *uout, int uout_size,
mlx5_cmd_cbk_t cbk, void *context, int page_queue)
{
gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
struct mlx5_cmd_work_ent *ent;
ent = kzalloc(sizeof(*ent), alloc_flags);
if (!ent)
return ERR_PTR(-ENOMEM);
ent->idx = -EINVAL;
ent->in = in;
ent->out = out;
ent->uout = uout;
ent->uout_size = uout_size;
ent->callback = cbk;
ent->context = context;
ent->cmd = cmd;
ent->page_queue = page_queue;
refcount_set(&ent->refcnt, 1);
return ent;
}
static void cmd_free_ent(struct mlx5_cmd_work_ent *ent)
{
kfree(ent);
}
static u8 alloc_token(struct mlx5_cmd *cmd)
{
u8 token;
spin_lock(&cmd->token_lock);
cmd->token++;
if (cmd->token == 0)
cmd->token++;
token = cmd->token;
spin_unlock(&cmd->token_lock);
return token;
}
static int cmd_alloc_index(struct mlx5_cmd *cmd)
{
unsigned long flags;
int ret;
spin_lock_irqsave(&cmd->alloc_lock, flags);
ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
if (ret < cmd->max_reg_cmds)
clear_bit(ret, &cmd->bitmask);
spin_unlock_irqrestore(&cmd->alloc_lock, flags);
return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
}
static void cmd_free_index(struct mlx5_cmd *cmd, int idx)
{
unsigned long flags;
spin_lock_irqsave(&cmd->alloc_lock, flags);
set_bit(idx, &cmd->bitmask);
spin_unlock_irqrestore(&cmd->alloc_lock, flags);
}
static void cmd_ent_get(struct mlx5_cmd_work_ent *ent)
{
refcount_inc(&ent->refcnt);
}
static void cmd_ent_put(struct mlx5_cmd_work_ent *ent)
{
if (!refcount_dec_and_test(&ent->refcnt))
return;
if (ent->idx >= 0) {
struct mlx5_cmd *cmd = ent->cmd;
cmd_free_index(cmd, ent->idx);
up(ent->page_queue ? &cmd->pages_sem : &cmd->sem);
}
cmd_free_ent(ent);
}
static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
{
return cmd->cmd_buf + (idx << cmd->log_stride);
}
static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
{
int size = msg->len;
int blen = size - min_t(int, sizeof(msg->first.data), size);
return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
}
static u8 xor8_buf(void *buf, size_t offset, int len)
{
u8 *ptr = buf;
u8 sum = 0;
int i;
int end = len + offset;
for (i = offset; i < end; i++)
sum ^= ptr[i];
return sum;
}
static int verify_block_sig(struct mlx5_cmd_prot_block *block)
{
size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
int xor_len = sizeof(*block) - sizeof(block->data) - 1;
if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
return -EINVAL;
if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
return -EINVAL;
return 0;
}
static void calc_block_sig(struct mlx5_cmd_prot_block *block)
{
int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
}
static void calc_chain_sig(struct mlx5_cmd_msg *msg)
{
struct mlx5_cmd_mailbox *next = msg->next;
int n = mlx5_calc_cmd_blocks(msg);
int i = 0;
for (i = 0; i < n && next; i++) {
calc_block_sig(next->buf);
next = next->next;
}
}
static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
{
ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
if (csum) {
calc_chain_sig(ent->in);
calc_chain_sig(ent->out);
}
}
static void poll_timeout(struct mlx5_cmd_work_ent *ent)
{
unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
u8 own;
do {
own = READ_ONCE(ent->lay->status_own);
if (!(own & CMD_OWNER_HW)) {
ent->ret = 0;
return;
}
cond_resched();
} while (time_before(jiffies, poll_end));
ent->ret = -ETIMEDOUT;
}
static int verify_signature(struct mlx5_cmd_work_ent *ent)
{
struct mlx5_cmd_mailbox *next = ent->out->next;
int n = mlx5_calc_cmd_blocks(ent->out);
int err;
u8 sig;
int i = 0;
sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
if (sig != 0xff)
return -EINVAL;
for (i = 0; i < n && next; i++) {
err = verify_block_sig(next->buf);
if (err)
return err;
next = next->next;
}
return 0;
}
static void dump_buf(void *buf, int size, int data_only, int offset)
{
__be32 *p = buf;
int i;
for (i = 0; i < size; i += 16) {
pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
be32_to_cpu(p[1]), be32_to_cpu(p[2]),
be32_to_cpu(p[3]));
p += 4;
offset += 16;
}
if (!data_only)
pr_debug("\n");
}
static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
u32 *synd, u8 *status)
{
*synd = 0;
*status = 0;
switch (op) {
case MLX5_CMD_OP_TEARDOWN_HCA:
case MLX5_CMD_OP_DISABLE_HCA:
case MLX5_CMD_OP_MANAGE_PAGES:
case MLX5_CMD_OP_DESTROY_MKEY:
case MLX5_CMD_OP_DESTROY_EQ:
case MLX5_CMD_OP_DESTROY_CQ:
case MLX5_CMD_OP_DESTROY_QP:
case MLX5_CMD_OP_DESTROY_PSV:
case MLX5_CMD_OP_DESTROY_SRQ:
case MLX5_CMD_OP_DESTROY_XRC_SRQ:
case MLX5_CMD_OP_DESTROY_XRQ:
case MLX5_CMD_OP_DESTROY_DCT:
case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
case MLX5_CMD_OP_DEALLOC_PD:
case MLX5_CMD_OP_DEALLOC_UAR:
case MLX5_CMD_OP_DETACH_FROM_MCG:
case MLX5_CMD_OP_DEALLOC_XRCD:
case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
case MLX5_CMD_OP_DESTROY_LAG:
case MLX5_CMD_OP_DESTROY_VPORT_LAG:
case MLX5_CMD_OP_DESTROY_TIR:
case MLX5_CMD_OP_DESTROY_SQ:
case MLX5_CMD_OP_DESTROY_RQ:
case MLX5_CMD_OP_DESTROY_RMP:
case MLX5_CMD_OP_DESTROY_TIS:
case MLX5_CMD_OP_DESTROY_RQT:
case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
case MLX5_CMD_OP_2ERR_QP:
case MLX5_CMD_OP_2RST_QP:
case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
case MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT:
case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
case MLX5_CMD_OP_FPGA_DESTROY_QP:
case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
case MLX5_CMD_OP_DEALLOC_MEMIC:
case MLX5_CMD_OP_PAGE_FAULT_RESUME:
case MLX5_CMD_OP_QUERY_ESW_FUNCTIONS:
return MLX5_CMD_STAT_OK;
case MLX5_CMD_OP_QUERY_HCA_CAP:
case MLX5_CMD_OP_QUERY_ADAPTER:
case MLX5_CMD_OP_INIT_HCA:
case MLX5_CMD_OP_ENABLE_HCA:
case MLX5_CMD_OP_QUERY_PAGES:
case MLX5_CMD_OP_SET_HCA_CAP:
case MLX5_CMD_OP_QUERY_ISSI:
case MLX5_CMD_OP_SET_ISSI:
case MLX5_CMD_OP_CREATE_MKEY:
case MLX5_CMD_OP_QUERY_MKEY:
case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
case MLX5_CMD_OP_CREATE_EQ:
case MLX5_CMD_OP_QUERY_EQ:
case MLX5_CMD_OP_GEN_EQE:
case MLX5_CMD_OP_CREATE_CQ:
case MLX5_CMD_OP_QUERY_CQ:
case MLX5_CMD_OP_MODIFY_CQ:
case MLX5_CMD_OP_CREATE_QP:
case MLX5_CMD_OP_RST2INIT_QP:
case MLX5_CMD_OP_INIT2RTR_QP:
case MLX5_CMD_OP_RTR2RTS_QP:
case MLX5_CMD_OP_RTS2RTS_QP:
case MLX5_CMD_OP_SQERR2RTS_QP:
case MLX5_CMD_OP_QUERY_QP:
case MLX5_CMD_OP_SQD_RTS_QP:
case MLX5_CMD_OP_INIT2INIT_QP:
case MLX5_CMD_OP_CREATE_PSV:
case MLX5_CMD_OP_CREATE_SRQ:
case MLX5_CMD_OP_QUERY_SRQ:
case MLX5_CMD_OP_ARM_RQ:
case MLX5_CMD_OP_CREATE_XRC_SRQ:
case MLX5_CMD_OP_QUERY_XRC_SRQ:
case MLX5_CMD_OP_ARM_XRC_SRQ:
case MLX5_CMD_OP_CREATE_XRQ:
case MLX5_CMD_OP_QUERY_XRQ:
case MLX5_CMD_OP_ARM_XRQ:
case MLX5_CMD_OP_CREATE_DCT:
case MLX5_CMD_OP_DRAIN_DCT:
case MLX5_CMD_OP_QUERY_DCT:
case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
case MLX5_CMD_OP_QUERY_VPORT_STATE:
case MLX5_CMD_OP_MODIFY_VPORT_STATE:
case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
case MLX5_CMD_OP_SET_ROCE_ADDRESS:
case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
case MLX5_CMD_OP_QUERY_VNIC_ENV:
case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
case MLX5_CMD_OP_ALLOC_Q_COUNTER:
case MLX5_CMD_OP_QUERY_Q_COUNTER:
case MLX5_CMD_OP_SET_MONITOR_COUNTER:
case MLX5_CMD_OP_ARM_MONITOR_COUNTER:
case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
case MLX5_CMD_OP_QUERY_RATE_LIMIT:
case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
case MLX5_CMD_OP_ALLOC_PD:
case MLX5_CMD_OP_ALLOC_UAR:
case MLX5_CMD_OP_CONFIG_INT_MODERATION:
case MLX5_CMD_OP_ACCESS_REG:
case MLX5_CMD_OP_ATTACH_TO_MCG:
case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
case MLX5_CMD_OP_MAD_IFC:
case MLX5_CMD_OP_QUERY_MAD_DEMUX:
case MLX5_CMD_OP_SET_MAD_DEMUX:
case MLX5_CMD_OP_NOP:
case MLX5_CMD_OP_ALLOC_XRCD:
case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
case MLX5_CMD_OP_QUERY_CONG_STATUS:
case MLX5_CMD_OP_MODIFY_CONG_STATUS:
case MLX5_CMD_OP_QUERY_CONG_PARAMS:
case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
case MLX5_CMD_OP_CREATE_LAG:
case MLX5_CMD_OP_MODIFY_LAG:
case MLX5_CMD_OP_QUERY_LAG:
case MLX5_CMD_OP_CREATE_VPORT_LAG:
case MLX5_CMD_OP_CREATE_TIR:
case MLX5_CMD_OP_MODIFY_TIR:
case MLX5_CMD_OP_QUERY_TIR:
case MLX5_CMD_OP_CREATE_SQ:
case MLX5_CMD_OP_MODIFY_SQ:
case MLX5_CMD_OP_QUERY_SQ:
case MLX5_CMD_OP_CREATE_RQ:
case MLX5_CMD_OP_MODIFY_RQ:
case MLX5_CMD_OP_QUERY_RQ:
case MLX5_CMD_OP_CREATE_RMP:
case MLX5_CMD_OP_MODIFY_RMP:
case MLX5_CMD_OP_QUERY_RMP:
case MLX5_CMD_OP_CREATE_TIS:
case MLX5_CMD_OP_MODIFY_TIS:
case MLX5_CMD_OP_QUERY_TIS:
case MLX5_CMD_OP_CREATE_RQT:
case MLX5_CMD_OP_MODIFY_RQT:
case MLX5_CMD_OP_QUERY_RQT:
case MLX5_CMD_OP_CREATE_FLOW_TABLE:
case MLX5_CMD_OP_QUERY_FLOW_TABLE:
case MLX5_CMD_OP_CREATE_FLOW_GROUP:
case MLX5_CMD_OP_QUERY_FLOW_GROUP:
case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
case MLX5_CMD_OP_FPGA_CREATE_QP:
case MLX5_CMD_OP_FPGA_MODIFY_QP:
case MLX5_CMD_OP_FPGA_QUERY_QP:
case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
case MLX5_CMD_OP_CREATE_UCTX:
case MLX5_CMD_OP_DESTROY_UCTX:
case MLX5_CMD_OP_CREATE_UMEM:
case MLX5_CMD_OP_DESTROY_UMEM:
case MLX5_CMD_OP_ALLOC_MEMIC:
case MLX5_CMD_OP_MODIFY_XRQ:
case MLX5_CMD_OP_RELEASE_XRQ_ERROR:
*status = MLX5_DRIVER_STATUS_ABORTED;
*synd = MLX5_DRIVER_SYND;
return -EIO;
default:
mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
return -EINVAL;
}
}
const char *mlx5_command_str(int command)
{
#define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
switch (command) {
MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
MLX5_COMMAND_STR_CASE(INIT_HCA);
MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
MLX5_COMMAND_STR_CASE(ENABLE_HCA);
MLX5_COMMAND_STR_CASE(DISABLE_HCA);
MLX5_COMMAND_STR_CASE(QUERY_PAGES);
MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
MLX5_COMMAND_STR_CASE(QUERY_ISSI);
MLX5_COMMAND_STR_CASE(SET_ISSI);
MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
MLX5_COMMAND_STR_CASE(CREATE_MKEY);
MLX5_COMMAND_STR_CASE(QUERY_MKEY);
MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
MLX5_COMMAND_STR_CASE(CREATE_EQ);
MLX5_COMMAND_STR_CASE(DESTROY_EQ);
MLX5_COMMAND_STR_CASE(QUERY_EQ);
MLX5_COMMAND_STR_CASE(GEN_EQE);
MLX5_COMMAND_STR_CASE(CREATE_CQ);
MLX5_COMMAND_STR_CASE(DESTROY_CQ);
MLX5_COMMAND_STR_CASE(QUERY_CQ);
MLX5_COMMAND_STR_CASE(MODIFY_CQ);
MLX5_COMMAND_STR_CASE(CREATE_QP);
MLX5_COMMAND_STR_CASE(DESTROY_QP);
MLX5_COMMAND_STR_CASE(RST2INIT_QP);
MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
MLX5_COMMAND_STR_CASE(2ERR_QP);
MLX5_COMMAND_STR_CASE(2RST_QP);
MLX5_COMMAND_STR_CASE(QUERY_QP);
MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
MLX5_COMMAND_STR_CASE(CREATE_PSV);
MLX5_COMMAND_STR_CASE(DESTROY_PSV);
MLX5_COMMAND_STR_CASE(CREATE_SRQ);
MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
MLX5_COMMAND_STR_CASE(QUERY_SRQ);
MLX5_COMMAND_STR_CASE(ARM_RQ);
MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
MLX5_COMMAND_STR_CASE(CREATE_DCT);
MLX5_COMMAND_STR_CASE(DESTROY_DCT);
MLX5_COMMAND_STR_CASE(DRAIN_DCT);
MLX5_COMMAND_STR_CASE(QUERY_DCT);
MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
MLX5_COMMAND_STR_CASE(SET_MONITOR_COUNTER);
MLX5_COMMAND_STR_CASE(ARM_MONITOR_COUNTER);
MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
MLX5_COMMAND_STR_CASE(ALLOC_PD);
MLX5_COMMAND_STR_CASE(DEALLOC_PD);
MLX5_COMMAND_STR_CASE(ALLOC_UAR);
MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
MLX5_COMMAND_STR_CASE(ACCESS_REG);
MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
MLX5_COMMAND_STR_CASE(MAD_IFC);
MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
MLX5_COMMAND_STR_CASE(NOP);
MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
MLX5_COMMAND_STR_CASE(CREATE_LAG);
MLX5_COMMAND_STR_CASE(MODIFY_LAG);
MLX5_COMMAND_STR_CASE(QUERY_LAG);
MLX5_COMMAND_STR_CASE(DESTROY_LAG);
MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
MLX5_COMMAND_STR_CASE(CREATE_TIR);
MLX5_COMMAND_STR_CASE(MODIFY_TIR);
MLX5_COMMAND_STR_CASE(DESTROY_TIR);
MLX5_COMMAND_STR_CASE(QUERY_TIR);
MLX5_COMMAND_STR_CASE(CREATE_SQ);
MLX5_COMMAND_STR_CASE(MODIFY_SQ);
MLX5_COMMAND_STR_CASE(DESTROY_SQ);
MLX5_COMMAND_STR_CASE(QUERY_SQ);
MLX5_COMMAND_STR_CASE(CREATE_RQ);
MLX5_COMMAND_STR_CASE(MODIFY_RQ);
MLX5_COMMAND_STR_CASE(DESTROY_RQ);
MLX5_COMMAND_STR_CASE(QUERY_RQ);
MLX5_COMMAND_STR_CASE(CREATE_RMP);
MLX5_COMMAND_STR_CASE(MODIFY_RMP);
MLX5_COMMAND_STR_CASE(DESTROY_RMP);
MLX5_COMMAND_STR_CASE(QUERY_RMP);
MLX5_COMMAND_STR_CASE(CREATE_TIS);
MLX5_COMMAND_STR_CASE(MODIFY_TIS);
MLX5_COMMAND_STR_CASE(DESTROY_TIS);
MLX5_COMMAND_STR_CASE(QUERY_TIS);
MLX5_COMMAND_STR_CASE(CREATE_RQT);
MLX5_COMMAND_STR_CASE(MODIFY_RQT);
MLX5_COMMAND_STR_CASE(DESTROY_RQT);
MLX5_COMMAND_STR_CASE(QUERY_RQT);
MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
MLX5_COMMAND_STR_CASE(ALLOC_PACKET_REFORMAT_CONTEXT);
MLX5_COMMAND_STR_CASE(DEALLOC_PACKET_REFORMAT_CONTEXT);
MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
MLX5_COMMAND_STR_CASE(CREATE_XRQ);
MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
MLX5_COMMAND_STR_CASE(QUERY_XRQ);
MLX5_COMMAND_STR_CASE(ARM_XRQ);
MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
MLX5_COMMAND_STR_CASE(ALLOC_MEMIC);
MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC);
MLX5_COMMAND_STR_CASE(QUERY_ESW_FUNCTIONS);
MLX5_COMMAND_STR_CASE(CREATE_UCTX);
MLX5_COMMAND_STR_CASE(DESTROY_UCTX);
MLX5_COMMAND_STR_CASE(CREATE_UMEM);
MLX5_COMMAND_STR_CASE(DESTROY_UMEM);
MLX5_COMMAND_STR_CASE(RELEASE_XRQ_ERROR);
MLX5_COMMAND_STR_CASE(MODIFY_XRQ);
default: return "unknown command opcode";
}
}
static const char *cmd_status_str(u8 status)
{
switch (status) {
case MLX5_CMD_STAT_OK:
return "OK";
case MLX5_CMD_STAT_INT_ERR:
return "internal error";
case MLX5_CMD_STAT_BAD_OP_ERR:
return "bad operation";
case MLX5_CMD_STAT_BAD_PARAM_ERR:
return "bad parameter";
case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
return "bad system state";
case MLX5_CMD_STAT_BAD_RES_ERR:
return "bad resource";
case MLX5_CMD_STAT_RES_BUSY:
return "resource busy";
case MLX5_CMD_STAT_LIM_ERR:
return "limits exceeded";
case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
return "bad resource state";
case MLX5_CMD_STAT_IX_ERR:
return "bad index";
case MLX5_CMD_STAT_NO_RES_ERR:
return "no resources";
case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
return "bad input length";
case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
return "bad output length";
case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
return "bad QP state";
case MLX5_CMD_STAT_BAD_PKT_ERR:
return "bad packet (discarded)";
case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
return "bad size too many outstanding CQEs";
default:
return "unknown status";
}
}
static int cmd_status_to_err(u8 status)
{
switch (status) {
case MLX5_CMD_STAT_OK: return 0;
case MLX5_CMD_STAT_INT_ERR: return -EIO;
case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
default: return -EIO;
}
}
struct mlx5_ifc_mbox_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
u8 syndrome[0x20];
u8 reserved_at_40[0x40];
};
struct mlx5_ifc_mbox_in_bits {
u8 opcode[0x10];
u8 uid[0x10];
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
u8 reserved_at_40[0x40];
};
void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
{
*status = MLX5_GET(mbox_out, out, status);
*syndrome = MLX5_GET(mbox_out, out, syndrome);
}
static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
{
u32 syndrome;
u8 status;
u16 opcode;
u16 op_mod;
u16 uid;
mlx5_cmd_mbox_status(out, &status, &syndrome);
if (!status)
return 0;
opcode = MLX5_GET(mbox_in, in, opcode);
op_mod = MLX5_GET(mbox_in, in, op_mod);
uid = MLX5_GET(mbox_in, in, uid);
if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
mlx5_core_err_rl(dev,
"%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
mlx5_command_str(opcode), opcode, op_mod,
cmd_status_str(status), status, syndrome);
else
mlx5_core_dbg(dev,
"%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
mlx5_command_str(opcode),
opcode, op_mod,
cmd_status_str(status),
status,
syndrome);
return cmd_status_to_err(status);
}
static void dump_command(struct mlx5_core_dev *dev,
struct mlx5_cmd_work_ent *ent, int input)
{
struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
struct mlx5_cmd_mailbox *next = msg->next;
int n = mlx5_calc_cmd_blocks(msg);
int data_only;
u32 offset = 0;
int dump_len;
int i;
data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
if (data_only)
mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
"dump command data %s(0x%x) %s\n",
mlx5_command_str(op), op,
input ? "INPUT" : "OUTPUT");
else
mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
mlx5_command_str(op), op,
input ? "INPUT" : "OUTPUT");
if (data_only) {
if (input) {
dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
offset += sizeof(ent->lay->in);
} else {
dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
offset += sizeof(ent->lay->out);
}
} else {
dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
offset += sizeof(*ent->lay);
}
for (i = 0; i < n && next; i++) {
if (data_only) {
dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
dump_buf(next->buf, dump_len, 1, offset);
offset += MLX5_CMD_DATA_BLOCK_SIZE;
} else {
mlx5_core_dbg(dev, "command block:\n");
dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
offset += sizeof(struct mlx5_cmd_prot_block);
}
next = next->next;
}
if (data_only)
pr_debug("\n");
}
static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
{
return MLX5_GET(mbox_in, in->first.data, opcode);
}
static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
static void cb_timeout_handler(struct work_struct *work)
{
struct delayed_work *dwork = container_of(work, struct delayed_work,
work);
struct mlx5_cmd_work_ent *ent = container_of(dwork,
struct mlx5_cmd_work_ent,
cb_timeout_work);
struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
cmd);
mlx5_cmd_eq_recover(dev);
/* Maybe got handled by eq recover ? */
if (!test_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state)) {
mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, recovered after timeout\n", ent->idx,
mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in));
goto out; /* phew, already handled */
}
ent->ret = -ETIMEDOUT;
mlx5_core_warn(dev, "cmd[%d]: %s(0x%x) Async, timeout. Will cause a leak of a command resource\n",
ent->idx, mlx5_command_str(msg_to_opcode(ent->in)), msg_to_opcode(ent->in));
mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
out:
cmd_ent_put(ent); /* for the cmd_ent_get() took on schedule delayed work */
}
static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
struct mlx5_cmd_msg *msg);
static bool opcode_allowed(struct mlx5_cmd *cmd, u16 opcode)
{
if (cmd->allowed_opcode == CMD_ALLOWED_OPCODE_ALL)
return true;
return cmd->allowed_opcode == opcode;
}
bool mlx5_cmd_is_down(struct mlx5_core_dev *dev)
{
return pci_channel_offline(dev->pdev) ||
dev->cmd.state != MLX5_CMDIF_STATE_UP ||
dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR;
}
static void cmd_work_handler(struct work_struct *work)
{
struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
struct mlx5_cmd *cmd = ent->cmd;
struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
struct mlx5_cmd_layout *lay;
struct semaphore *sem;
unsigned long flags;
bool poll_cmd = ent->polling;
int alloc_ret;
int cmd_mode;
complete(&ent->handling);
sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
down(sem);
if (!ent->page_queue) {
alloc_ret = cmd_alloc_index(cmd);
if (alloc_ret < 0) {
mlx5_core_err_rl(dev, "failed to allocate command entry\n");
if (ent->callback) {
ent->callback(-EAGAIN, ent->context);
mlx5_free_cmd_msg(dev, ent->out);
free_msg(dev, ent->in);
cmd_ent_put(ent);
} else {
ent->ret = -EAGAIN;
complete(&ent->done);
}
up(sem);
return;
}
ent->idx = alloc_ret;
} else {
ent->idx = cmd->max_reg_cmds;
spin_lock_irqsave(&cmd->alloc_lock, flags);
clear_bit(ent->idx, &cmd->bitmask);
spin_unlock_irqrestore(&cmd->alloc_lock, flags);
}
cmd->ent_arr[ent->idx] = ent;
lay = get_inst(cmd, ent->idx);
ent->lay = lay;
memset(lay, 0, sizeof(*lay));
memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
ent->op = be32_to_cpu(lay->in[0]) >> 16;
if (ent->in->next)
lay->in_ptr = cpu_to_be64(ent->in->next->dma);
lay->inlen = cpu_to_be32(ent->in->len);
if (ent->out->next)
lay->out_ptr = cpu_to_be64(ent->out->next->dma);
lay->outlen = cpu_to_be32(ent->out->len);
lay->type = MLX5_PCI_CMD_XPORT;
lay->token = ent->token;
lay->status_own = CMD_OWNER_HW;
set_signature(ent, !cmd->checksum_disabled);
dump_command(dev, ent, 1);
ent->ts1 = ktime_get_ns();
cmd_mode = cmd->mode;
if (ent->callback && schedule_delayed_work(&ent->cb_timeout_work, cb_timeout))
cmd_ent_get(ent);
set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
/* Skip sending command to fw if internal error */
if (mlx5_cmd_is_down(dev) || !opcode_allowed(&dev->cmd, ent->op)) {
u8 status = 0;
u32 drv_synd;
ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
MLX5_SET(mbox_out, ent->out, status, status);
MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, true);
return;
}
cmd_ent_get(ent); /* for the _real_ FW event on completion */
/* ring doorbell after the descriptor is valid */
mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
wmb();
iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
/* if not in polling don't use ent after this point */
if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
poll_timeout(ent);
/* make sure we read the descriptor after ownership is SW */
rmb();
mlx5_cmd_comp_handler(dev, 1ULL << ent->idx, (ent->ret == -ETIMEDOUT));
}
}
static const char *deliv_status_to_str(u8 status)
{
switch (status) {
case MLX5_CMD_DELIVERY_STAT_OK:
return "no errors";
case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
return "signature error";
case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
return "token error";
case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
return "bad block number";
case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
return "output pointer not aligned to block size";