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lpc32xx_udc.c
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lpc32xx_udc.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* USB Gadget driver for LPC32xx
*
* Authors:
* Kevin Wells <kevin.wells@nxp.com>
* Mike James
* Roland Stigge <stigge@antcom.de>
*
* Copyright (C) 2006 Philips Semiconductors
* Copyright (C) 2009 NXP Semiconductors
* Copyright (C) 2012 Roland Stigge
*
* Note: This driver is based on original work done by Mike James for
* the LPC3180.
*/
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/dmapool.h>
#include <linux/i2c.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/prefetch.h>
#include <linux/proc_fs.h>
#include <linux/slab.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/usb/isp1301.h>
#ifdef CONFIG_USB_GADGET_DEBUG_FILES
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#endif
/*
* USB device configuration structure
*/
typedef void (*usc_chg_event)(int);
struct lpc32xx_usbd_cfg {
int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */
usc_chg_event conn_chgb; /* Connection change event (optional) */
usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
};
/*
* controller driver data structures
*/
/* 16 endpoints (not to be confused with 32 hardware endpoints) */
#define NUM_ENDPOINTS 16
/*
* IRQ indices make reading the code a little easier
*/
#define IRQ_USB_LP 0
#define IRQ_USB_HP 1
#define IRQ_USB_DEVDMA 2
#define IRQ_USB_ATX 3
#define EP_OUT 0 /* RX (from host) */
#define EP_IN 1 /* TX (to host) */
/* Returns the interrupt mask for the selected hardware endpoint */
#define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
#define EP_INT_TYPE 0
#define EP_ISO_TYPE 1
#define EP_BLK_TYPE 2
#define EP_CTL_TYPE 3
/* EP0 states */
#define WAIT_FOR_SETUP 0 /* Wait for setup packet */
#define DATA_IN 1 /* Expect dev->host transfer */
#define DATA_OUT 2 /* Expect host->dev transfer */
/* DD (DMA Descriptor) structure, requires word alignment, this is already
* defined in the LPC32XX USB device header file, but this version is slightly
* modified to tag some work data with each DMA descriptor. */
struct lpc32xx_usbd_dd_gad {
u32 dd_next_phy;
u32 dd_setup;
u32 dd_buffer_addr;
u32 dd_status;
u32 dd_iso_ps_mem_addr;
u32 this_dma;
u32 iso_status[6]; /* 5 spare */
u32 dd_next_v;
};
/*
* Logical endpoint structure
*/
struct lpc32xx_ep {
struct usb_ep ep;
struct list_head queue;
struct lpc32xx_udc *udc;
u32 hwep_num_base; /* Physical hardware EP */
u32 hwep_num; /* Maps to hardware endpoint */
u32 maxpacket;
u32 lep;
bool is_in;
bool req_pending;
u32 eptype;
u32 totalints;
bool wedge;
};
enum atx_type {
ISP1301,
STOTG04,
};
/*
* Common UDC structure
*/
struct lpc32xx_udc {
struct usb_gadget gadget;
struct usb_gadget_driver *driver;
struct platform_device *pdev;
struct device *dev;
spinlock_t lock;
struct i2c_client *isp1301_i2c_client;
/* Board and device specific */
struct lpc32xx_usbd_cfg *board;
void __iomem *udp_baseaddr;
int udp_irq[4];
struct clk *usb_slv_clk;
/* DMA support */
u32 *udca_v_base;
u32 udca_p_base;
struct dma_pool *dd_cache;
/* Common EP and control data */
u32 enabled_devints;
u32 enabled_hwepints;
u32 dev_status;
u32 realized_eps;
/* VBUS detection, pullup, and power flags */
u8 vbus;
u8 last_vbus;
int pullup;
int poweron;
enum atx_type atx;
/* Work queues related to I2C support */
struct work_struct pullup_job;
struct work_struct power_job;
/* USB device peripheral - various */
struct lpc32xx_ep ep[NUM_ENDPOINTS];
bool enabled;
bool clocked;
bool suspended;
int ep0state;
atomic_t enabled_ep_cnt;
wait_queue_head_t ep_disable_wait_queue;
};
/*
* Endpoint request
*/
struct lpc32xx_request {
struct usb_request req;
struct list_head queue;
struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
bool mapped;
bool send_zlp;
};
static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
{
return container_of(g, struct lpc32xx_udc, gadget);
}
#define ep_dbg(epp, fmt, arg...) \
dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
#define ep_err(epp, fmt, arg...) \
dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
#define ep_info(epp, fmt, arg...) \
dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
#define ep_warn(epp, fmt, arg...) \
dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
#define UDCA_BUFF_SIZE (128)
/**********************************************************************
* USB device controller register offsets
**********************************************************************/
#define USBD_DEVINTST(x) ((x) + 0x200)
#define USBD_DEVINTEN(x) ((x) + 0x204)
#define USBD_DEVINTCLR(x) ((x) + 0x208)
#define USBD_DEVINTSET(x) ((x) + 0x20C)
#define USBD_CMDCODE(x) ((x) + 0x210)
#define USBD_CMDDATA(x) ((x) + 0x214)
#define USBD_RXDATA(x) ((x) + 0x218)
#define USBD_TXDATA(x) ((x) + 0x21C)
#define USBD_RXPLEN(x) ((x) + 0x220)
#define USBD_TXPLEN(x) ((x) + 0x224)
#define USBD_CTRL(x) ((x) + 0x228)
#define USBD_DEVINTPRI(x) ((x) + 0x22C)
#define USBD_EPINTST(x) ((x) + 0x230)
#define USBD_EPINTEN(x) ((x) + 0x234)
#define USBD_EPINTCLR(x) ((x) + 0x238)
#define USBD_EPINTSET(x) ((x) + 0x23C)
#define USBD_EPINTPRI(x) ((x) + 0x240)
#define USBD_REEP(x) ((x) + 0x244)
#define USBD_EPIND(x) ((x) + 0x248)
#define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
/* DMA support registers only below */
/* Set, clear, or get enabled state of the DMA request status. If
* enabled, an IN or OUT token will start a DMA transfer for the EP */
#define USBD_DMARST(x) ((x) + 0x250)
#define USBD_DMARCLR(x) ((x) + 0x254)
#define USBD_DMARSET(x) ((x) + 0x258)
/* DMA UDCA head pointer */
#define USBD_UDCAH(x) ((x) + 0x280)
/* EP DMA status, enable, and disable. This is used to specifically
* enabled or disable DMA for a specific EP */
#define USBD_EPDMAST(x) ((x) + 0x284)
#define USBD_EPDMAEN(x) ((x) + 0x288)
#define USBD_EPDMADIS(x) ((x) + 0x28C)
/* DMA master interrupts enable and pending interrupts */
#define USBD_DMAINTST(x) ((x) + 0x290)
#define USBD_DMAINTEN(x) ((x) + 0x294)
/* DMA end of transfer interrupt enable, disable, status */
#define USBD_EOTINTST(x) ((x) + 0x2A0)
#define USBD_EOTINTCLR(x) ((x) + 0x2A4)
#define USBD_EOTINTSET(x) ((x) + 0x2A8)
/* New DD request interrupt enable, disable, status */
#define USBD_NDDRTINTST(x) ((x) + 0x2AC)
#define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
#define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
/* DMA error interrupt enable, disable, status */
#define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
#define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
#define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
/**********************************************************************
* USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
* USBD_DEVINTPRI register definitions
**********************************************************************/
#define USBD_ERR_INT (1 << 9)
#define USBD_EP_RLZED (1 << 8)
#define USBD_TXENDPKT (1 << 7)
#define USBD_RXENDPKT (1 << 6)
#define USBD_CDFULL (1 << 5)
#define USBD_CCEMPTY (1 << 4)
#define USBD_DEV_STAT (1 << 3)
#define USBD_EP_SLOW (1 << 2)
#define USBD_EP_FAST (1 << 1)
#define USBD_FRAME (1 << 0)
/**********************************************************************
* USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
* USBD_EPINTPRI register definitions
**********************************************************************/
/* End point selection macro (RX) */
#define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
/* End point selection macro (TX) */
#define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
/**********************************************************************
* USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
* USBD_EPDMAEN/USBD_EPDMADIS/
* USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
* USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
* USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
* register definitions
**********************************************************************/
/* Endpoint selection macro */
#define USBD_EP_SEL(e) (1 << (e))
/**********************************************************************
* SBD_DMAINTST/USBD_DMAINTEN
**********************************************************************/
#define USBD_SYS_ERR_INT (1 << 2)
#define USBD_NEW_DD_INT (1 << 1)
#define USBD_EOT_INT (1 << 0)
/**********************************************************************
* USBD_RXPLEN register definitions
**********************************************************************/
#define USBD_PKT_RDY (1 << 11)
#define USBD_DV (1 << 10)
#define USBD_PK_LEN_MASK 0x3FF
/**********************************************************************
* USBD_CTRL register definitions
**********************************************************************/
#define USBD_LOG_ENDPOINT(e) ((e) << 2)
#define USBD_WR_EN (1 << 1)
#define USBD_RD_EN (1 << 0)
/**********************************************************************
* USBD_CMDCODE register definitions
**********************************************************************/
#define USBD_CMD_CODE(c) ((c) << 16)
#define USBD_CMD_PHASE(p) ((p) << 8)
/**********************************************************************
* USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
**********************************************************************/
#define USBD_DMAEP(e) (1 << (e))
/* DD (DMA Descriptor) structure, requires word alignment */
struct lpc32xx_usbd_dd {
u32 *dd_next;
u32 dd_setup;
u32 dd_buffer_addr;
u32 dd_status;
u32 dd_iso_ps_mem_addr;
};
/* dd_setup bit defines */
#define DD_SETUP_ATLE_DMA_MODE 0x01
#define DD_SETUP_NEXT_DD_VALID 0x04
#define DD_SETUP_ISO_EP 0x10
#define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
#define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
/* dd_status bit defines */
#define DD_STATUS_DD_RETIRED 0x01
#define DD_STATUS_STS_MASK 0x1E
#define DD_STATUS_STS_NS 0x00 /* Not serviced */
#define DD_STATUS_STS_BS 0x02 /* Being serviced */
#define DD_STATUS_STS_NC 0x04 /* Normal completion */
#define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */
#define DD_STATUS_STS_DOR 0x08 /* Data overrun */
#define DD_STATUS_STS_SE 0x12 /* System error */
#define DD_STATUS_PKT_VAL 0x20 /* Packet valid */
#define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */
#define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */
#define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
#define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
/*
*
* Protocol engine bits below
*
*/
/* Device Interrupt Bit Definitions */
#define FRAME_INT 0x00000001
#define EP_FAST_INT 0x00000002
#define EP_SLOW_INT 0x00000004
#define DEV_STAT_INT 0x00000008
#define CCEMTY_INT 0x00000010
#define CDFULL_INT 0x00000020
#define RxENDPKT_INT 0x00000040
#define TxENDPKT_INT 0x00000080
#define EP_RLZED_INT 0x00000100
#define ERR_INT 0x00000200
/* Rx & Tx Packet Length Definitions */
#define PKT_LNGTH_MASK 0x000003FF
#define PKT_DV 0x00000400
#define PKT_RDY 0x00000800
/* USB Control Definitions */
#define CTRL_RD_EN 0x00000001
#define CTRL_WR_EN 0x00000002
/* Command Codes */
#define CMD_SET_ADDR 0x00D00500
#define CMD_CFG_DEV 0x00D80500
#define CMD_SET_MODE 0x00F30500
#define CMD_RD_FRAME 0x00F50500
#define DAT_RD_FRAME 0x00F50200
#define CMD_RD_TEST 0x00FD0500
#define DAT_RD_TEST 0x00FD0200
#define CMD_SET_DEV_STAT 0x00FE0500
#define CMD_GET_DEV_STAT 0x00FE0500
#define DAT_GET_DEV_STAT 0x00FE0200
#define CMD_GET_ERR_CODE 0x00FF0500
#define DAT_GET_ERR_CODE 0x00FF0200
#define CMD_RD_ERR_STAT 0x00FB0500
#define DAT_RD_ERR_STAT 0x00FB0200
#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
#define CMD_CLR_BUF 0x00F20500
#define DAT_CLR_BUF 0x00F20200
#define CMD_VALID_BUF 0x00FA0500
/* Device Address Register Definitions */
#define DEV_ADDR_MASK 0x7F
#define DEV_EN 0x80
/* Device Configure Register Definitions */
#define CONF_DVICE 0x01
/* Device Mode Register Definitions */
#define AP_CLK 0x01
#define INAK_CI 0x02
#define INAK_CO 0x04
#define INAK_II 0x08
#define INAK_IO 0x10
#define INAK_BI 0x20
#define INAK_BO 0x40
/* Device Status Register Definitions */
#define DEV_CON 0x01
#define DEV_CON_CH 0x02
#define DEV_SUS 0x04
#define DEV_SUS_CH 0x08
#define DEV_RST 0x10
/* Error Code Register Definitions */
#define ERR_EC_MASK 0x0F
#define ERR_EA 0x10
/* Error Status Register Definitions */
#define ERR_PID 0x01
#define ERR_UEPKT 0x02
#define ERR_DCRC 0x04
#define ERR_TIMOUT 0x08
#define ERR_EOP 0x10
#define ERR_B_OVRN 0x20
#define ERR_BTSTF 0x40
#define ERR_TGL 0x80
/* Endpoint Select Register Definitions */
#define EP_SEL_F 0x01
#define EP_SEL_ST 0x02
#define EP_SEL_STP 0x04
#define EP_SEL_PO 0x08
#define EP_SEL_EPN 0x10
#define EP_SEL_B_1_FULL 0x20
#define EP_SEL_B_2_FULL 0x40
/* Endpoint Status Register Definitions */
#define EP_STAT_ST 0x01
#define EP_STAT_DA 0x20
#define EP_STAT_RF_MO 0x40
#define EP_STAT_CND_ST 0x80
/* Clear Buffer Register Definitions */
#define CLR_BUF_PO 0x01
/* DMA Interrupt Bit Definitions */
#define EOT_INT 0x01
#define NDD_REQ_INT 0x02
#define SYS_ERR_INT 0x04
#define DRIVER_VERSION "1.03"
static const char driver_name[] = "lpc32xx_udc";
/*
*
* proc interface support
*
*/
#ifdef CONFIG_USB_GADGET_DEBUG_FILES
static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
static const char debug_filename[] = "driver/udc";
static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
{
struct lpc32xx_request *req;
seq_printf(s, "\n");
seq_printf(s, "%12s, maxpacket %4d %3s",
ep->ep.name, ep->ep.maxpacket,
ep->is_in ? "in" : "out");
seq_printf(s, " type %4s", epnames[ep->eptype]);
seq_printf(s, " ints: %12d", ep->totalints);
if (list_empty(&ep->queue))
seq_printf(s, "\t(queue empty)\n");
else {
list_for_each_entry(req, &ep->queue, queue) {
u32 length = req->req.actual;
seq_printf(s, "\treq %p len %d/%d buf %p\n",
&req->req, length,
req->req.length, req->req.buf);
}
}
}
static int udc_show(struct seq_file *s, void *unused)
{
struct lpc32xx_udc *udc = s->private;
struct lpc32xx_ep *ep;
unsigned long flags;
seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
spin_lock_irqsave(&udc->lock, flags);
seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
udc->vbus ? "present" : "off",
udc->enabled ? (udc->vbus ? "active" : "enabled") :
"disabled",
udc->gadget.is_selfpowered ? "self" : "VBUS",
udc->suspended ? ", suspended" : "",
udc->driver ? udc->driver->driver.name : "(none)");
if (udc->enabled && udc->vbus) {
proc_ep_show(s, &udc->ep[0]);
list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
proc_ep_show(s, ep);
}
spin_unlock_irqrestore(&udc->lock, flags);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(udc);
static void create_debug_file(struct lpc32xx_udc *udc)
{
debugfs_create_file(debug_filename, 0, NULL, udc, &udc_fops);
}
static void remove_debug_file(struct lpc32xx_udc *udc)
{
debugfs_lookup_and_remove(debug_filename, NULL);
}
#else
static inline void create_debug_file(struct lpc32xx_udc *udc) {}
static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
#endif
/* Primary initialization sequence for the ISP1301 transceiver */
static void isp1301_udc_configure(struct lpc32xx_udc *udc)
{
u8 value;
s32 vendor, product;
vendor = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00);
product = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02);
if (vendor == 0x0483 && product == 0xa0c4)
udc->atx = STOTG04;
/* LPC32XX only supports DAT_SE0 USB mode */
/* This sequence is important */
/* Disable transparent UART mode first */
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
(ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
MC1_UART_EN);
/* Set full speed and SE0 mode */
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
(ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
/*
* The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
*/
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
(ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
value = MC2_BI_DI;
if (udc->atx != STOTG04)
value |= MC2_SPD_SUSP_CTRL;
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
ISP1301_I2C_MODE_CONTROL_2, value);
/* Driver VBUS_DRV high or low depending on board setup */
if (udc->board->vbus_drv_pol != 0)
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
else
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
OTG1_VBUS_DRV);
/* Bi-directional mode with suspend control
* Enable both pulldowns for now - the pullup will be enable when VBUS
* is detected */
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
(ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
ISP1301_I2C_OTG_CONTROL_1,
(0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
/* Discharge VBUS (just in case) */
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
msleep(1);
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
(ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
OTG1_VBUS_DISCHRG);
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", vendor);
dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", product);
dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
}
/* Enables or disables the USB device pullup via the ISP1301 transceiver */
static void isp1301_pullup_set(struct lpc32xx_udc *udc)
{
if (udc->pullup)
/* Enable pullup for bus signalling */
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
else
/* Enable pullup for bus signalling */
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
OTG1_DP_PULLUP);
}
static void pullup_work(struct work_struct *work)
{
struct lpc32xx_udc *udc =
container_of(work, struct lpc32xx_udc, pullup_job);
isp1301_pullup_set(udc);
}
static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
int block)
{
if (en_pullup == udc->pullup)
return;
udc->pullup = en_pullup;
if (block)
isp1301_pullup_set(udc);
else
/* defer slow i2c pull up setting */
schedule_work(&udc->pullup_job);
}
#ifdef CONFIG_PM
/* Powers up or down the ISP1301 transceiver */
static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
{
/* There is no "global power down" register for stotg04 */
if (udc->atx == STOTG04)
return;
if (enable != 0)
/* Power up ISP1301 - this ISP1301 will automatically wakeup
when VBUS is detected */
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
MC2_GLOBAL_PWR_DN);
else
/* Power down ISP1301 */
i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
}
static void power_work(struct work_struct *work)
{
struct lpc32xx_udc *udc =
container_of(work, struct lpc32xx_udc, power_job);
isp1301_set_powerstate(udc, udc->poweron);
}
#endif
/*
*
* USB protocol engine command/data read/write helper functions
*
*/
/* Issues a single command to the USB device state machine */
static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
{
u32 pass = 0;
int to;
/* EP may lock on CLRI if this read isn't done */
u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
(void) tmp;
while (pass == 0) {
writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
/* Write command code */
writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
to = 10000;
while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
USBD_CCEMPTY) == 0) && (to > 0)) {
to--;
}
if (to > 0)
pass = 1;
cpu_relax();
}
}
/* Issues 2 commands (or command and data) to the USB device state machine */
static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
u32 data)
{
udc_protocol_cmd_w(udc, cmd);
udc_protocol_cmd_w(udc, data);
}
/* Issues a single command to the USB device state machine and reads
* response data */
static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
{
int to = 1000;
/* Write a command and read data from the protocol engine */
writel((USBD_CDFULL | USBD_CCEMPTY),
USBD_DEVINTCLR(udc->udp_baseaddr));
/* Write command code */
udc_protocol_cmd_w(udc, cmd);
while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
&& (to > 0))
to--;
if (!to)
dev_dbg(udc->dev,
"Protocol engine didn't receive response (CDFULL)\n");
return readl(USBD_CMDDATA(udc->udp_baseaddr));
}
/*
*
* USB device interrupt mask support functions
*
*/
/* Enable one or more USB device interrupts */
static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
{
udc->enabled_devints |= devmask;
writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
}
/* Disable one or more USB device interrupts */
static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
{
udc->enabled_devints &= ~mask;
writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
}
/* Clear one or more USB device interrupts */
static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
{
writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
}
/*
*
* Endpoint interrupt disable/enable functions
*
*/
/* Enable one or more USB endpoint interrupts */
static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
{
udc->enabled_hwepints |= (1 << hwep);
writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
}
/* Disable one or more USB endpoint interrupts */
static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
{
udc->enabled_hwepints &= ~(1 << hwep);
writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
}
/* Clear one or more USB endpoint interrupts */
static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
{
writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
}
/* Enable DMA for the HW channel */
static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
{
writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
}
/* Disable DMA for the HW channel */
static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
{
writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
}
/*
*
* Endpoint realize/unrealize functions
*
*/
/* Before an endpoint can be used, it needs to be realized
* in the USB protocol engine - this realizes the endpoint.
* The interrupt (FIFO or DMA) is not enabled with this function */
static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
u32 maxpacket)
{
int to = 1000;
writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
writel(hwep, USBD_EPIND(udc->udp_baseaddr));
udc->realized_eps |= (1 << hwep);
writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
/* Wait until endpoint is realized in hardware */
while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
USBD_EP_RLZED)) && (to > 0))
to--;
if (!to)
dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
}
/* Unrealize an EP */
static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
{
udc->realized_eps &= ~(1 << hwep);
writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
}
/*
*
* Endpoint support functions
*
*/
/* Select and clear endpoint interrupt */
static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
{
udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
}
/* Disables the endpoint in the USB protocol engine */
static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
{
udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
DAT_WR_BYTE(EP_STAT_DA));
}
/* Stalls the endpoint - endpoint will return STALL */
static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
{
udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
DAT_WR_BYTE(EP_STAT_ST));
}
/* Clear stall or reset endpoint */
static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
{
udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
DAT_WR_BYTE(0));
}
/* Select an endpoint for endpoint status, clear, validate */
static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
{
udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
}
/*
*
* Endpoint buffer management functions
*
*/
/* Clear the current endpoint's buffer */
static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
{
udc_select_hwep(udc, hwep);
udc_protocol_cmd_w(udc, CMD_CLR_BUF);
}
/* Validate the current endpoint's buffer */
static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
{
udc_select_hwep(udc, hwep);
udc_protocol_cmd_w(udc, CMD_VALID_BUF);
}
static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
{
/* Clear EP interrupt */
uda_clear_hwepint(udc, hwep);
return udc_selep_clrint(udc, hwep);
}
/*
*
* USB EP DMA support
*
*/
/* Allocate a DMA Descriptor */
static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
{
dma_addr_t dma;
struct lpc32xx_usbd_dd_gad *dd;
dd = dma_pool_alloc(udc->dd_cache, GFP_ATOMIC | GFP_DMA, &dma);
if (dd)
dd->this_dma = dma;
return dd;
}
/* Free a DMA Descriptor */
static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
{
dma_pool_free(udc->dd_cache, dd, dd->this_dma);
}
/*
*
* USB setup and shutdown functions
*
*/
/* Enables or disables most of the USB system clocks when low power mode is
* needed. Clocks are typically started on a connection event, and disabled
* when a cable is disconnected */
static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
{
if (enable != 0) {
if (udc->clocked)
return;
udc->clocked = 1;
clk_prepare_enable(udc->usb_slv_clk);
} else {
if (!udc->clocked)
return;
udc->clocked = 0;
clk_disable_unprepare(udc->usb_slv_clk);
}
}
/* Set/reset USB device address */
static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
{
/* Address will be latched at the end of the status phase, or
latched immediately if function is called twice */
udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
DAT_WR_BYTE(DEV_EN | addr));
}
/* Setup up a IN request for DMA transfer - this consists of determining the
* list of DMA addresses for the transfer, allocating DMA Descriptors,
* installing the DD into the UDCA, and then enabling the DMA for that EP */
static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
{
struct lpc32xx_request *req;
u32 hwep = ep->hwep_num;
ep->req_pending = 1;
/* There will always be a request waiting here */
req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
/* Place the DD Descriptor into the UDCA */
udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
/* Enable DMA and interrupt for the HW EP */
udc_ep_dma_enable(udc, hwep);
/* Clear ZLP if last packet is not of MAXP size */
if (req->req.length % ep->ep.maxpacket)
req->send_zlp = 0;
return 0;
}
/* Setup up a OUT request for DMA transfer - this consists of determining the
* list of DMA addresses for the transfer, allocating DMA Descriptors,
* installing the DD into the UDCA, and then enabling the DMA for that EP */