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cx2072x.c
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cx2072x.c
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// SPDX-License-Identifier: GPL-2.0
//
// ALSA SoC CX20721/CX20723 codec driver
//
// Copyright: (C) 2017 Conexant Systems, Inc.
// Author: Simon Ho, <Simon.ho@conexant.com>
//
// TODO: add support for TDM mode.
//
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <sound/jack.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/tlv.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include "cx2072x.h"
#define PLL_OUT_HZ_48 (1024 * 3 * 48000)
#define BITS_PER_SLOT 8
/* codec private data */
struct cx2072x_priv {
struct regmap *regmap;
struct clk *mclk;
unsigned int mclk_rate;
struct device *dev;
struct snd_soc_component *codec;
struct snd_soc_jack_gpio jack_gpio;
struct mutex lock;
unsigned int bclk_ratio;
bool pll_changed;
bool i2spcm_changed;
int sample_size;
int frame_size;
int sample_rate;
unsigned int dai_fmt;
bool en_aec_ref;
};
/*
* DAC/ADC Volume
*
* max : 74 : 0 dB
* ( in 1 dB step )
* min : 0 : -74 dB
*/
static const DECLARE_TLV_DB_SCALE(adc_tlv, -7400, 100, 0);
static const DECLARE_TLV_DB_SCALE(dac_tlv, -7400, 100, 0);
static const DECLARE_TLV_DB_SCALE(boost_tlv, 0, 1200, 0);
struct cx2072x_eq_ctrl {
u8 ch;
u8 band;
};
static const DECLARE_TLV_DB_RANGE(hpf_tlv,
0, 0, TLV_DB_SCALE_ITEM(120, 0, 0),
1, 63, TLV_DB_SCALE_ITEM(30, 30, 0)
);
/* Lookup table for PRE_DIV */
static const struct {
unsigned int mclk;
unsigned int div;
} mclk_pre_div[] = {
{ 6144000, 1 },
{ 12288000, 2 },
{ 19200000, 3 },
{ 26000000, 4 },
{ 28224000, 5 },
{ 36864000, 6 },
{ 36864000, 7 },
{ 48000000, 8 },
{ 49152000, 8 },
};
/*
* cx2072x register cache.
*/
static const struct reg_default cx2072x_reg_defaults[] = {
{ CX2072X_AFG_POWER_STATE, 0x00000003 },
{ CX2072X_UM_RESPONSE, 0x00000000 },
{ CX2072X_GPIO_DATA, 0x00000000 },
{ CX2072X_GPIO_ENABLE, 0x00000000 },
{ CX2072X_GPIO_DIRECTION, 0x00000000 },
{ CX2072X_GPIO_WAKE, 0x00000000 },
{ CX2072X_GPIO_UM_ENABLE, 0x00000000 },
{ CX2072X_GPIO_STICKY_MASK, 0x00000000 },
{ CX2072X_DAC1_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_DAC1_AMP_GAIN_RIGHT, 0x0000004a },
{ CX2072X_DAC1_AMP_GAIN_LEFT, 0x0000004a },
{ CX2072X_DAC1_POWER_STATE, 0x00000433 },
{ CX2072X_DAC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
{ CX2072X_DAC1_EAPD_ENABLE, 0x00000000 },
{ CX2072X_DAC2_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_DAC2_AMP_GAIN_RIGHT, 0x0000004a },
{ CX2072X_DAC2_AMP_GAIN_LEFT, 0x0000004a },
{ CX2072X_DAC2_POWER_STATE, 0x00000433 },
{ CX2072X_DAC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
{ CX2072X_ADC1_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_0, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_1, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_2, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_3, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_3, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_4, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_4, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_5, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_5, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_RIGHT_6, 0x0000004a },
{ CX2072X_ADC1_AMP_GAIN_LEFT_6, 0x0000004a },
{ CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 0x00000000 },
{ CX2072X_ADC1_POWER_STATE, 0x00000433 },
{ CX2072X_ADC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
{ CX2072X_ADC2_CONVERTER_FORMAT, 0x00000031 },
{ CX2072X_ADC2_AMP_GAIN_RIGHT_0, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_LEFT_0, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_RIGHT_1, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_LEFT_1, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_RIGHT_2, 0x0000004a },
{ CX2072X_ADC2_AMP_GAIN_LEFT_2, 0x0000004a },
{ CX2072X_ADC2_CONNECTION_SELECT_CONTROL, 0x00000000 },
{ CX2072X_ADC2_POWER_STATE, 0x00000433 },
{ CX2072X_ADC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
{ CX2072X_PORTA_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTA_POWER_STATE, 0x00000433 },
{ CX2072X_PORTA_PIN_CTRL, 0x000000c0 },
{ CX2072X_PORTA_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTA_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTA_EAPD_BTL, 0x00000002 },
{ CX2072X_PORTB_POWER_STATE, 0x00000433 },
{ CX2072X_PORTB_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTB_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTB_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTB_EAPD_BTL, 0x00000002 },
{ CX2072X_PORTB_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTB_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTC_POWER_STATE, 0x00000433 },
{ CX2072X_PORTC_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTC_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTC_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTD_POWER_STATE, 0x00000433 },
{ CX2072X_PORTD_PIN_CTRL, 0x00000020 },
{ CX2072X_PORTD_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTD_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTD_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTD_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTE_POWER_STATE, 0x00000433 },
{ CX2072X_PORTE_PIN_CTRL, 0x00000040 },
{ CX2072X_PORTE_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTE_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTE_EAPD_BTL, 0x00000002 },
{ CX2072X_PORTE_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTE_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTF_POWER_STATE, 0x00000433 },
{ CX2072X_PORTF_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTF_UNSOLICITED_RESPONSE, 0x00000000 },
{ CX2072X_PORTF_PIN_SENSE, 0x00000000 },
{ CX2072X_PORTF_GAIN_RIGHT, 0x00000000 },
{ CX2072X_PORTF_GAIN_LEFT, 0x00000000 },
{ CX2072X_PORTG_POWER_STATE, 0x00000433 },
{ CX2072X_PORTG_PIN_CTRL, 0x00000040 },
{ CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTG_EAPD_BTL, 0x00000002 },
{ CX2072X_PORTM_POWER_STATE, 0x00000433 },
{ CX2072X_PORTM_PIN_CTRL, 0x00000000 },
{ CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0x00000000 },
{ CX2072X_PORTM_EAPD_BTL, 0x00000002 },
{ CX2072X_MIXER_POWER_STATE, 0x00000433 },
{ CX2072X_MIXER_GAIN_RIGHT_0, 0x0000004a },
{ CX2072X_MIXER_GAIN_LEFT_0, 0x0000004a },
{ CX2072X_MIXER_GAIN_RIGHT_1, 0x0000004a },
{ CX2072X_MIXER_GAIN_LEFT_1, 0x0000004a },
{ CX2072X_SPKR_DRC_ENABLE_STEP, 0x040065a4 },
{ CX2072X_SPKR_DRC_CONTROL, 0x007b0024 },
{ CX2072X_SPKR_DRC_TEST, 0x00000000 },
{ CX2072X_DIGITAL_BIOS_TEST0, 0x001f008a },
{ CX2072X_DIGITAL_BIOS_TEST2, 0x00990026 },
{ CX2072X_I2SPCM_CONTROL1, 0x00010001 },
{ CX2072X_I2SPCM_CONTROL2, 0x00000000 },
{ CX2072X_I2SPCM_CONTROL3, 0x00000000 },
{ CX2072X_I2SPCM_CONTROL4, 0x00000000 },
{ CX2072X_I2SPCM_CONTROL5, 0x00000000 },
{ CX2072X_I2SPCM_CONTROL6, 0x00000000 },
{ CX2072X_UM_INTERRUPT_CRTL_E, 0x00000000 },
{ CX2072X_CODEC_TEST2, 0x00000000 },
{ CX2072X_CODEC_TEST9, 0x00000004 },
{ CX2072X_CODEC_TEST20, 0x00000600 },
{ CX2072X_CODEC_TEST26, 0x00000208 },
{ CX2072X_ANALOG_TEST4, 0x00000000 },
{ CX2072X_ANALOG_TEST5, 0x00000000 },
{ CX2072X_ANALOG_TEST6, 0x0000059a },
{ CX2072X_ANALOG_TEST7, 0x000000a7 },
{ CX2072X_ANALOG_TEST8, 0x00000017 },
{ CX2072X_ANALOG_TEST9, 0x00000000 },
{ CX2072X_ANALOG_TEST10, 0x00000285 },
{ CX2072X_ANALOG_TEST11, 0x00000000 },
{ CX2072X_ANALOG_TEST12, 0x00000000 },
{ CX2072X_ANALOG_TEST13, 0x00000000 },
{ CX2072X_DIGITAL_TEST1, 0x00000242 },
{ CX2072X_DIGITAL_TEST11, 0x00000000 },
{ CX2072X_DIGITAL_TEST12, 0x00000084 },
{ CX2072X_DIGITAL_TEST15, 0x00000077 },
{ CX2072X_DIGITAL_TEST16, 0x00000021 },
{ CX2072X_DIGITAL_TEST17, 0x00000018 },
{ CX2072X_DIGITAL_TEST18, 0x00000024 },
{ CX2072X_DIGITAL_TEST19, 0x00000001 },
{ CX2072X_DIGITAL_TEST20, 0x00000002 },
};
/*
* register initialization
*/
static const struct reg_sequence cx2072x_reg_init[] = {
{ CX2072X_ANALOG_TEST9, 0x080 }, /* DC offset Calibration */
{ CX2072X_CODEC_TEST26, 0x65f }, /* Disable the PA */
{ CX2072X_ANALOG_TEST10, 0x289 }, /* Set the speaker output gain */
{ CX2072X_CODEC_TEST20, 0xf05 },
{ CX2072X_CODEC_TESTXX, 0x380 },
{ CX2072X_CODEC_TEST26, 0xb90 },
{ CX2072X_CODEC_TEST9, 0x001 }, /* Enable 30 Hz High pass filter */
{ CX2072X_ANALOG_TEST3, 0x300 }, /* Disable PCBEEP pad */
{ CX2072X_CODEC_TEST24, 0x100 }, /* Disable SnM mode */
{ CX2072X_PORTD_PIN_CTRL, 0x020 }, /* Enable PortD input */
{ CX2072X_GPIO_ENABLE, 0x040 }, /* Enable GPIO7 pin for button */
{ CX2072X_GPIO_UM_ENABLE, 0x040 }, /* Enable UM for GPIO7 */
{ CX2072X_UM_RESPONSE, 0x080 }, /* Enable button response */
{ CX2072X_DIGITAL_TEST12, 0x0c4 }, /* Enable headset button */
{ CX2072X_DIGITAL_TEST0, 0x415 }, /* Power down class-D during idle */
{ CX2072X_I2SPCM_CONTROL2, 0x00f }, /* Enable I2S TX */
{ CX2072X_I2SPCM_CONTROL3, 0x00f }, /* Enable I2S RX */
};
static unsigned int cx2072x_register_size(unsigned int reg)
{
switch (reg) {
case CX2072X_VENDOR_ID:
case CX2072X_REVISION_ID:
case CX2072X_PORTA_PIN_SENSE:
case CX2072X_PORTB_PIN_SENSE:
case CX2072X_PORTD_PIN_SENSE:
case CX2072X_PORTE_PIN_SENSE:
case CX2072X_PORTF_PIN_SENSE:
case CX2072X_I2SPCM_CONTROL1:
case CX2072X_I2SPCM_CONTROL2:
case CX2072X_I2SPCM_CONTROL3:
case CX2072X_I2SPCM_CONTROL4:
case CX2072X_I2SPCM_CONTROL5:
case CX2072X_I2SPCM_CONTROL6:
case CX2072X_UM_INTERRUPT_CRTL_E:
case CX2072X_EQ_G_COEFF:
case CX2072X_SPKR_DRC_CONTROL:
case CX2072X_SPKR_DRC_TEST:
case CX2072X_DIGITAL_BIOS_TEST0:
case CX2072X_DIGITAL_BIOS_TEST2:
return 4;
case CX2072X_EQ_ENABLE_BYPASS:
case CX2072X_EQ_B0_COEFF:
case CX2072X_EQ_B1_COEFF:
case CX2072X_EQ_B2_COEFF:
case CX2072X_EQ_A1_COEFF:
case CX2072X_EQ_A2_COEFF:
case CX2072X_DAC1_CONVERTER_FORMAT:
case CX2072X_DAC2_CONVERTER_FORMAT:
case CX2072X_ADC1_CONVERTER_FORMAT:
case CX2072X_ADC2_CONVERTER_FORMAT:
case CX2072X_CODEC_TEST2:
case CX2072X_CODEC_TEST9:
case CX2072X_CODEC_TEST20:
case CX2072X_CODEC_TEST26:
case CX2072X_ANALOG_TEST3:
case CX2072X_ANALOG_TEST4:
case CX2072X_ANALOG_TEST5:
case CX2072X_ANALOG_TEST6:
case CX2072X_ANALOG_TEST7:
case CX2072X_ANALOG_TEST8:
case CX2072X_ANALOG_TEST9:
case CX2072X_ANALOG_TEST10:
case CX2072X_ANALOG_TEST11:
case CX2072X_ANALOG_TEST12:
case CX2072X_ANALOG_TEST13:
case CX2072X_DIGITAL_TEST0:
case CX2072X_DIGITAL_TEST1:
case CX2072X_DIGITAL_TEST11:
case CX2072X_DIGITAL_TEST12:
case CX2072X_DIGITAL_TEST15:
case CX2072X_DIGITAL_TEST16:
case CX2072X_DIGITAL_TEST17:
case CX2072X_DIGITAL_TEST18:
case CX2072X_DIGITAL_TEST19:
case CX2072X_DIGITAL_TEST20:
return 2;
default:
return 1;
}
}
static bool cx2072x_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CX2072X_VENDOR_ID:
case CX2072X_REVISION_ID:
case CX2072X_CURRENT_BCLK_FREQUENCY:
case CX2072X_AFG_POWER_STATE:
case CX2072X_UM_RESPONSE:
case CX2072X_GPIO_DATA:
case CX2072X_GPIO_ENABLE:
case CX2072X_GPIO_DIRECTION:
case CX2072X_GPIO_WAKE:
case CX2072X_GPIO_UM_ENABLE:
case CX2072X_GPIO_STICKY_MASK:
case CX2072X_DAC1_CONVERTER_FORMAT:
case CX2072X_DAC1_AMP_GAIN_RIGHT:
case CX2072X_DAC1_AMP_GAIN_LEFT:
case CX2072X_DAC1_POWER_STATE:
case CX2072X_DAC1_CONVERTER_STREAM_CHANNEL:
case CX2072X_DAC1_EAPD_ENABLE:
case CX2072X_DAC2_CONVERTER_FORMAT:
case CX2072X_DAC2_AMP_GAIN_RIGHT:
case CX2072X_DAC2_AMP_GAIN_LEFT:
case CX2072X_DAC2_POWER_STATE:
case CX2072X_DAC2_CONVERTER_STREAM_CHANNEL:
case CX2072X_ADC1_CONVERTER_FORMAT:
case CX2072X_ADC1_AMP_GAIN_RIGHT_0:
case CX2072X_ADC1_AMP_GAIN_LEFT_0:
case CX2072X_ADC1_AMP_GAIN_RIGHT_1:
case CX2072X_ADC1_AMP_GAIN_LEFT_1:
case CX2072X_ADC1_AMP_GAIN_RIGHT_2:
case CX2072X_ADC1_AMP_GAIN_LEFT_2:
case CX2072X_ADC1_AMP_GAIN_RIGHT_3:
case CX2072X_ADC1_AMP_GAIN_LEFT_3:
case CX2072X_ADC1_AMP_GAIN_RIGHT_4:
case CX2072X_ADC1_AMP_GAIN_LEFT_4:
case CX2072X_ADC1_AMP_GAIN_RIGHT_5:
case CX2072X_ADC1_AMP_GAIN_LEFT_5:
case CX2072X_ADC1_AMP_GAIN_RIGHT_6:
case CX2072X_ADC1_AMP_GAIN_LEFT_6:
case CX2072X_ADC1_CONNECTION_SELECT_CONTROL:
case CX2072X_ADC1_POWER_STATE:
case CX2072X_ADC1_CONVERTER_STREAM_CHANNEL:
case CX2072X_ADC2_CONVERTER_FORMAT:
case CX2072X_ADC2_AMP_GAIN_RIGHT_0:
case CX2072X_ADC2_AMP_GAIN_LEFT_0:
case CX2072X_ADC2_AMP_GAIN_RIGHT_1:
case CX2072X_ADC2_AMP_GAIN_LEFT_1:
case CX2072X_ADC2_AMP_GAIN_RIGHT_2:
case CX2072X_ADC2_AMP_GAIN_LEFT_2:
case CX2072X_ADC2_CONNECTION_SELECT_CONTROL:
case CX2072X_ADC2_POWER_STATE:
case CX2072X_ADC2_CONVERTER_STREAM_CHANNEL:
case CX2072X_PORTA_CONNECTION_SELECT_CTRL:
case CX2072X_PORTA_POWER_STATE:
case CX2072X_PORTA_PIN_CTRL:
case CX2072X_PORTA_UNSOLICITED_RESPONSE:
case CX2072X_PORTA_PIN_SENSE:
case CX2072X_PORTA_EAPD_BTL:
case CX2072X_PORTB_POWER_STATE:
case CX2072X_PORTB_PIN_CTRL:
case CX2072X_PORTB_UNSOLICITED_RESPONSE:
case CX2072X_PORTB_PIN_SENSE:
case CX2072X_PORTB_EAPD_BTL:
case CX2072X_PORTB_GAIN_RIGHT:
case CX2072X_PORTB_GAIN_LEFT:
case CX2072X_PORTC_POWER_STATE:
case CX2072X_PORTC_PIN_CTRL:
case CX2072X_PORTC_GAIN_RIGHT:
case CX2072X_PORTC_GAIN_LEFT:
case CX2072X_PORTD_POWER_STATE:
case CX2072X_PORTD_PIN_CTRL:
case CX2072X_PORTD_UNSOLICITED_RESPONSE:
case CX2072X_PORTD_PIN_SENSE:
case CX2072X_PORTD_GAIN_RIGHT:
case CX2072X_PORTD_GAIN_LEFT:
case CX2072X_PORTE_CONNECTION_SELECT_CTRL:
case CX2072X_PORTE_POWER_STATE:
case CX2072X_PORTE_PIN_CTRL:
case CX2072X_PORTE_UNSOLICITED_RESPONSE:
case CX2072X_PORTE_PIN_SENSE:
case CX2072X_PORTE_EAPD_BTL:
case CX2072X_PORTE_GAIN_RIGHT:
case CX2072X_PORTE_GAIN_LEFT:
case CX2072X_PORTF_POWER_STATE:
case CX2072X_PORTF_PIN_CTRL:
case CX2072X_PORTF_UNSOLICITED_RESPONSE:
case CX2072X_PORTF_PIN_SENSE:
case CX2072X_PORTF_GAIN_RIGHT:
case CX2072X_PORTF_GAIN_LEFT:
case CX2072X_PORTG_POWER_STATE:
case CX2072X_PORTG_PIN_CTRL:
case CX2072X_PORTG_CONNECTION_SELECT_CTRL:
case CX2072X_PORTG_EAPD_BTL:
case CX2072X_PORTM_POWER_STATE:
case CX2072X_PORTM_PIN_CTRL:
case CX2072X_PORTM_CONNECTION_SELECT_CTRL:
case CX2072X_PORTM_EAPD_BTL:
case CX2072X_MIXER_POWER_STATE:
case CX2072X_MIXER_GAIN_RIGHT_0:
case CX2072X_MIXER_GAIN_LEFT_0:
case CX2072X_MIXER_GAIN_RIGHT_1:
case CX2072X_MIXER_GAIN_LEFT_1:
case CX2072X_EQ_ENABLE_BYPASS:
case CX2072X_EQ_B0_COEFF:
case CX2072X_EQ_B1_COEFF:
case CX2072X_EQ_B2_COEFF:
case CX2072X_EQ_A1_COEFF:
case CX2072X_EQ_A2_COEFF:
case CX2072X_EQ_G_COEFF:
case CX2072X_SPKR_DRC_ENABLE_STEP:
case CX2072X_SPKR_DRC_CONTROL:
case CX2072X_SPKR_DRC_TEST:
case CX2072X_DIGITAL_BIOS_TEST0:
case CX2072X_DIGITAL_BIOS_TEST2:
case CX2072X_I2SPCM_CONTROL1:
case CX2072X_I2SPCM_CONTROL2:
case CX2072X_I2SPCM_CONTROL3:
case CX2072X_I2SPCM_CONTROL4:
case CX2072X_I2SPCM_CONTROL5:
case CX2072X_I2SPCM_CONTROL6:
case CX2072X_UM_INTERRUPT_CRTL_E:
case CX2072X_CODEC_TEST2:
case CX2072X_CODEC_TEST9:
case CX2072X_CODEC_TEST20:
case CX2072X_CODEC_TEST26:
case CX2072X_ANALOG_TEST4:
case CX2072X_ANALOG_TEST5:
case CX2072X_ANALOG_TEST6:
case CX2072X_ANALOG_TEST7:
case CX2072X_ANALOG_TEST8:
case CX2072X_ANALOG_TEST9:
case CX2072X_ANALOG_TEST10:
case CX2072X_ANALOG_TEST11:
case CX2072X_ANALOG_TEST12:
case CX2072X_ANALOG_TEST13:
case CX2072X_DIGITAL_TEST0:
case CX2072X_DIGITAL_TEST1:
case CX2072X_DIGITAL_TEST11:
case CX2072X_DIGITAL_TEST12:
case CX2072X_DIGITAL_TEST15:
case CX2072X_DIGITAL_TEST16:
case CX2072X_DIGITAL_TEST17:
case CX2072X_DIGITAL_TEST18:
case CX2072X_DIGITAL_TEST19:
case CX2072X_DIGITAL_TEST20:
return true;
default:
return false;
}
}
static bool cx2072x_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CX2072X_VENDOR_ID:
case CX2072X_REVISION_ID:
case CX2072X_UM_INTERRUPT_CRTL_E:
case CX2072X_DIGITAL_TEST11:
case CX2072X_PORTA_PIN_SENSE:
case CX2072X_PORTB_PIN_SENSE:
case CX2072X_PORTD_PIN_SENSE:
case CX2072X_PORTE_PIN_SENSE:
case CX2072X_PORTF_PIN_SENSE:
case CX2072X_EQ_G_COEFF:
case CX2072X_EQ_BAND:
return true;
default:
return false;
}
}
static int cx2072x_reg_raw_write(struct i2c_client *client,
unsigned int reg,
const void *val, size_t val_count)
{
struct device *dev = &client->dev;
u8 buf[2 + CX2072X_MAX_EQ_COEFF];
int ret;
if (WARN_ON(val_count + 2 > sizeof(buf)))
return -EINVAL;
buf[0] = reg >> 8;
buf[1] = reg & 0xff;
memcpy(buf + 2, val, val_count);
ret = i2c_master_send(client, buf, val_count + 2);
if (ret != val_count + 2) {
dev_err(dev, "I2C write failed, ret = %d\n", ret);
return ret < 0 ? ret : -EIO;
}
return 0;
}
static int cx2072x_reg_write(void *context, unsigned int reg,
unsigned int value)
{
__le32 raw_value;
unsigned int size;
size = cx2072x_register_size(reg);
if (reg == CX2072X_UM_INTERRUPT_CRTL_E) {
/* Update the MSB byte only */
reg += 3;
size = 1;
value >>= 24;
}
raw_value = cpu_to_le32(value);
return cx2072x_reg_raw_write(context, reg, &raw_value, size);
}
static int cx2072x_reg_read(void *context, unsigned int reg,
unsigned int *value)
{
struct i2c_client *client = context;
struct device *dev = &client->dev;
__le32 recv_buf = 0;
struct i2c_msg msgs[2];
unsigned int size;
u8 send_buf[2];
int ret;
size = cx2072x_register_size(reg);
send_buf[0] = reg >> 8;
send_buf[1] = reg & 0xff;
msgs[0].addr = client->addr;
msgs[0].len = sizeof(send_buf);
msgs[0].buf = send_buf;
msgs[0].flags = 0;
msgs[1].addr = client->addr;
msgs[1].len = size;
msgs[1].buf = (u8 *)&recv_buf;
msgs[1].flags = I2C_M_RD;
ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
if (ret != ARRAY_SIZE(msgs)) {
dev_err(dev, "Failed to read register, ret = %d\n", ret);
return ret < 0 ? ret : -EIO;
}
*value = le32_to_cpu(recv_buf);
return 0;
}
/* get suggested pre_div valuce from mclk frequency */
static unsigned int get_div_from_mclk(unsigned int mclk)
{
unsigned int div = 8;
int i;
for (i = 0; i < ARRAY_SIZE(mclk_pre_div); i++) {
if (mclk <= mclk_pre_div[i].mclk) {
div = mclk_pre_div[i].div;
break;
}
}
return div;
}
static int cx2072x_config_pll(struct cx2072x_priv *cx2072x)
{
struct device *dev = cx2072x->dev;
unsigned int pre_div;
unsigned int pre_div_val;
unsigned int pll_input;
unsigned int pll_output;
unsigned int int_div;
unsigned int frac_div;
u64 frac_num;
unsigned int frac;
unsigned int sample_rate = cx2072x->sample_rate;
int pt_sample_per_sync = 2;
int pt_clock_per_sample = 96;
switch (sample_rate) {
case 48000:
case 32000:
case 24000:
case 16000:
break;
case 96000:
pt_sample_per_sync = 1;
pt_clock_per_sample = 48;
break;
case 192000:
pt_sample_per_sync = 0;
pt_clock_per_sample = 24;
break;
default:
dev_err(dev, "Unsupported sample rate %d\n", sample_rate);
return -EINVAL;
}
/* Configure PLL settings */
pre_div = get_div_from_mclk(cx2072x->mclk_rate);
pll_input = cx2072x->mclk_rate / pre_div;
pll_output = sample_rate * 3072;
int_div = pll_output / pll_input;
frac_div = pll_output - (int_div * pll_input);
if (frac_div) {
frac_div *= 1000;
frac_div /= pll_input;
frac_num = (u64)(4000 + frac_div) * ((1 << 20) - 4);
do_div(frac_num, 7);
frac = ((u32)frac_num + 499) / 1000;
}
pre_div_val = (pre_div - 1) * 2;
regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST4,
0x40 | (pre_div_val << 8));
if (frac_div == 0) {
/* Int mode */
regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST7, 0x100);
} else {
/* frac mode */
regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST6,
frac & 0xfff);
regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST7,
(u8)(frac >> 12));
}
int_div--;
regmap_write(cx2072x->regmap, CX2072X_ANALOG_TEST8, int_div);
/* configure PLL tracking */
if (frac_div == 0) {
/* disable PLL tracking */
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST16, 0x00);
} else {
/* configure and enable PLL tracking */
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST16,
(pt_sample_per_sync << 4) & 0xf0);
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST17,
pt_clock_per_sample);
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST18,
pt_clock_per_sample * 3 / 2);
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST19, 0x01);
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_TEST20, 0x02);
regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_TEST16,
0x01, 0x01);
}
return 0;
}
static int cx2072x_config_i2spcm(struct cx2072x_priv *cx2072x)
{
struct device *dev = cx2072x->dev;
unsigned int bclk_rate = 0;
int is_i2s = 0;
int has_one_bit_delay = 0;
int is_frame_inv = 0;
int is_bclk_inv = 0;
int pulse_len;
int frame_len = cx2072x->frame_size;
int sample_size = cx2072x->sample_size;
int i2s_right_slot;
int i2s_right_pause_interval = 0;
int i2s_right_pause_pos;
int is_big_endian = 1;
u64 div;
unsigned int mod;
union cx2072x_reg_i2spcm_ctrl_reg1 reg1;
union cx2072x_reg_i2spcm_ctrl_reg2 reg2;
union cx2072x_reg_i2spcm_ctrl_reg3 reg3;
union cx2072x_reg_i2spcm_ctrl_reg4 reg4;
union cx2072x_reg_i2spcm_ctrl_reg5 reg5;
union cx2072x_reg_i2spcm_ctrl_reg6 reg6;
union cx2072x_reg_digital_bios_test2 regdbt2;
const unsigned int fmt = cx2072x->dai_fmt;
if (frame_len <= 0) {
dev_err(dev, "Incorrect frame len %d\n", frame_len);
return -EINVAL;
}
if (sample_size <= 0) {
dev_err(dev, "Incorrect sample size %d\n", sample_size);
return -EINVAL;
}
dev_dbg(dev, "config_i2spcm set_dai_fmt- %08x\n", fmt);
regdbt2.ulval = 0xac;
/* set master/slave */
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBM_CFM:
reg2.r.tx_master = 1;
reg3.r.rx_master = 1;
dev_dbg(dev, "Sets Master mode\n");
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg2.r.tx_master = 0;
reg3.r.rx_master = 0;
dev_dbg(dev, "Sets Slave mode\n");
break;
default:
dev_err(dev, "Unsupported DAI master mode\n");
return -EINVAL;
}
/* set format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
is_i2s = 1;
has_one_bit_delay = 1;
pulse_len = frame_len / 2;
break;
case SND_SOC_DAIFMT_RIGHT_J:
is_i2s = 1;
pulse_len = frame_len / 2;
break;
case SND_SOC_DAIFMT_LEFT_J:
is_i2s = 1;
pulse_len = frame_len / 2;
break;
default:
dev_err(dev, "Unsupported DAI format\n");
return -EINVAL;
}
/* clock inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
is_frame_inv = is_i2s;
is_bclk_inv = is_i2s;
break;
case SND_SOC_DAIFMT_IB_IF:
is_frame_inv = !is_i2s;
is_bclk_inv = !is_i2s;
break;
case SND_SOC_DAIFMT_IB_NF:
is_frame_inv = is_i2s;
is_bclk_inv = !is_i2s;
break;
case SND_SOC_DAIFMT_NB_IF:
is_frame_inv = !is_i2s;
is_bclk_inv = is_i2s;
break;
default:
dev_err(dev, "Unsupported DAI clock inversion\n");
return -EINVAL;
}
reg1.r.rx_data_one_line = 1;
reg1.r.tx_data_one_line = 1;
if (is_i2s) {
i2s_right_slot = (frame_len / 2) / BITS_PER_SLOT;
i2s_right_pause_interval = (frame_len / 2) % BITS_PER_SLOT;
i2s_right_pause_pos = i2s_right_slot * BITS_PER_SLOT;
}
reg1.r.rx_ws_pol = is_frame_inv;
reg1.r.rx_ws_wid = pulse_len - 1;
reg1.r.rx_frm_len = frame_len / BITS_PER_SLOT - 1;
reg1.r.rx_sa_size = (sample_size / BITS_PER_SLOT) - 1;
reg1.r.tx_ws_pol = reg1.r.rx_ws_pol;
reg1.r.tx_ws_wid = pulse_len - 1;
reg1.r.tx_frm_len = reg1.r.rx_frm_len;
reg1.r.tx_sa_size = reg1.r.rx_sa_size;
reg2.r.tx_endian_sel = !is_big_endian;
reg2.r.tx_dstart_dly = has_one_bit_delay;
if (cx2072x->en_aec_ref)
reg2.r.tx_dstart_dly = 0;
reg3.r.rx_endian_sel = !is_big_endian;
reg3.r.rx_dstart_dly = has_one_bit_delay;
reg4.ulval = 0;
if (is_i2s) {
reg2.r.tx_slot_1 = 0;
reg2.r.tx_slot_2 = i2s_right_slot;
reg3.r.rx_slot_1 = 0;
if (cx2072x->en_aec_ref)
reg3.r.rx_slot_2 = 0;
else
reg3.r.rx_slot_2 = i2s_right_slot;
reg6.r.rx_pause_start_pos = i2s_right_pause_pos;
reg6.r.rx_pause_cycles = i2s_right_pause_interval;
reg6.r.tx_pause_start_pos = i2s_right_pause_pos;
reg6.r.tx_pause_cycles = i2s_right_pause_interval;
} else {
dev_err(dev, "TDM mode is not implemented yet\n");
return -EINVAL;
}
regdbt2.r.i2s_bclk_invert = is_bclk_inv;
reg1.r.rx_data_one_line = 1;
reg1.r.tx_data_one_line = 1;
/* Configures the BCLK output */
bclk_rate = cx2072x->sample_rate * frame_len;
reg5.r.i2s_pcm_clk_div_chan_en = 0;
/* Disables bclk output before setting new value */
regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL5, 0);
if (reg2.r.tx_master) {
/* Configures BCLK rate */
div = PLL_OUT_HZ_48;
mod = do_div(div, bclk_rate);
if (mod) {
dev_err(dev, "Unsupported BCLK %dHz\n", bclk_rate);
return -EINVAL;
}
dev_dbg(dev, "enables BCLK %dHz output\n", bclk_rate);
reg5.r.i2s_pcm_clk_div = (u32)div - 1;
reg5.r.i2s_pcm_clk_div_chan_en = 1;
}
regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL1, reg1.ulval);
regmap_update_bits(cx2072x->regmap, CX2072X_I2SPCM_CONTROL2, 0xffffffc0,
reg2.ulval);
regmap_update_bits(cx2072x->regmap, CX2072X_I2SPCM_CONTROL3, 0xffffffc0,
reg3.ulval);
regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL4, reg4.ulval);
regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL6, reg6.ulval);
regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL5, reg5.ulval);
regmap_write(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST2,
regdbt2.ulval);
return 0;
}
static int afg_power_ev(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *codec = snd_soc_dapm_to_component(w->dapm);
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST0,
0x00, 0x10);
break;
case SND_SOC_DAPM_PRE_PMD:
regmap_update_bits(cx2072x->regmap, CX2072X_DIGITAL_BIOS_TEST0,
0x10, 0x10);
break;
}
return 0;
}
static const struct snd_kcontrol_new cx2072x_snd_controls[] = {
SOC_DOUBLE_R_TLV("PortD Boost Volume", CX2072X_PORTD_GAIN_LEFT,
CX2072X_PORTD_GAIN_RIGHT, 0, 3, 0, boost_tlv),
SOC_DOUBLE_R_TLV("PortC Boost Volume", CX2072X_PORTC_GAIN_LEFT,
CX2072X_PORTC_GAIN_RIGHT, 0, 3, 0, boost_tlv),
SOC_DOUBLE_R_TLV("PortB Boost Volume", CX2072X_PORTB_GAIN_LEFT,
CX2072X_PORTB_GAIN_RIGHT, 0, 3, 0, boost_tlv),
SOC_DOUBLE_R_TLV("PortD ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_1,
CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0, 0x4a, 0, adc_tlv),
SOC_DOUBLE_R_TLV("PortC ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_2,
CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0, 0x4a, 0, adc_tlv),
SOC_DOUBLE_R_TLV("PortB ADC1 Volume", CX2072X_ADC1_AMP_GAIN_LEFT_0,
CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0, 0x4a, 0, adc_tlv),
SOC_DOUBLE_R_TLV("DAC1 Volume", CX2072X_DAC1_AMP_GAIN_LEFT,
CX2072X_DAC1_AMP_GAIN_RIGHT, 0, 0x4a, 0, dac_tlv),
SOC_DOUBLE_R("DAC1 Switch", CX2072X_DAC1_AMP_GAIN_LEFT,
CX2072X_DAC1_AMP_GAIN_RIGHT, 7, 1, 0),
SOC_DOUBLE_R_TLV("DAC2 Volume", CX2072X_DAC2_AMP_GAIN_LEFT,
CX2072X_DAC2_AMP_GAIN_RIGHT, 0, 0x4a, 0, dac_tlv),
SOC_SINGLE_TLV("HPF Freq", CX2072X_CODEC_TEST9, 0, 0x3f, 0, hpf_tlv),
SOC_DOUBLE("HPF Switch", CX2072X_CODEC_TEST9, 8, 9, 1, 1),
SOC_SINGLE("PortA HP Amp Switch", CX2072X_PORTA_PIN_CTRL, 7, 1, 0),
};
static int cx2072x_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *codec = dai->component;
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
struct device *dev = codec->dev;
const unsigned int sample_rate = params_rate(params);
int sample_size, frame_size;
/* Data sizes if not using TDM */
sample_size = params_width(params);
if (sample_size < 0)
return sample_size;
frame_size = snd_soc_params_to_frame_size(params);
if (frame_size < 0)
return frame_size;
if (cx2072x->mclk_rate == 0) {
dev_err(dev, "Master clock rate is not configured\n");
return -EINVAL;
}
if (cx2072x->bclk_ratio)
frame_size = cx2072x->bclk_ratio;
switch (sample_rate) {
case 48000:
case 32000:
case 24000:
case 16000:
case 96000:
case 192000:
break;
default:
dev_err(dev, "Unsupported sample rate %d\n", sample_rate);
return -EINVAL;
}
dev_dbg(dev, "Sample size %d bits, frame = %d bits, rate = %d Hz\n",
sample_size, frame_size, sample_rate);
cx2072x->frame_size = frame_size;
cx2072x->sample_size = sample_size;
cx2072x->sample_rate = sample_rate;
if (dai->id == CX2072X_DAI_DSP) {
cx2072x->en_aec_ref = true;
dev_dbg(cx2072x->dev, "enables aec reference\n");
regmap_write(cx2072x->regmap,
CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 3);
}
if (cx2072x->pll_changed) {
cx2072x_config_pll(cx2072x);
cx2072x->pll_changed = false;
}
if (cx2072x->i2spcm_changed) {
cx2072x_config_i2spcm(cx2072x);
cx2072x->i2spcm_changed = false;
}
return 0;
}
static int cx2072x_set_dai_bclk_ratio(struct snd_soc_dai *dai,
unsigned int ratio)
{
struct snd_soc_component *codec = dai->component;
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
cx2072x->bclk_ratio = ratio;
return 0;
}
static int cx2072x_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
unsigned int freq, int dir)
{
struct snd_soc_component *codec = dai->component;
struct cx2072x_priv *cx2072x = snd_soc_component_get_drvdata(codec);
if (clk_set_rate(cx2072x->mclk, freq)) {
dev_err(codec->dev, "set clk rate failed\n");
return -EINVAL;