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rzg2ul-smarc-som.dtsi
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rzg2ul-smarc-som.dtsi
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/G2UL SMARC SOM common parts
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/ {
aliases {
ethernet0 = ð0;
ethernet1 = ð1;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
#if !(SW_SW0_DEV_SEL)
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
states = <3300000 1>, <1800000 0>;
regulator-boot-on;
gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>;
regulator-always-on;
};
#endif
};
#if (SW_SW0_DEV_SEL)
&adc {
pinctrl-0 = <&adc_pins>;
pinctrl-names = "default";
status = "okay";
};
#endif
#if (!SW_ET0_EN_N)
ð0 {
pinctrl-0 = <ð0_pins>;
pinctrl-names = "default";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
status = "okay";
phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
interrupt-parent = <&irqc>;
interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
#endif
ð1 {
pinctrl-0 = <ð1_pins>;
pinctrl-names = "default";
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
phy1: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
interrupt-parent = <&irqc>;
interrupts = <RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
txen-skew-psec = <0>;
rxd0-skew-psec = <0>;
rxd1-skew-psec = <0>;
rxd2-skew-psec = <0>;
rxd3-skew-psec = <0>;
txd0-skew-psec = <0>;
txd1-skew-psec = <0>;
txd2-skew-psec = <0>;
txd3-skew-psec = <0>;
};
};
&extal_clk {
clock-frequency = <24000000>;
};
&ostm1 {
status = "okay";
};
&ostm2 {
status = "okay";
};
&pinctrl {
adc_pins: adc {
pinmux = <RZG2L_PORT_PINMUX(6, 2, 1)>; /* ADC_TRG */
};
eth0_pins: eth0 {
pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
<RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
<RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
<RZG2L_PORT_PINMUX(1, 0, 1)>, /* ET0_TXC */
<RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
<RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
<RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
<RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
<RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
<RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
<RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
<RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
<RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
};
eth1_pins: eth1 {
pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */
<RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
<RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
<RZG2L_PORT_PINMUX(7, 0, 1)>, /* ET1_TXC */
<RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */
<RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
<RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
<RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
<RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
<RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
<RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
<RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
<RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
<RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
};
sdhi0_emmc_pins: sd0emmc {
sd0_emmc_data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
power-source = <1800>;
};
sd0_emmc_ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
sd0_emmc_rst {
pins = "SD0_RST#";
power-source = <1800>;
};
};
sdhi0_pins: sd0 {
sd0_data {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <3300>;
};
sd0_ctrl {
pins = "SD0_CLK", "SD0_CMD";
power-source = <3300>;
};
sd0_mux {
pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
};
};
sdhi0_pins_uhs: sd0_uhs {
sd0_data_uhs {
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
power-source = <1800>;
};
sd0_ctrl_uhs {
pins = "SD0_CLK", "SD0_CMD";
power-source = <1800>;
};
sd0_mux_uhs {
pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
};
};
};
#if (SW_SW0_DEV_SEL)
&sdhi0 {
pinctrl-0 = <&sdhi0_emmc_pins>;
pinctrl-1 = <&sdhi0_emmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <®_3p3v>;
vqmmc-supply = <®_1p8v>;
bus-width = <8>;
mmc-hs200-1_8v;
non-removable;
fixed-emmc-driver-type = <1>;
status = "okay";
};
#else
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <®_3p3v>;
vqmmc-supply = <&vccq_sdhi0>;
bus-width = <4>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
#endif
&wdt0 {
status = "okay";
timeout-sec = <60>;
};