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intel_cx0_phy.c
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intel_cx0_phy.c
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// SPDX-License-Identifier: MIT
/*
* Copyright © 2023 Intel Corporation
*/
#include <linux/log2.h>
#include <linux/math64.h>
#include "i915_reg.h"
#include "intel_cx0_phy.h"
#include "intel_cx0_phy_regs.h"
#include "intel_ddi.h"
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_hdmi.h"
#include "intel_panel.h"
#include "intel_psr.h"
#include "intel_tc.h"
#define MB_WRITE_COMMITTED true
#define MB_WRITE_UNCOMMITTED false
#define for_each_cx0_lane_in_mask(__lane_mask, __lane) \
for ((__lane) = 0; (__lane) < 2; (__lane)++) \
for_each_if((__lane_mask) & BIT(__lane))
#define INTEL_CX0_LANE0 BIT(0)
#define INTEL_CX0_LANE1 BIT(1)
#define INTEL_CX0_BOTH_LANES (INTEL_CX0_LANE1 | INTEL_CX0_LANE0)
bool intel_is_c10phy(struct drm_i915_private *i915, enum phy phy)
{
if (IS_METEORLAKE(i915) && (phy < PHY_C))
return true;
return false;
}
static int lane_mask_to_lane(u8 lane_mask)
{
if (WARN_ON((lane_mask & ~INTEL_CX0_BOTH_LANES) ||
hweight8(lane_mask) != 1))
return 0;
return ilog2(lane_mask);
}
static void
assert_dc_off(struct drm_i915_private *i915)
{
bool enabled;
enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF);
drm_WARN_ON(&i915->drm, !enabled);
}
/*
* Prepare HW for CX0 phy transactions.
*
* It is required that PSR and DC5/6 are disabled before any CX0 message
* bus transaction is executed.
*/
static intel_wakeref_t intel_cx0_phy_transaction_begin(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
intel_psr_pause(intel_dp);
return intel_display_power_get(i915, POWER_DOMAIN_DC_OFF);
}
static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_wakeref_t wakeref)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
intel_psr_resume(intel_dp);
intel_display_power_put(i915, POWER_DOMAIN_DC_OFF, wakeref);
}
static void intel_clear_response_ready_flag(struct drm_i915_private *i915,
enum port port, int lane)
{
intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
}
static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, int lane)
{
enum phy phy = intel_port_to_phy(i915, port);
intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET);
if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
return;
}
intel_clear_response_ready_flag(i915, port, lane);
}
static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port,
int command, int lane, u32 *val)
{
enum phy phy = intel_port_to_phy(i915, port);
if (__intel_de_wait_for_register(i915,
XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_MSGBUS_TIMEOUT_FAST_US,
XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
phy_name(phy), *val);
return -ETIMEDOUT;
}
if (*val & XELPDP_PORT_P2M_ERROR_SET) {
drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy),
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val);
intel_cx0_bus_reset(i915, port, lane);
return -EINVAL;
}
if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) {
drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy),
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val);
intel_cx0_bus_reset(i915, port, lane);
return -EINVAL;
}
return 0;
}
static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
int lane, u16 addr)
{
enum phy phy = intel_port_to_phy(i915, port);
int ack;
u32 val;
if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(&i915->drm,
"PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
intel_cx0_bus_reset(i915, port, lane);
return -ETIMEDOUT;
}
intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
XELPDP_PORT_M2P_COMMAND_READ |
XELPDP_PORT_M2P_ADDRESS(addr));
ack = intel_cx0_wait_for_ack(i915, port, XELPDP_PORT_P2M_COMMAND_READ_ACK, lane, &val);
if (ack < 0) {
intel_cx0_bus_reset(i915, port, lane);
return ack;
}
intel_clear_response_ready_flag(i915, port, lane);
return REG_FIELD_GET(XELPDP_PORT_P2M_DATA_MASK, val);
}
static u8 __intel_cx0_read(struct drm_i915_private *i915, enum port port,
int lane, u16 addr)
{
enum phy phy = intel_port_to_phy(i915, port);
int i, status;
assert_dc_off(i915);
/* 3 tries is assumed to be enough to read successfully */
for (i = 0; i < 3; i++) {
status = __intel_cx0_read_once(i915, port, lane, addr);
if (status >= 0)
return status;
}
drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n",
phy_name(phy), addr, i);
return 0;
}
static u8 intel_cx0_read(struct drm_i915_private *i915, enum port port,
u8 lane_mask, u16 addr)
{
int lane = lane_mask_to_lane(lane_mask);
return __intel_cx0_read(i915, port, lane, addr);
}
static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
int lane, u16 addr, u8 data, bool committed)
{
enum phy phy = intel_port_to_phy(i915, port);
u32 val;
if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(&i915->drm,
"PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy));
intel_cx0_bus_reset(i915, port, lane);
return -ETIMEDOUT;
}
intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
(committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
XELPDP_PORT_M2P_DATA(data) |
XELPDP_PORT_M2P_ADDRESS(addr));
if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(&i915->drm,
"PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy));
intel_cx0_bus_reset(i915, port, lane);
return -ETIMEDOUT;
}
if (committed) {
if (intel_cx0_wait_for_ack(i915, port, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val) < 0) {
intel_cx0_bus_reset(i915, port, lane);
return -EINVAL;
}
} else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) &
XELPDP_PORT_P2M_ERROR_SET)) {
drm_dbg_kms(&i915->drm,
"PHY %c Error occurred during write command.\n", phy_name(phy));
intel_cx0_bus_reset(i915, port, lane);
return -EINVAL;
}
intel_clear_response_ready_flag(i915, port, lane);
return 0;
}
static void __intel_cx0_write(struct drm_i915_private *i915, enum port port,
int lane, u16 addr, u8 data, bool committed)
{
enum phy phy = intel_port_to_phy(i915, port);
int i, status;
assert_dc_off(i915);
/* 3 tries is assumed to be enough to write successfully */
for (i = 0; i < 3; i++) {
status = __intel_cx0_write_once(i915, port, lane, addr, data, committed);
if (status == 0)
return;
}
drm_err_once(&i915->drm,
"PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
}
static void intel_cx0_write(struct drm_i915_private *i915, enum port port,
u8 lane_mask, u16 addr, u8 data, bool committed)
{
int lane;
for_each_cx0_lane_in_mask(lane_mask, lane)
__intel_cx0_write(i915, port, lane, addr, data, committed);
}
static void intel_c20_sram_write(struct drm_i915_private *i915, enum port port,
int lane, u16 addr, u16 data)
{
assert_dc_off(i915);
intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0);
intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0);
intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_H, data >> 8, 0);
intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1);
}
static u16 intel_c20_sram_read(struct drm_i915_private *i915, enum port port,
int lane, u16 addr)
{
u16 val;
assert_dc_off(i915);
intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0);
intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1);
val = intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_H);
val <<= 8;
val |= intel_cx0_read(i915, port, lane, PHY_C20_RD_DATA_L);
return val;
}
static void __intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
int lane, u16 addr, u8 clear, u8 set, bool committed)
{
u8 old, val;
old = __intel_cx0_read(i915, port, lane, addr);
val = (old & ~clear) | set;
if (val != old)
__intel_cx0_write(i915, port, lane, addr, val, committed);
}
static void intel_cx0_rmw(struct drm_i915_private *i915, enum port port,
u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed)
{
u8 lane;
for_each_cx0_lane_in_mask(lane_mask, lane)
__intel_cx0_rmw(i915, port, lane, addr, clear, set, committed);
}
static u8 intel_c10_get_tx_vboost_lvl(const struct intel_crtc_state *crtc_state)
{
if (intel_crtc_has_dp_encoder(crtc_state)) {
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
(crtc_state->port_clock == 540000 ||
crtc_state->port_clock == 810000))
return 5;
else
return 4;
} else {
return 5;
}
}
static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state)
{
if (intel_crtc_has_dp_encoder(crtc_state)) {
if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
(crtc_state->port_clock == 540000 ||
crtc_state->port_clock == 810000))
return 5;
else
return 2;
} else {
return 6;
}
}
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
const struct intel_ddi_buf_trans *trans;
enum phy phy = intel_port_to_phy(i915, encoder->port);
intel_wakeref_t wakeref;
int n_entries, ln;
wakeref = intel_cx0_phy_transaction_begin(encoder);
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
if (drm_WARN_ON_ONCE(&i915->drm, !trans)) {
intel_cx0_phy_transaction_end(encoder, wakeref);
return;
}
if (intel_is_c10phy(i915, phy)) {
intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED);
intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CMN(3),
C10_CMN3_TXVBOOST_MASK,
C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)),
MB_WRITE_UNCOMMITTED);
intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_TX(1),
C10_TX1_TERMCTL_MASK,
C10_TX1_TERMCTL(intel_c10_get_tx_term_ctl(crtc_state)),
MB_WRITE_COMMITTED);
}
for (ln = 0; ln < crtc_state->lane_count; ln++) {
int level = intel_ddi_level(encoder, crtc_state, ln);
int lane, tx;
lane = ln / 2;
tx = ln % 2;
intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 0),
C10_PHY_OVRD_LEVEL_MASK,
C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor),
MB_WRITE_COMMITTED);
intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 1),
C10_PHY_OVRD_LEVEL_MASK,
C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing),
MB_WRITE_COMMITTED);
intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 2),
C10_PHY_OVRD_LEVEL_MASK,
C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor),
MB_WRITE_COMMITTED);
}
/* Write Override enables in 0xD71 */
intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_OVRD,
0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2,
MB_WRITE_COMMITTED);
if (intel_is_c10phy(i915, phy))
intel_cx0_rmw(i915, encoder->port, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1),
0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED);
intel_cx0_phy_transaction_end(encoder, wakeref);
}
/*
* Basic DP link rates with 38.4 MHz reference clock.
* Note: The tables below are with SSC. In non-ssc
* registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
* programmed 0.
*/
static const struct intel_c10pll_state mtl_c10_dp_rbr = {
.clock = 162000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0xB4,
.pll[1] = 0,
.pll[2] = 0x30,
.pll[3] = 0x1,
.pll[4] = 0x26,
.pll[5] = 0x0C,
.pll[6] = 0x98,
.pll[7] = 0x46,
.pll[8] = 0x1,
.pll[9] = 0x1,
.pll[10] = 0,
.pll[11] = 0,
.pll[12] = 0xC0,
.pll[13] = 0,
.pll[14] = 0,
.pll[15] = 0x2,
.pll[16] = 0x84,
.pll[17] = 0x4F,
.pll[18] = 0xE5,
.pll[19] = 0x23,
};
static const struct intel_c10pll_state mtl_c10_edp_r216 = {
.clock = 216000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0x4,
.pll[1] = 0,
.pll[2] = 0xA2,
.pll[3] = 0x1,
.pll[4] = 0x33,
.pll[5] = 0x10,
.pll[6] = 0x75,
.pll[7] = 0xB3,
.pll[8] = 0x1,
.pll[9] = 0x1,
.pll[10] = 0,
.pll[11] = 0,
.pll[12] = 0,
.pll[13] = 0,
.pll[14] = 0,
.pll[15] = 0x2,
.pll[16] = 0x85,
.pll[17] = 0x0F,
.pll[18] = 0xE6,
.pll[19] = 0x23,
};
static const struct intel_c10pll_state mtl_c10_edp_r243 = {
.clock = 243000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0x34,
.pll[1] = 0,
.pll[2] = 0xDA,
.pll[3] = 0x1,
.pll[4] = 0x39,
.pll[5] = 0x12,
.pll[6] = 0xE3,
.pll[7] = 0xE9,
.pll[8] = 0x1,
.pll[9] = 0x1,
.pll[10] = 0,
.pll[11] = 0,
.pll[12] = 0x20,
.pll[13] = 0,
.pll[14] = 0,
.pll[15] = 0x2,
.pll[16] = 0x85,
.pll[17] = 0x8F,
.pll[18] = 0xE6,
.pll[19] = 0x23,
};
static const struct intel_c10pll_state mtl_c10_dp_hbr1 = {
.clock = 270000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0xF4,
.pll[1] = 0,
.pll[2] = 0xF8,
.pll[3] = 0x0,
.pll[4] = 0x20,
.pll[5] = 0x0A,
.pll[6] = 0x29,
.pll[7] = 0x10,
.pll[8] = 0x1, /* Verify */
.pll[9] = 0x1,
.pll[10] = 0,
.pll[11] = 0,
.pll[12] = 0xA0,
.pll[13] = 0,
.pll[14] = 0,
.pll[15] = 0x1,
.pll[16] = 0x84,
.pll[17] = 0x4F,
.pll[18] = 0xE5,
.pll[19] = 0x23,
};
static const struct intel_c10pll_state mtl_c10_edp_r324 = {
.clock = 324000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0xB4,
.pll[1] = 0,
.pll[2] = 0x30,
.pll[3] = 0x1,
.pll[4] = 0x26,
.pll[5] = 0x0C,
.pll[6] = 0x98,
.pll[7] = 0x46,
.pll[8] = 0x1,
.pll[9] = 0x1,
.pll[10] = 0,
.pll[11] = 0,
.pll[12] = 0xC0,
.pll[13] = 0,
.pll[14] = 0,
.pll[15] = 0x1,
.pll[16] = 0x85,
.pll[17] = 0x4F,
.pll[18] = 0xE6,
.pll[19] = 0x23,
};
static const struct intel_c10pll_state mtl_c10_edp_r432 = {
.clock = 432000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0x4,
.pll[1] = 0,
.pll[2] = 0xA2,
.pll[3] = 0x1,
.pll[4] = 0x33,
.pll[5] = 0x10,
.pll[6] = 0x75,
.pll[7] = 0xB3,
.pll[8] = 0x1,
.pll[9] = 0x1,
.pll[10] = 0,
.pll[11] = 0,
.pll[12] = 0,
.pll[13] = 0,
.pll[14] = 0,
.pll[15] = 0x1,
.pll[16] = 0x85,
.pll[17] = 0x0F,
.pll[18] = 0xE6,
.pll[19] = 0x23,
};
static const struct intel_c10pll_state mtl_c10_dp_hbr2 = {
.clock = 540000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0xF4,
.pll[1] = 0,
.pll[2] = 0xF8,
.pll[3] = 0,
.pll[4] = 0x20,
.pll[5] = 0x0A,
.pll[6] = 0x29,
.pll[7] = 0x10,
.pll[8] = 0x1,
.pll[9] = 0x1,
.pll[10] = 0,
.pll[11] = 0,
.pll[12] = 0xA0,
.pll[13] = 0,
.pll[14] = 0,
.pll[15] = 0,
.pll[16] = 0x84,
.pll[17] = 0x4F,
.pll[18] = 0xE5,
.pll[19] = 0x23,
};
static const struct intel_c10pll_state mtl_c10_edp_r675 = {
.clock = 675000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0xB4,
.pll[1] = 0,
.pll[2] = 0x3E,
.pll[3] = 0x1,
.pll[4] = 0xA8,
.pll[5] = 0x0C,
.pll[6] = 0x33,
.pll[7] = 0x54,
.pll[8] = 0x1,
.pll[9] = 0x1,
.pll[10] = 0,
.pll[11] = 0,
.pll[12] = 0xC8,
.pll[13] = 0,
.pll[14] = 0,
.pll[15] = 0,
.pll[16] = 0x85,
.pll[17] = 0x8F,
.pll[18] = 0xE6,
.pll[19] = 0x23,
};
static const struct intel_c10pll_state mtl_c10_dp_hbr3 = {
.clock = 810000,
.tx = 0x10,
.cmn = 0x21,
.pll[0] = 0x34,
.pll[1] = 0,
.pll[2] = 0x84,
.pll[3] = 0x1,
.pll[4] = 0x30,
.pll[5] = 0x0F,
.pll[6] = 0x3D,
.pll[7] = 0x98,
.pll[8] = 0x1,
.pll[9] = 0x1,
.pll[10] = 0,
.pll[11] = 0,
.pll[12] = 0xF0,
.pll[13] = 0,
.pll[14] = 0,
.pll[15] = 0,
.pll[16] = 0x84,
.pll[17] = 0x0F,
.pll[18] = 0xE5,
.pll[19] = 0x23,
};
static const struct intel_c10pll_state * const mtl_c10_dp_tables[] = {
&mtl_c10_dp_rbr,
&mtl_c10_dp_hbr1,
&mtl_c10_dp_hbr2,
&mtl_c10_dp_hbr3,
NULL,
};
static const struct intel_c10pll_state * const mtl_c10_edp_tables[] = {
&mtl_c10_dp_rbr,
&mtl_c10_edp_r216,
&mtl_c10_edp_r243,
&mtl_c10_dp_hbr1,
&mtl_c10_edp_r324,
&mtl_c10_edp_r432,
&mtl_c10_dp_hbr2,
&mtl_c10_edp_r675,
&mtl_c10_dp_hbr3,
NULL,
};
/* C20 basic DP 1.4 tables */
static const struct intel_c20pll_state mtl_c20_dp_rbr = {
.link_bit_rate = 162000,
.clock = 162000,
.tx = { 0xbe88, /* tx cfg0 */
0x5800, /* tx cfg1 */
0x0000, /* tx cfg2 */
},
.cmn = {0x0500, /* cmn cfg0*/
0x0005, /* cmn cfg1 */
0x0000, /* cmn cfg2 */
0x0000, /* cmn cfg3 */
},
.mpllb = { 0x50a8, /* mpllb cfg0 */
0x2120, /* mpllb cfg1 */
0xcd9a, /* mpllb cfg2 */
0xbfc1, /* mpllb cfg3 */
0x5ab8, /* mpllb cfg4 */
0x4c34, /* mpllb cfg5 */
0x2000, /* mpllb cfg6 */
0x0001, /* mpllb cfg7 */
0x6000, /* mpllb cfg8 */
0x0000, /* mpllb cfg9 */
0x0000, /* mpllb cfg10 */
},
};
static const struct intel_c20pll_state mtl_c20_dp_hbr1 = {
.link_bit_rate = 270000,
.clock = 270000,
.tx = { 0xbe88, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x0000, /* tx cfg2 */
},
.cmn = {0x0500, /* cmn cfg0*/
0x0005, /* cmn cfg1 */
0x0000, /* cmn cfg2 */
0x0000, /* cmn cfg3 */
},
.mpllb = { 0x308c, /* mpllb cfg0 */
0x2110, /* mpllb cfg1 */
0xcc9c, /* mpllb cfg2 */
0xbfc1, /* mpllb cfg3 */
0x4b9a, /* mpllb cfg4 */
0x3f81, /* mpllb cfg5 */
0x2000, /* mpllb cfg6 */
0x0001, /* mpllb cfg7 */
0x5000, /* mpllb cfg8 */
0x0000, /* mpllb cfg9 */
0x0000, /* mpllb cfg10 */
},
};
static const struct intel_c20pll_state mtl_c20_dp_hbr2 = {
.link_bit_rate = 540000,
.clock = 540000,
.tx = { 0xbe88, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x0000, /* tx cfg2 */
},
.cmn = {0x0500, /* cmn cfg0*/
0x0005, /* cmn cfg1 */
0x0000, /* cmn cfg2 */
0x0000, /* cmn cfg3 */
},
.mpllb = { 0x108c, /* mpllb cfg0 */
0x2108, /* mpllb cfg1 */
0xcc9c, /* mpllb cfg2 */
0xbfc1, /* mpllb cfg3 */
0x4b9a, /* mpllb cfg4 */
0x3f81, /* mpllb cfg5 */
0x2000, /* mpllb cfg6 */
0x0001, /* mpllb cfg7 */
0x5000, /* mpllb cfg8 */
0x0000, /* mpllb cfg9 */
0x0000, /* mpllb cfg10 */
},
};
static const struct intel_c20pll_state mtl_c20_dp_hbr3 = {
.link_bit_rate = 810000,
.clock = 810000,
.tx = { 0xbe88, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x0000, /* tx cfg2 */
},
.cmn = {0x0500, /* cmn cfg0*/
0x0005, /* cmn cfg1 */
0x0000, /* cmn cfg2 */
0x0000, /* cmn cfg3 */
},
.mpllb = { 0x10d2, /* mpllb cfg0 */
0x2108, /* mpllb cfg1 */
0x8d98, /* mpllb cfg2 */
0xbfc1, /* mpllb cfg3 */
0x7166, /* mpllb cfg4 */
0x5f42, /* mpllb cfg5 */
0x2000, /* mpllb cfg6 */
0x0001, /* mpllb cfg7 */
0x7800, /* mpllb cfg8 */
0x0000, /* mpllb cfg9 */
0x0000, /* mpllb cfg10 */
},
};
/* C20 basic DP 2.0 tables */
static const struct intel_c20pll_state mtl_c20_dp_uhbr10 = {
.link_bit_rate = 1000000, /* 10 Gbps */
.clock = 312500,
.tx = { 0xbe21, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x0000, /* tx cfg2 */
},
.cmn = {0x0500, /* cmn cfg0*/
0x0005, /* cmn cfg1 */
0x0000, /* cmn cfg2 */
0x0000, /* cmn cfg3 */
},
.mplla = { 0x3104, /* mplla cfg0 */
0xd105, /* mplla cfg1 */
0xc025, /* mplla cfg2 */
0xc025, /* mplla cfg3 */
0x8c00, /* mplla cfg4 */
0x759a, /* mplla cfg5 */
0x4000, /* mplla cfg6 */
0x0003, /* mplla cfg7 */
0x3555, /* mplla cfg8 */
0x0001, /* mplla cfg9 */
},
};
static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = {
.link_bit_rate = 1350000, /* 13.5 Gbps */
.clock = 421875,
.tx = { 0xbea0, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x0000, /* tx cfg2 */
},
.cmn = {0x0500, /* cmn cfg0*/
0x0005, /* cmn cfg1 */
0x0000, /* cmn cfg2 */
0x0000, /* cmn cfg3 */
},
.mpllb = { 0x015f, /* mpllb cfg0 */
0x2205, /* mpllb cfg1 */
0x1b17, /* mpllb cfg2 */
0xffc1, /* mpllb cfg3 */
0xe100, /* mpllb cfg4 */
0xbd00, /* mpllb cfg5 */
0x2000, /* mpllb cfg6 */
0x0001, /* mpllb cfg7 */
0x4800, /* mpllb cfg8 */
0x0000, /* mpllb cfg9 */
0x0000, /* mpllb cfg10 */
},
};
static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = {
.link_bit_rate = 2000000, /* 20 Gbps */
.clock = 625000,
.tx = { 0xbe20, /* tx cfg0 */
0x4800, /* tx cfg1 */
0x0000, /* tx cfg2 */
},
.cmn = {0x0500, /* cmn cfg0*/
0x0005, /* cmn cfg1 */
0x0000, /* cmn cfg2 */
0x0000, /* cmn cfg3 */
},
.mplla = { 0x3104, /* mplla cfg0 */
0xd105, /* mplla cfg1 */
0xc025, /* mplla cfg2 */
0xc025, /* mplla cfg3 */
0xa6ab, /* mplla cfg4 */
0x8c00, /* mplla cfg5 */
0x4000, /* mplla cfg6 */
0x0003, /* mplla cfg7 */
0x3555, /* mplla cfg8 */
0x0001, /* mplla cfg9 */
},
};
static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = {
&mtl_c20_dp_rbr,
&mtl_c20_dp_hbr1,
&mtl_c20_dp_hbr2,
&mtl_c20_dp_hbr3,
&mtl_c20_dp_uhbr10,
&mtl_c20_dp_uhbr13_5,
&mtl_c20_dp_uhbr20,
NULL,
};
/*
* HDMI link rates with 38.4 MHz reference clock.
*/
static const struct intel_c10pll_state mtl_c10_hdmi_25_2 = {
.clock = 25200,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x4,
.pll[1] = 0,
.pll[2] = 0xB2,
.pll[3] = 0,
.pll[4] = 0,
.pll[5] = 0,
.pll[6] = 0,
.pll[7] = 0,
.pll[8] = 0x20,
.pll[9] = 0x1,
.pll[10] = 0,
.pll[11] = 0,
.pll[12] = 0,
.pll[13] = 0,
.pll[14] = 0,
.pll[15] = 0xD,
.pll[16] = 0x6,
.pll[17] = 0x8F,
.pll[18] = 0x84,
.pll[19] = 0x23,
};
static const struct intel_c10pll_state mtl_c10_hdmi_27_0 = {
.clock = 27000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0x34,
.pll[1] = 0,
.pll[2] = 0xC0,
.pll[3] = 0,
.pll[4] = 0,
.pll[5] = 0,
.pll[6] = 0,
.pll[7] = 0,
.pll[8] = 0x20,
.pll[9] = 0x1,
.pll[10] = 0,
.pll[11] = 0,
.pll[12] = 0x80,
.pll[13] = 0,
.pll[14] = 0,
.pll[15] = 0xD,
.pll[16] = 0x6,
.pll[17] = 0xCF,
.pll[18] = 0x84,
.pll[19] = 0x23,
};
static const struct intel_c10pll_state mtl_c10_hdmi_74_25 = {
.clock = 74250,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4,
.pll[1] = 0,
.pll[2] = 0x7A,
.pll[3] = 0,
.pll[4] = 0,
.pll[5] = 0,
.pll[6] = 0,
.pll[7] = 0,
.pll[8] = 0x20,
.pll[9] = 0x1,
.pll[10] = 0,
.pll[11] = 0,
.pll[12] = 0x58,
.pll[13] = 0,
.pll[14] = 0,
.pll[15] = 0xB,
.pll[16] = 0x6,
.pll[17] = 0xF,
.pll[18] = 0x85,
.pll[19] = 0x23,
};
static const struct intel_c10pll_state mtl_c10_hdmi_148_5 = {
.clock = 148500,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4,
.pll[1] = 0,
.pll[2] = 0x7A,
.pll[3] = 0,
.pll[4] = 0,
.pll[5] = 0,
.pll[6] = 0,
.pll[7] = 0,
.pll[8] = 0x20,
.pll[9] = 0x1,
.pll[10] = 0,
.pll[11] = 0,
.pll[12] = 0x58,
.pll[13] = 0,
.pll[14] = 0,
.pll[15] = 0xA,
.pll[16] = 0x6,
.pll[17] = 0xF,
.pll[18] = 0x85,
.pll[19] = 0x23,
};
static const struct intel_c10pll_state mtl_c10_hdmi_594 = {
.clock = 594000,
.tx = 0x10,
.cmn = 0x1,
.pll[0] = 0xF4,
.pll[1] = 0,
.pll[2] = 0x7A,
.pll[3] = 0,
.pll[4] = 0,
.pll[5] = 0,
.pll[6] = 0,
.pll[7] = 0,
.pll[8] = 0x20,
.pll[9] = 0x1,
.pll[10] = 0,
.pll[11] = 0,
.pll[12] = 0x58,
.pll[13] = 0,