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dc_link.c
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dc_link.c
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include <linux/slab.h>
#include "dm_services.h"
#include "atomfirmware.h"
#include "dm_helpers.h"
#include "dc.h"
#include "grph_object_id.h"
#include "gpio_service_interface.h"
#include "core_status.h"
#include "dc_link_dp.h"
#include "dc_link_ddc.h"
#include "link_hwss.h"
#include "opp.h"
#include "link_encoder.h"
#include "hw_sequencer.h"
#include "resource.h"
#include "abm.h"
#include "fixed31_32.h"
#include "dpcd_defs.h"
#include "dmcu.h"
#include "hw/clk_mgr.h"
#include "dce/dmub_psr.h"
#include "dmub/dmub_srv.h"
#include "inc/hw/panel_cntl.h"
#define DC_LOGGER_INIT(logger)
#define LINK_INFO(...) \
DC_LOG_HW_HOTPLUG( \
__VA_ARGS__)
#define RETIMER_REDRIVER_INFO(...) \
DC_LOG_RETIMER_REDRIVER( \
__VA_ARGS__)
/*******************************************************************************
* Private structures
******************************************************************************/
enum {
PEAK_FACTOR_X1000 = 1006,
/*
* Some receivers fail to train on first try and are good
* on subsequent tries. 2 retries should be plenty. If we
* don't have a successful training then we don't expect to
* ever get one.
*/
LINK_TRAINING_MAX_VERIFY_RETRY = 2
};
/*******************************************************************************
* Private functions
******************************************************************************/
static void dc_link_destruct(struct dc_link *link)
{
int i;
if (link->hpd_gpio) {
dal_gpio_destroy_irq(&link->hpd_gpio);
link->hpd_gpio = NULL;
}
if (link->ddc)
dal_ddc_service_destroy(&link->ddc);
if (link->panel_cntl)
link->panel_cntl->funcs->destroy(&link->panel_cntl);
if (link->link_enc)
link->link_enc->funcs->destroy(&link->link_enc);
if (link->local_sink)
dc_sink_release(link->local_sink);
for (i = 0; i < link->sink_count; ++i)
dc_sink_release(link->remote_sinks[i]);
}
struct gpio *get_hpd_gpio(struct dc_bios *dcb,
struct graphics_object_id link_id,
struct gpio_service *gpio_service)
{
enum bp_result bp_result;
struct graphics_object_hpd_info hpd_info;
struct gpio_pin_info pin_info;
if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
return NULL;
bp_result = dcb->funcs->get_gpio_pin_info(dcb,
hpd_info.hpd_int_gpio_uid, &pin_info);
if (bp_result != BP_RESULT_OK) {
ASSERT(bp_result == BP_RESULT_NORECORD);
return NULL;
}
return dal_gpio_service_create_irq(gpio_service,
pin_info.offset,
pin_info.mask);
}
/*
* Function: program_hpd_filter
*
* @brief
* Programs HPD filter on associated HPD line
*
* @param [in] delay_on_connect_in_ms: Connect filter timeout
* @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
*
* @return
* true on success, false otherwise
*/
static bool program_hpd_filter(const struct dc_link *link)
{
bool result = false;
struct gpio *hpd;
int delay_on_connect_in_ms = 0;
int delay_on_disconnect_in_ms = 0;
if (link->is_hpd_filter_disabled)
return false;
/* Verify feature is supported */
switch (link->connector_signal) {
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
case SIGNAL_TYPE_HDMI_TYPE_A:
/* Program hpd filter */
delay_on_connect_in_ms = 500;
delay_on_disconnect_in_ms = 100;
break;
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
/* Program hpd filter to allow DP signal to settle */
/* 500: not able to detect MST <-> SST switch as HPD is low for
* only 100ms on DELL U2413
* 0: some passive dongle still show aux mode instead of i2c
* 20-50: not enough to hide bouncing HPD with passive dongle.
* also see intermittent i2c read issues.
*/
delay_on_connect_in_ms = 80;
delay_on_disconnect_in_ms = 0;
break;
case SIGNAL_TYPE_LVDS:
case SIGNAL_TYPE_EDP:
default:
/* Don't program hpd filter */
return false;
}
/* Obtain HPD handle */
hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
link->ctx->gpio_service);
if (!hpd)
return result;
/* Setup HPD filtering */
if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
struct gpio_hpd_config config;
config.delay_on_connect = delay_on_connect_in_ms;
config.delay_on_disconnect = delay_on_disconnect_in_ms;
dal_irq_setup_hpd_filter(hpd, &config);
dal_gpio_close(hpd);
result = true;
} else {
ASSERT_CRITICAL(false);
}
/* Release HPD handle */
dal_gpio_destroy_irq(&hpd);
return result;
}
/**
* dc_link_detect_sink() - Determine if there is a sink connected
*
* @type: Returned connection type
* Does not detect downstream devices, such as MST sinks
* or display connected through active dongles
*/
bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
{
uint32_t is_hpd_high = 0;
struct gpio *hpd_pin;
if (link->connector_signal == SIGNAL_TYPE_LVDS) {
*type = dc_connection_single;
return true;
}
if (link->connector_signal == SIGNAL_TYPE_EDP) {
/*in case it is not on*/
link->dc->hwss.edp_power_control(link, true);
link->dc->hwss.edp_wait_for_hpd_ready(link, true);
}
/* todo: may need to lock gpio access */
hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
link->ctx->gpio_service);
if (!hpd_pin)
goto hpd_gpio_failure;
dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
dal_gpio_get_value(hpd_pin, &is_hpd_high);
dal_gpio_close(hpd_pin);
dal_gpio_destroy_irq(&hpd_pin);
if (is_hpd_high) {
*type = dc_connection_single;
/* TODO: need to do the actual detection */
} else {
*type = dc_connection_none;
}
return true;
hpd_gpio_failure:
return false;
}
static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
{
enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
switch (sink_signal) {
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
case SIGNAL_TYPE_HDMI_TYPE_A:
case SIGNAL_TYPE_LVDS:
case SIGNAL_TYPE_RGB:
transaction_type = DDC_TRANSACTION_TYPE_I2C;
break;
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_EDP:
transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
break;
case SIGNAL_TYPE_DISPLAY_PORT_MST:
/* MST does not use I2COverAux, but there is the
* SPECIAL use case for "immediate dwnstrm device
* access" (EPR#370830).
*/
transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
break;
default:
break;
}
return transaction_type;
}
static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
struct graphics_object_id downstream)
{
if (downstream.type == OBJECT_TYPE_CONNECTOR) {
switch (downstream.id) {
case CONNECTOR_ID_SINGLE_LINK_DVII:
switch (encoder.id) {
case ENCODER_ID_INTERNAL_DAC1:
case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
case ENCODER_ID_INTERNAL_DAC2:
case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
return SIGNAL_TYPE_RGB;
default:
return SIGNAL_TYPE_DVI_SINGLE_LINK;
}
break;
case CONNECTOR_ID_DUAL_LINK_DVII:
{
switch (encoder.id) {
case ENCODER_ID_INTERNAL_DAC1:
case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
case ENCODER_ID_INTERNAL_DAC2:
case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
return SIGNAL_TYPE_RGB;
default:
return SIGNAL_TYPE_DVI_DUAL_LINK;
}
}
break;
case CONNECTOR_ID_SINGLE_LINK_DVID:
return SIGNAL_TYPE_DVI_SINGLE_LINK;
case CONNECTOR_ID_DUAL_LINK_DVID:
return SIGNAL_TYPE_DVI_DUAL_LINK;
case CONNECTOR_ID_VGA:
return SIGNAL_TYPE_RGB;
case CONNECTOR_ID_HDMI_TYPE_A:
return SIGNAL_TYPE_HDMI_TYPE_A;
case CONNECTOR_ID_LVDS:
return SIGNAL_TYPE_LVDS;
case CONNECTOR_ID_DISPLAY_PORT:
return SIGNAL_TYPE_DISPLAY_PORT;
case CONNECTOR_ID_EDP:
return SIGNAL_TYPE_EDP;
default:
return SIGNAL_TYPE_NONE;
}
} else if (downstream.type == OBJECT_TYPE_ENCODER) {
switch (downstream.id) {
case ENCODER_ID_EXTERNAL_NUTMEG:
case ENCODER_ID_EXTERNAL_TRAVIS:
return SIGNAL_TYPE_DISPLAY_PORT;
default:
return SIGNAL_TYPE_NONE;
}
}
return SIGNAL_TYPE_NONE;
}
/**
* dc_link_is_dp_sink_present() - Check if there is a native DP
* or passive DP-HDMI dongle connected
*/
bool dc_link_is_dp_sink_present(struct dc_link *link)
{
enum gpio_result gpio_result;
uint32_t clock_pin = 0;
uint8_t retry = 0;
struct ddc *ddc;
enum connector_id connector_id =
dal_graphics_object_id_get_connector_id(link->link_id);
bool present =
((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
(connector_id == CONNECTOR_ID_EDP));
ddc = dal_ddc_service_get_ddc_pin(link->ddc);
if (!ddc) {
BREAK_TO_DEBUGGER();
return present;
}
/* Open GPIO and set it to I2C mode */
/* Note: this GpioMode_Input will be converted
* to GpioConfigType_I2cAuxDualMode in GPIO component,
* which indicates we need additional delay
*/
if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
dal_ddc_close(ddc);
return present;
}
/*
* Read GPIO: DP sink is present if both clock and data pins are zero
*
* [W/A] plug-unplug DP cable, sometimes customer board has
* one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
* then monitor can't br light up. Add retry 3 times
* But in real passive dongle, it need additional 3ms to detect
*/
do {
gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
ASSERT(gpio_result == GPIO_RESULT_OK);
if (clock_pin)
udelay(1000);
else
break;
} while (retry++ < 3);
present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
dal_ddc_close(ddc);
return present;
}
/*
* @brief
* Detect output sink type
*/
static enum signal_type link_detect_sink(struct dc_link *link,
enum dc_detect_reason reason)
{
enum signal_type result = get_basic_signal_type(link->link_enc->id,
link->link_id);
/* Internal digital encoder will detect only dongles
* that require digital signal
*/
/* Detection mechanism is different
* for different native connectors.
* LVDS connector supports only LVDS signal;
* PCIE is a bus slot, the actual connector needs to be detected first;
* eDP connector supports only eDP signal;
* HDMI should check straps for audio
*/
/* PCIE detects the actual connector on add-on board */
if (link->link_id.id == CONNECTOR_ID_PCIE) {
/* ZAZTODO implement PCIE add-on card detection */
}
switch (link->link_id.id) {
case CONNECTOR_ID_HDMI_TYPE_A: {
/* check audio support:
* if native HDMI is not supported, switch to DVI
*/
struct audio_support *aud_support =
&link->dc->res_pool->audio_support;
if (!aud_support->hdmi_audio_native)
if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
result = SIGNAL_TYPE_DVI_SINGLE_LINK;
}
break;
case CONNECTOR_ID_DISPLAY_PORT: {
/* DP HPD short pulse. Passive DP dongle will not
* have short pulse
*/
if (reason != DETECT_REASON_HPDRX) {
/* Check whether DP signal detected: if not -
* we assume signal is DVI; it could be corrected
* to HDMI after dongle detection
*/
if (!dm_helpers_is_dp_sink_present(link))
result = SIGNAL_TYPE_DVI_SINGLE_LINK;
}
}
break;
default:
break;
}
return result;
}
static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
struct audio_support *audio_support)
{
enum signal_type signal = SIGNAL_TYPE_NONE;
switch (dongle_type) {
case DISPLAY_DONGLE_DP_HDMI_DONGLE:
if (audio_support->hdmi_audio_on_dongle)
signal = SIGNAL_TYPE_HDMI_TYPE_A;
else
signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
break;
case DISPLAY_DONGLE_DP_DVI_DONGLE:
signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
break;
case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
if (audio_support->hdmi_audio_native)
signal = SIGNAL_TYPE_HDMI_TYPE_A;
else
signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
break;
default:
signal = SIGNAL_TYPE_NONE;
break;
}
return signal;
}
static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
struct display_sink_capability *sink_cap,
struct audio_support *audio_support)
{
dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
audio_support);
}
static void link_disconnect_sink(struct dc_link *link)
{
if (link->local_sink) {
dc_sink_release(link->local_sink);
link->local_sink = NULL;
}
link->dpcd_sink_count = 0;
}
static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
{
dc_sink_release(link->local_sink);
link->local_sink = prev_sink;
}
#if defined(CONFIG_DRM_AMD_DC_HDCP)
bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
{
bool ret = false;
switch (signal) {
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
break;
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
case SIGNAL_TYPE_HDMI_TYPE_A:
/* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
* we can poll for bksv but some displays have an issue with this. Since its so rare
* for a display to not be 1.4 capable, this assumtion is ok
*/
ret = true;
break;
default:
break;
}
return ret;
}
bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
{
bool ret = false;
switch (signal) {
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
(link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
break;
case SIGNAL_TYPE_DVI_SINGLE_LINK:
case SIGNAL_TYPE_DVI_DUAL_LINK:
case SIGNAL_TYPE_HDMI_TYPE_A:
ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
break;
default:
break;
}
return ret;
}
static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
{
struct hdcp_protection_message msg22;
struct hdcp_protection_message msg14;
memset(&msg22, 0, sizeof(struct hdcp_protection_message));
memset(&msg14, 0, sizeof(struct hdcp_protection_message));
memset(link->hdcp_caps.rx_caps.raw, 0,
sizeof(link->hdcp_caps.rx_caps.raw));
if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
link->ddc->transaction_type ==
DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
link->connector_signal == SIGNAL_TYPE_EDP) {
msg22.data = link->hdcp_caps.rx_caps.raw;
msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
} else {
msg22.data = &link->hdcp_caps.rx_caps.fields.version;
msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
}
msg22.version = HDCP_VERSION_22;
msg22.link = HDCP_LINK_PRIMARY;
msg22.max_retries = 5;
dc_process_hdcp_msg(signal, link, &msg22);
if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
enum hdcp_message_status status = HDCP_MESSAGE_UNSUPPORTED;
msg14.data = &link->hdcp_caps.bcaps.raw;
msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
msg14.version = HDCP_VERSION_14;
msg14.link = HDCP_LINK_PRIMARY;
msg14.max_retries = 5;
status = dc_process_hdcp_msg(signal, link, &msg14);
}
}
#endif
static void read_current_link_settings_on_detect(struct dc_link *link)
{
union lane_count_set lane_count_set = { {0} };
uint8_t link_bw_set;
uint8_t link_rate_set;
uint32_t read_dpcd_retry_cnt = 10;
enum dc_status status = DC_ERROR_UNEXPECTED;
int i;
union max_down_spread max_down_spread = { {0} };
// Read DPCD 00101h to find out the number of lanes currently set
for (i = 0; i < read_dpcd_retry_cnt; i++) {
status = core_link_read_dpcd(link,
DP_LANE_COUNT_SET,
&lane_count_set.raw,
sizeof(lane_count_set));
/* First DPCD read after VDD ON can fail if the particular board
* does not have HPD pin wired correctly. So if DPCD read fails,
* which it should never happen, retry a few times. Target worst
* case scenario of 80 ms.
*/
if (status == DC_OK) {
link->cur_link_settings.lane_count =
lane_count_set.bits.LANE_COUNT_SET;
break;
}
msleep(8);
}
// Read DPCD 00100h to find if standard link rates are set
core_link_read_dpcd(link, DP_LINK_BW_SET,
&link_bw_set, sizeof(link_bw_set));
if (link_bw_set == 0) {
if (link->connector_signal == SIGNAL_TYPE_EDP) {
/* If standard link rates are not being used,
* Read DPCD 00115h to find the edp link rate set used
*/
core_link_read_dpcd(link, DP_LINK_RATE_SET,
&link_rate_set, sizeof(link_rate_set));
// edp_supported_link_rates_count = 0 for DP
if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
link->cur_link_settings.link_rate =
link->dpcd_caps.edp_supported_link_rates[link_rate_set];
link->cur_link_settings.link_rate_set = link_rate_set;
link->cur_link_settings.use_link_rate_set = true;
}
} else {
// Link Rate not found. Seamless boot may not work.
ASSERT(false);
}
} else {
link->cur_link_settings.link_rate = link_bw_set;
link->cur_link_settings.use_link_rate_set = false;
}
// Read DPCD 00003h to find the max down spread.
core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
&max_down_spread.raw, sizeof(max_down_spread));
link->cur_link_settings.link_spread =
max_down_spread.bits.MAX_DOWN_SPREAD ?
LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
}
static bool detect_dp(struct dc_link *link,
struct display_sink_capability *sink_caps,
bool *converter_disable_audio,
struct audio_support *audio_support,
enum dc_detect_reason reason)
{
bool boot = false;
sink_caps->signal = link_detect_sink(link, reason);
sink_caps->transaction_type =
get_ddc_transaction_type(sink_caps->signal);
if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
if (!detect_dp_sink_caps(link))
return false;
if (is_mst_supported(link)) {
sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
link->type = dc_connection_mst_branch;
dal_ddc_service_set_transaction_type(link->ddc,
sink_caps->transaction_type);
#if defined(CONFIG_DRM_AMD_DC_HDCP)
/* In case of fallback to SST when topology discovery below fails
* HDCP caps will be querried again later by the upper layer (caller
* of this function). */
query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
#endif
/*
* This call will initiate MST topology discovery. Which
* will detect MST ports and add new DRM connector DRM
* framework. Then read EDID via remote i2c over aux. In
* the end, will notify DRM detect result and save EDID
* into DRM framework.
*
* .detect is called by .fill_modes.
* .fill_modes is called by user mode ioctl
* DRM_IOCTL_MODE_GETCONNECTOR.
*
* .get_modes is called by .fill_modes.
*
* call .get_modes, AMDGPU DM implementation will create
* new dc_sink and add to dc_link. For long HPD plug
* in/out, MST has its own handle.
*
* Therefore, just after dc_create, link->sink is not
* created for MST until user mode app calls
* DRM_IOCTL_MODE_GETCONNECTOR.
*
* Need check ->sink usages in case ->sink = NULL
* TODO: s3 resume check
*/
if (reason == DETECT_REASON_BOOT)
boot = true;
dm_helpers_dp_update_branch_info(link->ctx, link);
if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
link, boot)) {
/* MST not supported */
link->type = dc_connection_single;
sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
}
}
if (link->type != dc_connection_mst_branch &&
is_dp_active_dongle(link)) {
/* DP active dongles */
link->type = dc_connection_active_dongle;
if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) {
/*
* active dongle unplug processing for short irq
*/
link_disconnect_sink(link);
return true;
}
if (link->dpcd_caps.dongle_type !=
DISPLAY_DONGLE_DP_HDMI_CONVERTER)
*converter_disable_audio = true;
}
} else {
/* DP passive dongles */
sink_caps->signal = dp_passive_dongle_detection(link->ddc,
sink_caps,
audio_support);
link->dpcd_caps.dongle_type = sink_caps->dongle_type;
}
return true;
}
static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
{
if (old_edid->length != new_edid->length)
return false;
if (new_edid->length == 0)
return false;
return (memcmp(old_edid->raw_edid,
new_edid->raw_edid, new_edid->length) == 0);
}
static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
{
/**
* something is terribly wrong if time out is > 200ms. (5Hz)
* 500 microseconds * 400 tries us 200 ms
**/
unsigned int sleep_time_in_microseconds = 500;
unsigned int tries_allowed = 400;
bool is_in_alt_mode;
unsigned long long enter_timestamp;
unsigned long long finish_timestamp;
unsigned long long time_taken_in_ns;
int tries_taken;
DC_LOGGER_INIT(link->ctx->logger);
if (!link->link_enc->funcs->is_in_alt_mode)
return true;
is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
if (is_in_alt_mode)
return true;
enter_timestamp = dm_get_timestamp(link->ctx);
for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
udelay(sleep_time_in_microseconds);
/* ask the link if alt mode is enabled, if so return ok */
if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
finish_timestamp = dm_get_timestamp(link->ctx);
time_taken_in_ns =
dm_get_elapse_time_in_ns(link->ctx,
finish_timestamp,
enter_timestamp);
DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
div_u64(time_taken_in_ns, 1000000));
return true;
}
}
finish_timestamp = dm_get_timestamp(link->ctx);
time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
enter_timestamp);
DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
div_u64(time_taken_in_ns, 1000000));
return false;
}
/**
* dc_link_detect() - Detect if a sink is attached to a given link
*
* link->local_sink is created or destroyed as needed.
*
* This does not create remote sinks but will trigger DM
* to start MST detection if a branch is detected.
*/
static bool dc_link_detect_helper(struct dc_link *link,
enum dc_detect_reason reason)
{
struct dc_sink_init_data sink_init_data = { 0 };
struct display_sink_capability sink_caps = { 0 };
uint8_t i;
bool converter_disable_audio = false;
struct audio_support *aud_support = &link->dc->res_pool->audio_support;
bool same_edid = false;
enum dc_edid_status edid_status;
struct dc_context *dc_ctx = link->ctx;
struct dc_sink *sink = NULL;
struct dc_sink *prev_sink = NULL;
struct dpcd_caps prev_dpcd_caps;
bool same_dpcd = true;
enum dc_connection_type new_connection_type = dc_connection_none;
bool perform_dp_seamless_boot = false;
const uint32_t post_oui_delay = 30; // 30ms
DC_LOGGER_INIT(link->ctx->logger);
if (dc_is_virtual_signal(link->connector_signal))
return false;
if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
link->connector_signal == SIGNAL_TYPE_EDP) &&
link->local_sink) {
// need to re-write OUI and brightness in resume case
if (link->connector_signal == SIGNAL_TYPE_EDP) {
dpcd_set_source_specific_data(link);
msleep(post_oui_delay);
dc_link_set_default_brightness_aux(link);
//TODO: use cached
}
return true;
}
if (!dc_link_detect_sink(link, &new_connection_type)) {
BREAK_TO_DEBUGGER();
return false;
}
prev_sink = link->local_sink;
if (prev_sink) {
dc_sink_retain(prev_sink);
memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
}
link_disconnect_sink(link);
if (new_connection_type != dc_connection_none) {
link->type = new_connection_type;
link->link_state_valid = false;
/* From Disconnected-to-Connected. */
switch (link->connector_signal) {
case SIGNAL_TYPE_HDMI_TYPE_A: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
if (aud_support->hdmi_audio_native)
sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
else
sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
break;
}
case SIGNAL_TYPE_DVI_SINGLE_LINK: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
break;
}
case SIGNAL_TYPE_DVI_DUAL_LINK: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
break;
}
case SIGNAL_TYPE_LVDS: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_LVDS;
break;
}
case SIGNAL_TYPE_EDP: {
read_current_link_settings_on_detect(link);
detect_edp_sink_caps(link);
read_current_link_settings_on_detect(link);
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
sink_caps.signal = SIGNAL_TYPE_EDP;
break;
}
case SIGNAL_TYPE_DISPLAY_PORT: {
/* wa HPD high coming too early*/
if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
/* if alt mode times out, return false */
if (!wait_for_entering_dp_alt_mode(link))
return false;
}
if (!detect_dp(link, &sink_caps,
&converter_disable_audio,
aud_support, reason)) {
if (prev_sink)
dc_sink_release(prev_sink);
return false;
}
// Check if dpcp block is the same
if (prev_sink) {
if (memcmp(&link->dpcd_caps, &prev_dpcd_caps,
sizeof(struct dpcd_caps)))
same_dpcd = false;
}
/* Active dongle downstream unplug*/
if (link->type == dc_connection_active_dongle &&
link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
if (prev_sink)
/* Downstream unplug */
dc_sink_release(prev_sink);
return true;
}
if (link->type == dc_connection_mst_branch) {
LINK_INFO("link=%d, mst branch is now Connected\n",
link->link_index);
/* Need to setup mst link_cap struct here
* otherwise dc_link_detect() will leave mst link_cap
* empty which leads to allocate_mst_payload() has "0"
* pbn_per_slot value leading to exception on dc_fixpt_div()
*/
dp_verify_mst_link_cap(link);
if (prev_sink)
dc_sink_release(prev_sink);
return false;
}
// For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
if (reason == DETECT_REASON_BOOT &&
!dc_ctx->dc->config.power_down_display_on_boot &&
link->link_status.link_active)
perform_dp_seamless_boot = true;
if (perform_dp_seamless_boot) {
read_current_link_settings_on_detect(link);
link->verified_link_cap = link->reported_link_cap;
}
break;
}
default:
DC_ERROR("Invalid connector type! signal:%d\n",
link->connector_signal);
if (prev_sink)
dc_sink_release(prev_sink);
return false;
} /* switch() */