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hda.c
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hda.c
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
//
// This file is provided under a dual BSD/GPLv2 license. When using or
// redistributing this file, you may do so under either license.
//
// Copyright(c) 2018 Intel Corporation. All rights reserved.
//
// Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
// Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
// Rander Wang <rander.wang@intel.com>
// Keyon Jie <yang.jie@linux.intel.com>
//
/*
* Hardware interface for generic Intel audio DSP HDA IP
*/
#include <sound/hdaudio_ext.h>
#include <sound/hda_register.h>
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_intel.h>
#include <sound/intel-dsp-config.h>
#include <sound/intel-nhlt.h>
#include <sound/sof.h>
#include <sound/sof/xtensa.h>
#include <sound/hda-mlink.h>
#include "../sof-audio.h"
#include "../sof-pci-dev.h"
#include "../ops.h"
#include "hda.h"
#define CREATE_TRACE_POINTS
#include <trace/events/sof_intel.h>
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
#include <sound/soc-acpi-intel-match.h>
#endif
/* platform specific devices */
#include "shim.h"
#define EXCEPT_MAX_HDR_SIZE 0x400
#define HDA_EXT_ROM_STATUS_SIZE 8
static u32 hda_get_interface_mask(struct snd_sof_dev *sdev)
{
const struct sof_intel_dsp_desc *chip;
u32 interface_mask[2] = { 0 };
chip = get_chip_info(sdev->pdata);
switch (chip->hw_ip_version) {
case SOF_INTEL_TANGIER:
case SOF_INTEL_BAYTRAIL:
case SOF_INTEL_BROADWELL:
interface_mask[0] = BIT(SOF_DAI_INTEL_SSP);
break;
case SOF_INTEL_CAVS_1_5:
case SOF_INTEL_CAVS_1_5_PLUS:
interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) |
BIT(SOF_DAI_INTEL_HDA);
interface_mask[1] = BIT(SOF_DAI_INTEL_HDA);
break;
case SOF_INTEL_CAVS_1_8:
case SOF_INTEL_CAVS_2_0:
case SOF_INTEL_CAVS_2_5:
case SOF_INTEL_ACE_1_0:
interface_mask[0] = BIT(SOF_DAI_INTEL_SSP) | BIT(SOF_DAI_INTEL_DMIC) |
BIT(SOF_DAI_INTEL_HDA) | BIT(SOF_DAI_INTEL_ALH);
interface_mask[1] = BIT(SOF_DAI_INTEL_HDA);
break;
default:
break;
}
return interface_mask[sdev->dspless_mode_selected];
}
#if IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
/*
* The default for SoundWire clock stop quirks is to power gate the IP
* and do a Bus Reset, this will need to be modified when the DSP
* needs to remain in D0i3 so that the Master does not lose context
* and enumeration is not required on clock restart
*/
static int sdw_clock_stop_quirks = SDW_INTEL_CLK_STOP_BUS_RESET;
module_param(sdw_clock_stop_quirks, int, 0444);
MODULE_PARM_DESC(sdw_clock_stop_quirks, "SOF SoundWire clock stop quirks");
static int sdw_params_stream(struct device *dev,
struct sdw_intel_stream_params_data *params_data)
{
struct snd_soc_dai *d = params_data->dai;
struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(d, params_data->stream);
struct snd_sof_dai_config_data data = { 0 };
data.dai_index = (params_data->link_id << 8) | d->id;
data.dai_data = params_data->alh_stream_id;
return hda_dai_config(w, SOF_DAI_CONFIG_FLAGS_HW_PARAMS, &data);
}
struct sdw_intel_ops sdw_callback = {
.params_stream = sdw_params_stream,
};
void hda_common_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
{
struct sof_intel_hda_dev *hdev;
hdev = sdev->pdata->hw_pdata;
if (!hdev->sdw)
return;
snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC2,
HDA_DSP_REG_ADSPIC2_SNDW,
enable ? HDA_DSP_REG_ADSPIC2_SNDW : 0);
}
void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable)
{
u32 interface_mask = hda_get_interface_mask(sdev);
const struct sof_intel_dsp_desc *chip;
if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
return;
chip = get_chip_info(sdev->pdata);
if (chip && chip->enable_sdw_irq)
chip->enable_sdw_irq(sdev, enable);
}
static int hda_sdw_acpi_scan(struct snd_sof_dev *sdev)
{
u32 interface_mask = hda_get_interface_mask(sdev);
struct sof_intel_hda_dev *hdev;
acpi_handle handle;
int ret;
if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
return -EINVAL;
handle = ACPI_HANDLE(sdev->dev);
/* save ACPI info for the probe step */
hdev = sdev->pdata->hw_pdata;
ret = sdw_intel_acpi_scan(handle, &hdev->info);
if (ret < 0)
return -EINVAL;
return 0;
}
static int hda_sdw_probe(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hdev;
struct sdw_intel_res res;
void *sdw;
hdev = sdev->pdata->hw_pdata;
memset(&res, 0, sizeof(res));
res.hw_ops = &sdw_intel_cnl_hw_ops;
res.mmio_base = sdev->bar[HDA_DSP_BAR];
res.shim_base = hdev->desc->sdw_shim_base;
res.alh_base = hdev->desc->sdw_alh_base;
res.irq = sdev->ipc_irq;
res.handle = hdev->info.handle;
res.parent = sdev->dev;
res.ops = &sdw_callback;
res.dev = sdev->dev;
res.clock_stop_quirks = sdw_clock_stop_quirks;
/*
* ops and arg fields are not populated for now,
* they will be needed when the DAI callbacks are
* provided
*/
/* we could filter links here if needed, e.g for quirks */
res.count = hdev->info.count;
res.link_mask = hdev->info.link_mask;
sdw = sdw_intel_probe(&res);
if (!sdw) {
dev_err(sdev->dev, "error: SoundWire probe failed\n");
return -EINVAL;
}
/* save context */
hdev->sdw = sdw;
return 0;
}
int hda_sdw_check_lcount_common(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hdev;
struct sdw_intel_ctx *ctx;
u32 caps;
hdev = sdev->pdata->hw_pdata;
ctx = hdev->sdw;
caps = snd_sof_dsp_read(sdev, HDA_DSP_BAR, ctx->shim_base + SDW_SHIM_LCAP);
caps &= SDW_SHIM_LCAP_LCOUNT_MASK;
/* Check HW supported vs property value */
if (caps < ctx->count) {
dev_err(sdev->dev,
"%s: BIOS master count %d is larger than hardware capabilities %d\n",
__func__, ctx->count, caps);
return -EINVAL;
}
return 0;
}
static int hda_sdw_check_lcount(struct snd_sof_dev *sdev)
{
const struct sof_intel_dsp_desc *chip;
chip = get_chip_info(sdev->pdata);
if (chip && chip->read_sdw_lcount)
return chip->read_sdw_lcount(sdev);
return 0;
}
int hda_sdw_startup(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hdev;
struct snd_sof_pdata *pdata = sdev->pdata;
int ret;
hdev = sdev->pdata->hw_pdata;
if (!hdev->sdw)
return 0;
if (pdata->machine && !pdata->machine->mach_params.link_mask)
return 0;
ret = hda_sdw_check_lcount(sdev);
if (ret < 0)
return ret;
return sdw_intel_startup(hdev->sdw);
}
static int hda_sdw_exit(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hdev;
hdev = sdev->pdata->hw_pdata;
hda_sdw_int_enable(sdev, false);
if (hdev->sdw)
sdw_intel_exit(hdev->sdw);
hdev->sdw = NULL;
return 0;
}
bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hdev;
bool ret = false;
u32 irq_status;
hdev = sdev->pdata->hw_pdata;
if (!hdev->sdw)
return ret;
/* store status */
irq_status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS2);
/* invalid message ? */
if (irq_status == 0xffffffff)
goto out;
/* SDW message ? */
if (irq_status & HDA_DSP_REG_ADSPIS2_SNDW)
ret = true;
out:
return ret;
}
static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
{
u32 interface_mask = hda_get_interface_mask(sdev);
const struct sof_intel_dsp_desc *chip;
if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
return false;
chip = get_chip_info(sdev->pdata);
if (chip && chip->check_sdw_irq)
return chip->check_sdw_irq(sdev);
return false;
}
static irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
{
return sdw_intel_thread(irq, context);
}
static bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
{
u32 interface_mask = hda_get_interface_mask(sdev);
struct sof_intel_hda_dev *hdev;
if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
return false;
hdev = sdev->pdata->hw_pdata;
if (hdev->sdw &&
snd_sof_dsp_read(sdev, HDA_DSP_BAR,
hdev->desc->sdw_shim_base + SDW_SHIM_WAKESTS))
return true;
return false;
}
void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
{
u32 interface_mask = hda_get_interface_mask(sdev);
struct sof_intel_hda_dev *hdev;
if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
return;
hdev = sdev->pdata->hw_pdata;
if (!hdev->sdw)
return;
sdw_intel_process_wakeen_event(hdev->sdw);
}
#else /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */
static inline int hda_sdw_acpi_scan(struct snd_sof_dev *sdev)
{
return 0;
}
static inline int hda_sdw_probe(struct snd_sof_dev *sdev)
{
return 0;
}
static inline int hda_sdw_exit(struct snd_sof_dev *sdev)
{
return 0;
}
static inline bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
{
return false;
}
static inline irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
{
return IRQ_HANDLED;
}
static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
{
return false;
}
#endif /* IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE) */
/*
* Debug
*/
struct hda_dsp_msg_code {
u32 code;
const char *text;
};
#if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
static bool hda_use_msi = true;
module_param_named(use_msi, hda_use_msi, bool, 0444);
MODULE_PARM_DESC(use_msi, "SOF HDA use PCI MSI mode");
#else
#define hda_use_msi (1)
#endif
int sof_hda_position_quirk = SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS;
module_param_named(position_quirk, sof_hda_position_quirk, int, 0444);
MODULE_PARM_DESC(position_quirk, "SOF HDaudio position quirk");
static char *hda_model;
module_param(hda_model, charp, 0444);
MODULE_PARM_DESC(hda_model, "Use the given HDA board model.");
static int dmic_num_override = -1;
module_param_named(dmic_num, dmic_num_override, int, 0444);
MODULE_PARM_DESC(dmic_num, "SOF HDA DMIC number");
static int mclk_id_override = -1;
module_param_named(mclk_id, mclk_id_override, int, 0444);
MODULE_PARM_DESC(mclk_id, "SOF SSP mclk_id");
static const struct hda_dsp_msg_code hda_dsp_rom_fw_error_texts[] = {
{HDA_DSP_ROM_CSE_ERROR, "error: cse error"},
{HDA_DSP_ROM_CSE_WRONG_RESPONSE, "error: cse wrong response"},
{HDA_DSP_ROM_IMR_TO_SMALL, "error: IMR too small"},
{HDA_DSP_ROM_BASE_FW_NOT_FOUND, "error: base fw not found"},
{HDA_DSP_ROM_CSE_VALIDATION_FAILED, "error: signature verification failed"},
{HDA_DSP_ROM_IPC_FATAL_ERROR, "error: ipc fatal error"},
{HDA_DSP_ROM_L2_CACHE_ERROR, "error: L2 cache error"},
{HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL, "error: load offset too small"},
{HDA_DSP_ROM_API_PTR_INVALID, "error: API ptr invalid"},
{HDA_DSP_ROM_BASEFW_INCOMPAT, "error: base fw incompatible"},
{HDA_DSP_ROM_UNHANDLED_INTERRUPT, "error: unhandled interrupt"},
{HDA_DSP_ROM_MEMORY_HOLE_ECC, "error: ECC memory hole"},
{HDA_DSP_ROM_KERNEL_EXCEPTION, "error: kernel exception"},
{HDA_DSP_ROM_USER_EXCEPTION, "error: user exception"},
{HDA_DSP_ROM_UNEXPECTED_RESET, "error: unexpected reset"},
{HDA_DSP_ROM_NULL_FW_ENTRY, "error: null FW entry point"},
};
#define FSR_ROM_STATE_ENTRY(state) {FSR_STATE_ROM_##state, #state}
static const struct hda_dsp_msg_code fsr_rom_state_names[] = {
FSR_ROM_STATE_ENTRY(INIT),
FSR_ROM_STATE_ENTRY(INIT_DONE),
FSR_ROM_STATE_ENTRY(CSE_MANIFEST_LOADED),
FSR_ROM_STATE_ENTRY(FW_MANIFEST_LOADED),
FSR_ROM_STATE_ENTRY(FW_FW_LOADED),
FSR_ROM_STATE_ENTRY(FW_ENTERED),
FSR_ROM_STATE_ENTRY(VERIFY_FEATURE_MASK),
FSR_ROM_STATE_ENTRY(GET_LOAD_OFFSET),
FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT),
FSR_ROM_STATE_ENTRY(FETCH_ROM_EXT_DONE),
/* CSE states */
FSR_ROM_STATE_ENTRY(CSE_IMR_REQUEST),
FSR_ROM_STATE_ENTRY(CSE_IMR_GRANTED),
FSR_ROM_STATE_ENTRY(CSE_VALIDATE_IMAGE_REQUEST),
FSR_ROM_STATE_ENTRY(CSE_IMAGE_VALIDATED),
FSR_ROM_STATE_ENTRY(CSE_IPC_IFACE_INIT),
FSR_ROM_STATE_ENTRY(CSE_IPC_RESET_PHASE_1),
FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL_ENTRY),
FSR_ROM_STATE_ENTRY(CSE_IPC_OPERATIONAL),
FSR_ROM_STATE_ENTRY(CSE_IPC_DOWN),
};
#define FSR_BRINGUP_STATE_ENTRY(state) {FSR_STATE_BRINGUP_##state, #state}
static const struct hda_dsp_msg_code fsr_bringup_state_names[] = {
FSR_BRINGUP_STATE_ENTRY(INIT),
FSR_BRINGUP_STATE_ENTRY(INIT_DONE),
FSR_BRINGUP_STATE_ENTRY(HPSRAM_LOAD),
FSR_BRINGUP_STATE_ENTRY(UNPACK_START),
FSR_BRINGUP_STATE_ENTRY(IMR_RESTORE),
FSR_BRINGUP_STATE_ENTRY(FW_ENTERED),
};
#define FSR_WAIT_STATE_ENTRY(state) {FSR_WAIT_FOR_##state, #state}
static const struct hda_dsp_msg_code fsr_wait_state_names[] = {
FSR_WAIT_STATE_ENTRY(IPC_BUSY),
FSR_WAIT_STATE_ENTRY(IPC_DONE),
FSR_WAIT_STATE_ENTRY(CACHE_INVALIDATION),
FSR_WAIT_STATE_ENTRY(LP_SRAM_OFF),
FSR_WAIT_STATE_ENTRY(DMA_BUFFER_FULL),
FSR_WAIT_STATE_ENTRY(CSE_CSR),
};
#define FSR_MODULE_NAME_ENTRY(mod) [FSR_MOD_##mod] = #mod
static const char * const fsr_module_names[] = {
FSR_MODULE_NAME_ENTRY(ROM),
FSR_MODULE_NAME_ENTRY(ROM_BYP),
FSR_MODULE_NAME_ENTRY(BASE_FW),
FSR_MODULE_NAME_ENTRY(LP_BOOT),
FSR_MODULE_NAME_ENTRY(BRNGUP),
FSR_MODULE_NAME_ENTRY(ROM_EXT),
};
static const char *
hda_dsp_get_state_text(u32 code, const struct hda_dsp_msg_code *msg_code,
size_t array_size)
{
int i;
for (i = 0; i < array_size; i++) {
if (code == msg_code[i].code)
return msg_code[i].text;
}
return NULL;
}
static void hda_dsp_get_state(struct snd_sof_dev *sdev, const char *level)
{
const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata);
const char *state_text, *error_text, *module_text;
u32 fsr, state, wait_state, module, error_code;
fsr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg);
state = FSR_TO_STATE_CODE(fsr);
wait_state = FSR_TO_WAIT_STATE_CODE(fsr);
module = FSR_TO_MODULE_CODE(fsr);
if (module > FSR_MOD_ROM_EXT)
module_text = "unknown";
else
module_text = fsr_module_names[module];
if (module == FSR_MOD_BRNGUP)
state_text = hda_dsp_get_state_text(state, fsr_bringup_state_names,
ARRAY_SIZE(fsr_bringup_state_names));
else
state_text = hda_dsp_get_state_text(state, fsr_rom_state_names,
ARRAY_SIZE(fsr_rom_state_names));
/* not for us, must be generic sof message */
if (!state_text) {
dev_printk(level, sdev->dev, "%#010x: unknown ROM status value\n", fsr);
return;
}
if (wait_state) {
const char *wait_state_text;
wait_state_text = hda_dsp_get_state_text(wait_state, fsr_wait_state_names,
ARRAY_SIZE(fsr_wait_state_names));
if (!wait_state_text)
wait_state_text = "unknown";
dev_printk(level, sdev->dev,
"%#010x: module: %s, state: %s, waiting for: %s, %s\n",
fsr, module_text, state_text, wait_state_text,
fsr & FSR_HALTED ? "not running" : "running");
} else {
dev_printk(level, sdev->dev, "%#010x: module: %s, state: %s, %s\n",
fsr, module_text, state_text,
fsr & FSR_HALTED ? "not running" : "running");
}
error_code = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + 4);
if (!error_code)
return;
error_text = hda_dsp_get_state_text(error_code, hda_dsp_rom_fw_error_texts,
ARRAY_SIZE(hda_dsp_rom_fw_error_texts));
if (!error_text)
error_text = "unknown";
if (state == FSR_STATE_FW_ENTERED)
dev_printk(level, sdev->dev, "status code: %#x (%s)\n", error_code,
error_text);
else
dev_printk(level, sdev->dev, "error code: %#x (%s)\n", error_code,
error_text);
}
static void hda_dsp_get_registers(struct snd_sof_dev *sdev,
struct sof_ipc_dsp_oops_xtensa *xoops,
struct sof_ipc_panic_info *panic_info,
u32 *stack, size_t stack_words)
{
u32 offset = sdev->dsp_oops_offset;
/* first read registers */
sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
/* note: variable AR register array is not read */
/* then get panic info */
if (xoops->arch_hdr.totalsize > EXCEPT_MAX_HDR_SIZE) {
dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
xoops->arch_hdr.totalsize);
return;
}
offset += xoops->arch_hdr.totalsize;
sof_block_read(sdev, sdev->mmio_bar, offset,
panic_info, sizeof(*panic_info));
/* then get the stack */
offset += sizeof(*panic_info);
sof_block_read(sdev, sdev->mmio_bar, offset, stack,
stack_words * sizeof(u32));
}
/* dump the first 8 dwords representing the extended ROM status */
static void hda_dsp_dump_ext_rom_status(struct snd_sof_dev *sdev, const char *level,
u32 flags)
{
const struct sof_intel_dsp_desc *chip;
char msg[128];
int len = 0;
u32 value;
int i;
chip = get_chip_info(sdev->pdata);
for (i = 0; i < HDA_EXT_ROM_STATUS_SIZE; i++) {
value = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->rom_status_reg + i * 0x4);
len += scnprintf(msg + len, sizeof(msg) - len, " 0x%x", value);
}
dev_printk(level, sdev->dev, "extended rom status: %s", msg);
}
void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags)
{
char *level = (flags & SOF_DBG_DUMP_OPTIONAL) ? KERN_DEBUG : KERN_ERR;
struct sof_ipc_dsp_oops_xtensa xoops;
struct sof_ipc_panic_info panic_info;
u32 stack[HDA_DSP_STACK_DUMP_SIZE];
/* print ROM/FW status */
hda_dsp_get_state(sdev, level);
/* The firmware register dump only available with IPC3 */
if (flags & SOF_DBG_DUMP_REGS && sdev->pdata->ipc_type == SOF_IPC) {
u32 status = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_STATUS);
u32 panic = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_SRAM_REG_FW_TRACEP);
hda_dsp_get_registers(sdev, &xoops, &panic_info, stack,
HDA_DSP_STACK_DUMP_SIZE);
sof_print_oops_and_stack(sdev, level, status, panic, &xoops,
&panic_info, stack, HDA_DSP_STACK_DUMP_SIZE);
} else {
hda_dsp_dump_ext_rom_status(sdev, level, flags);
}
}
static bool hda_check_ipc_irq(struct snd_sof_dev *sdev)
{
const struct sof_intel_dsp_desc *chip;
chip = get_chip_info(sdev->pdata);
if (chip && chip->check_ipc_irq)
return chip->check_ipc_irq(sdev);
return false;
}
void hda_ipc_irq_dump(struct snd_sof_dev *sdev)
{
u32 adspis;
u32 intsts;
u32 intctl;
u32 ppsts;
u8 rirbsts;
/* read key IRQ stats and config registers */
adspis = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIS);
intsts = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
intctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL);
ppsts = snd_sof_dsp_read(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPSTS);
rirbsts = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, AZX_REG_RIRBSTS);
dev_err(sdev->dev, "hda irq intsts 0x%8.8x intlctl 0x%8.8x rirb %2.2x\n",
intsts, intctl, rirbsts);
dev_err(sdev->dev, "dsp irq ppsts 0x%8.8x adspis 0x%8.8x\n", ppsts, adspis);
}
void hda_ipc_dump(struct snd_sof_dev *sdev)
{
u32 hipcie;
u32 hipct;
u32 hipcctl;
hda_ipc_irq_dump(sdev);
/* read IPC status */
hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
/* dump the IPC regs */
/* TODO: parse the raw msg */
dev_err(sdev->dev, "host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
hipcie, hipct, hipcctl);
}
void hda_ipc4_dump(struct snd_sof_dev *sdev)
{
u32 hipci, hipcie, hipct, hipcte, hipcctl;
hda_ipc_irq_dump(sdev);
hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCI);
hipcie = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCIE);
hipct = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCT);
hipcte = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCTE);
hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_HIPCCTL);
/* dump the IPC regs */
/* TODO: parse the raw msg */
dev_err(sdev->dev, "Host IPC initiator: %#x|%#x, target: %#x|%#x, ctl: %#x\n",
hipci, hipcie, hipct, hipcte, hipcctl);
}
bool hda_ipc4_tx_is_busy(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
u32 val;
val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, chip->ipc_req);
return !!(val & chip->ipc_req_mask);
}
static int hda_init(struct snd_sof_dev *sdev)
{
struct hda_bus *hbus;
struct hdac_bus *bus;
struct pci_dev *pci = to_pci_dev(sdev->dev);
int ret;
hbus = sof_to_hbus(sdev);
bus = sof_to_bus(sdev);
/* HDA bus init */
sof_hda_bus_init(sdev, &pci->dev);
if (sof_hda_position_quirk == SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS)
bus->use_posbuf = 0;
else
bus->use_posbuf = 1;
bus->bdl_pos_adj = 0;
bus->sync_write = 1;
mutex_init(&hbus->prepare_mutex);
hbus->pci = pci;
hbus->mixer_assigned = -1;
hbus->modelname = hda_model;
/* initialise hdac bus */
bus->addr = pci_resource_start(pci, 0);
bus->remap_addr = pci_ioremap_bar(pci, 0);
if (!bus->remap_addr) {
dev_err(bus->dev, "error: ioremap error\n");
return -ENXIO;
}
/* HDA base */
sdev->bar[HDA_DSP_HDA_BAR] = bus->remap_addr;
/* init i915 and HDMI codecs */
ret = hda_codec_i915_init(sdev);
if (ret < 0)
dev_warn(sdev->dev, "init of i915 and HDMI codec failed\n");
/* get controller capabilities */
ret = hda_dsp_ctrl_get_caps(sdev);
if (ret < 0)
dev_err(sdev->dev, "error: get caps error\n");
return ret;
}
static int check_dmic_num(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
struct nhlt_acpi_table *nhlt;
int dmic_num = 0;
nhlt = hdev->nhlt;
if (nhlt)
dmic_num = intel_nhlt_get_dmic_geo(sdev->dev, nhlt);
/* allow for module parameter override */
if (dmic_num_override != -1) {
dev_dbg(sdev->dev,
"overriding DMICs detected in NHLT tables %d by kernel param %d\n",
dmic_num, dmic_num_override);
dmic_num = dmic_num_override;
}
if (dmic_num < 0 || dmic_num > 4) {
dev_dbg(sdev->dev, "invalid dmic_number %d\n", dmic_num);
dmic_num = 0;
}
return dmic_num;
}
static int check_nhlt_ssp_mask(struct snd_sof_dev *sdev)
{
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
struct nhlt_acpi_table *nhlt;
int ssp_mask = 0;
nhlt = hdev->nhlt;
if (!nhlt)
return ssp_mask;
if (intel_nhlt_has_endpoint_type(nhlt, NHLT_LINK_SSP)) {
ssp_mask = intel_nhlt_ssp_endpoint_mask(nhlt, NHLT_DEVICE_I2S);
if (ssp_mask)
dev_info(sdev->dev, "NHLT_DEVICE_I2S detected, ssp_mask %#x\n", ssp_mask);
}
return ssp_mask;
}
static int check_nhlt_ssp_mclk_mask(struct snd_sof_dev *sdev, int ssp_num)
{
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
struct nhlt_acpi_table *nhlt;
nhlt = hdev->nhlt;
if (!nhlt)
return 0;
return intel_nhlt_ssp_mclk_mask(nhlt, ssp_num);
}
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC) || IS_ENABLED(CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE)
static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
const char *sof_tplg_filename,
const char *idisp_str,
const char *dmic_str)
{
const char *tplg_filename = NULL;
char *filename, *tmp;
const char *split_ext;
filename = kstrdup(sof_tplg_filename, GFP_KERNEL);
if (!filename)
return NULL;
/* this assumes a .tplg extension */
tmp = filename;
split_ext = strsep(&tmp, ".");
if (split_ext)
tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
"%s%s%s.tplg",
split_ext, idisp_str, dmic_str);
kfree(filename);
return tplg_filename;
}
static int dmic_detect_topology_fixup(struct snd_sof_dev *sdev,
const char **tplg_filename,
const char *idisp_str,
int *dmic_found,
bool tplg_fixup)
{
const char *dmic_str;
int dmic_num;
/* first check for DMICs (using NHLT or module parameter) */
dmic_num = check_dmic_num(sdev);
switch (dmic_num) {
case 1:
dmic_str = "-1ch";
break;
case 2:
dmic_str = "-2ch";
break;
case 3:
dmic_str = "-3ch";
break;
case 4:
dmic_str = "-4ch";
break;
default:
dmic_num = 0;
dmic_str = "";
break;
}
if (tplg_fixup) {
const char *default_tplg_filename = *tplg_filename;
const char *fixed_tplg_filename;
fixed_tplg_filename = fixup_tplg_name(sdev, default_tplg_filename,
idisp_str, dmic_str);
if (!fixed_tplg_filename)
return -ENOMEM;
*tplg_filename = fixed_tplg_filename;
}
dev_info(sdev->dev, "DMICs detected in NHLT tables: %d\n", dmic_num);
*dmic_found = dmic_num;
return 0;
}
#endif
static int hda_init_caps(struct snd_sof_dev *sdev)
{
u32 interface_mask = hda_get_interface_mask(sdev);
struct hdac_bus *bus = sof_to_bus(sdev);
struct snd_sof_pdata *pdata = sdev->pdata;
struct sof_intel_hda_dev *hdev = pdata->hw_pdata;
u32 link_mask;
int ret = 0;
/* check if dsp is there */
if (bus->ppcap)
dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n");
/* Init HDA controller after i915 init */
ret = hda_dsp_ctrl_init_chip(sdev);
if (ret < 0) {
dev_err(bus->dev, "error: init chip failed with ret: %d\n",
ret);
return ret;
}
hda_bus_ml_init(bus);
/* Skip SoundWire if it is not supported */
if (!(interface_mask & BIT(SOF_DAI_INTEL_ALH)))
goto skip_soundwire;
/* scan SoundWire capabilities exposed by DSDT */
ret = hda_sdw_acpi_scan(sdev);
if (ret < 0) {
dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n");
goto skip_soundwire;
}
link_mask = hdev->info.link_mask;
if (!link_mask) {
dev_dbg(sdev->dev, "skipping SoundWire, no links enabled\n");
goto skip_soundwire;
}
/*
* probe/allocate SoundWire resources.
* The hardware configuration takes place in hda_sdw_startup
* after power rails are enabled.
* It's entirely possible to have a mix of I2S/DMIC/SoundWire
* devices, so we allocate the resources in all cases.
*/
ret = hda_sdw_probe(sdev);
if (ret < 0) {
dev_err(sdev->dev, "error: SoundWire probe error\n");
return ret;
}
skip_soundwire:
/* create codec instances */
hda_codec_probe_bus(sdev);
if (!HDA_IDISP_CODEC(bus->codec_mask))
hda_codec_i915_display_power(sdev, false);
hda_bus_ml_put_all(bus);
return 0;
}
static irqreturn_t hda_dsp_interrupt_handler(int irq, void *context)
{
struct snd_sof_dev *sdev = context;
/*
* Get global interrupt status. It includes all hardware interrupt
* sources in the Intel HD Audio controller.
*/
if (snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS) &
SOF_HDA_INTSTS_GIS) {
/* disable GIE interrupt */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
SOF_HDA_INTCTL,
SOF_HDA_INT_GLOBAL_EN,
0);
return IRQ_WAKE_THREAD;
}
return IRQ_NONE;
}
static irqreturn_t hda_dsp_interrupt_thread(int irq, void *context)
{
struct snd_sof_dev *sdev = context;
struct sof_intel_hda_dev *hdev = sdev->pdata->hw_pdata;
/* deal with streams and controller first */
if (hda_dsp_check_stream_irq(sdev)) {
trace_sof_intel_hda_irq(sdev, "stream");
hda_dsp_stream_threaded_handler(irq, sdev);
}
if (hda_check_ipc_irq(sdev)) {