-
Notifications
You must be signed in to change notification settings - Fork 102
/
cs42l42.c
1968 lines (1773 loc) · 57.4 KB
/
cs42l42.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// SPDX-License-Identifier: GPL-2.0-only
/*
* cs42l42.c -- CS42L42 ALSA SoC audio driver
*
* Copyright 2016 Cirrus Logic, Inc.
*
* Author: James Schulman <james.schulman@cirrus.com>
* Author: Brian Austin <brian.austin@cirrus.com>
* Author: Michael White <michael.white@cirrus.com>
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/version.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/gpio/consumer.h>
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/of_device.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>
#include <dt-bindings/sound/cs42l42.h>
#include "cs42l42.h"
static const struct reg_default cs42l42_reg_defaults[] = {
{ CS42L42_FRZ_CTL, 0x00 },
{ CS42L42_SRC_CTL, 0x10 },
{ CS42L42_MCLK_STATUS, 0x02 },
{ CS42L42_MCLK_CTL, 0x02 },
{ CS42L42_SFTRAMP_RATE, 0xA4 },
{ CS42L42_I2C_DEBOUNCE, 0x88 },
{ CS42L42_I2C_STRETCH, 0x03 },
{ CS42L42_I2C_TIMEOUT, 0xB7 },
{ CS42L42_PWR_CTL1, 0xFF },
{ CS42L42_PWR_CTL2, 0x84 },
{ CS42L42_PWR_CTL3, 0x20 },
{ CS42L42_RSENSE_CTL1, 0x40 },
{ CS42L42_RSENSE_CTL2, 0x00 },
{ CS42L42_OSC_SWITCH, 0x00 },
{ CS42L42_OSC_SWITCH_STATUS, 0x05 },
{ CS42L42_RSENSE_CTL3, 0x1B },
{ CS42L42_TSENSE_CTL, 0x1B },
{ CS42L42_TSRS_INT_DISABLE, 0x00 },
{ CS42L42_TRSENSE_STATUS, 0x00 },
{ CS42L42_HSDET_CTL1, 0x77 },
{ CS42L42_HSDET_CTL2, 0x00 },
{ CS42L42_HS_SWITCH_CTL, 0xF3 },
{ CS42L42_HS_DET_STATUS, 0x00 },
{ CS42L42_HS_CLAMP_DISABLE, 0x00 },
{ CS42L42_MCLK_SRC_SEL, 0x00 },
{ CS42L42_SPDIF_CLK_CFG, 0x00 },
{ CS42L42_FSYNC_PW_LOWER, 0x00 },
{ CS42L42_FSYNC_PW_UPPER, 0x00 },
{ CS42L42_FSYNC_P_LOWER, 0xF9 },
{ CS42L42_FSYNC_P_UPPER, 0x00 },
{ CS42L42_ASP_CLK_CFG, 0x00 },
{ CS42L42_ASP_FRM_CFG, 0x10 },
{ CS42L42_FS_RATE_EN, 0x00 },
{ CS42L42_IN_ASRC_CLK, 0x00 },
{ CS42L42_OUT_ASRC_CLK, 0x00 },
{ CS42L42_PLL_DIV_CFG1, 0x00 },
{ CS42L42_ADC_OVFL_STATUS, 0x00 },
{ CS42L42_MIXER_STATUS, 0x00 },
{ CS42L42_SRC_STATUS, 0x00 },
{ CS42L42_ASP_RX_STATUS, 0x00 },
{ CS42L42_ASP_TX_STATUS, 0x00 },
{ CS42L42_CODEC_STATUS, 0x00 },
{ CS42L42_DET_INT_STATUS1, 0x00 },
{ CS42L42_DET_INT_STATUS2, 0x00 },
{ CS42L42_SRCPL_INT_STATUS, 0x00 },
{ CS42L42_VPMON_STATUS, 0x00 },
{ CS42L42_PLL_LOCK_STATUS, 0x00 },
{ CS42L42_TSRS_PLUG_STATUS, 0x00 },
{ CS42L42_ADC_OVFL_INT_MASK, 0x01 },
{ CS42L42_MIXER_INT_MASK, 0x0F },
{ CS42L42_SRC_INT_MASK, 0x0F },
{ CS42L42_ASP_RX_INT_MASK, 0x1F },
{ CS42L42_ASP_TX_INT_MASK, 0x0F },
{ CS42L42_CODEC_INT_MASK, 0x03 },
{ CS42L42_SRCPL_INT_MASK, 0xFF },
{ CS42L42_VPMON_INT_MASK, 0x01 },
{ CS42L42_PLL_LOCK_INT_MASK, 0x01 },
{ CS42L42_TSRS_PLUG_INT_MASK, 0x0F },
{ CS42L42_PLL_CTL1, 0x00 },
{ CS42L42_PLL_DIV_FRAC0, 0x00 },
{ CS42L42_PLL_DIV_FRAC1, 0x00 },
{ CS42L42_PLL_DIV_FRAC2, 0x00 },
{ CS42L42_PLL_DIV_INT, 0x40 },
{ CS42L42_PLL_CTL3, 0x10 },
{ CS42L42_PLL_CAL_RATIO, 0x80 },
{ CS42L42_PLL_CTL4, 0x03 },
{ CS42L42_LOAD_DET_RCSTAT, 0x00 },
{ CS42L42_LOAD_DET_DONE, 0x00 },
{ CS42L42_LOAD_DET_EN, 0x00 },
{ CS42L42_HSBIAS_SC_AUTOCTL, 0x03 },
{ CS42L42_WAKE_CTL, 0xC0 },
{ CS42L42_ADC_DISABLE_MUTE, 0x00 },
{ CS42L42_TIPSENSE_CTL, 0x02 },
{ CS42L42_MISC_DET_CTL, 0x03 },
{ CS42L42_MIC_DET_CTL1, 0x1F },
{ CS42L42_MIC_DET_CTL2, 0x2F },
{ CS42L42_DET_STATUS1, 0x00 },
{ CS42L42_DET_STATUS2, 0x00 },
{ CS42L42_DET_INT1_MASK, 0xE0 },
{ CS42L42_DET_INT2_MASK, 0xFF },
{ CS42L42_HS_BIAS_CTL, 0xC2 },
{ CS42L42_ADC_CTL, 0x00 },
{ CS42L42_ADC_VOLUME, 0x00 },
{ CS42L42_ADC_WNF_HPF_CTL, 0x71 },
{ CS42L42_DAC_CTL1, 0x00 },
{ CS42L42_DAC_CTL2, 0x02 },
{ CS42L42_HP_CTL, 0x0D },
{ CS42L42_CLASSH_CTL, 0x07 },
{ CS42L42_MIXER_CHA_VOL, 0x3F },
{ CS42L42_MIXER_ADC_VOL, 0x3F },
{ CS42L42_MIXER_CHB_VOL, 0x3F },
{ CS42L42_EQ_COEF_IN0, 0x22 },
{ CS42L42_EQ_COEF_IN1, 0x00 },
{ CS42L42_EQ_COEF_IN2, 0x00 },
{ CS42L42_EQ_COEF_IN3, 0x00 },
{ CS42L42_EQ_COEF_RW, 0x00 },
{ CS42L42_EQ_COEF_OUT0, 0x00 },
{ CS42L42_EQ_COEF_OUT1, 0x00 },
{ CS42L42_EQ_COEF_OUT2, 0x00 },
{ CS42L42_EQ_COEF_OUT3, 0x00 },
{ CS42L42_EQ_INIT_STAT, 0x00 },
{ CS42L42_EQ_START_FILT, 0x00 },
{ CS42L42_EQ_MUTE_CTL, 0x00 },
{ CS42L42_SP_RX_CH_SEL, 0x04 },
{ CS42L42_SP_RX_ISOC_CTL, 0x04 },
{ CS42L42_SP_RX_FS, 0x8C },
{ CS42l42_SPDIF_CH_SEL, 0x0E },
{ CS42L42_SP_TX_ISOC_CTL, 0x04 },
{ CS42L42_SP_TX_FS, 0xCC },
{ CS42L42_SPDIF_SW_CTL1, 0x3F },
{ CS42L42_SRC_SDIN_FS, 0x40 },
{ CS42L42_SRC_SDOUT_FS, 0x40 },
{ CS42L42_SPDIF_CTL1, 0x01 },
{ CS42L42_SPDIF_CTL2, 0x00 },
{ CS42L42_SPDIF_CTL3, 0x00 },
{ CS42L42_SPDIF_CTL4, 0x42 },
{ CS42L42_ASP_TX_SZ_EN, 0x00 },
{ CS42L42_ASP_TX_CH_EN, 0x00 },
{ CS42L42_ASP_TX_CH_AP_RES, 0x0F },
{ CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
{ CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
{ CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 },
{ CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 },
{ CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_EN, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 },
{ CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 },
{ CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 },
{ CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 },
{ CS42L42_SUB_REVID, 0x03 },
};
static bool cs42l42_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L42_PAGE_REGISTER:
case CS42L42_DEVID_AB:
case CS42L42_DEVID_CD:
case CS42L42_DEVID_E:
case CS42L42_FABID:
case CS42L42_REVID:
case CS42L42_FRZ_CTL:
case CS42L42_SRC_CTL:
case CS42L42_MCLK_STATUS:
case CS42L42_MCLK_CTL:
case CS42L42_SFTRAMP_RATE:
case CS42L42_I2C_DEBOUNCE:
case CS42L42_I2C_STRETCH:
case CS42L42_I2C_TIMEOUT:
case CS42L42_PWR_CTL1:
case CS42L42_PWR_CTL2:
case CS42L42_PWR_CTL3:
case CS42L42_RSENSE_CTL1:
case CS42L42_RSENSE_CTL2:
case CS42L42_OSC_SWITCH:
case CS42L42_OSC_SWITCH_STATUS:
case CS42L42_RSENSE_CTL3:
case CS42L42_TSENSE_CTL:
case CS42L42_TSRS_INT_DISABLE:
case CS42L42_TRSENSE_STATUS:
case CS42L42_HSDET_CTL1:
case CS42L42_HSDET_CTL2:
case CS42L42_HS_SWITCH_CTL:
case CS42L42_HS_DET_STATUS:
case CS42L42_HS_CLAMP_DISABLE:
case CS42L42_MCLK_SRC_SEL:
case CS42L42_SPDIF_CLK_CFG:
case CS42L42_FSYNC_PW_LOWER:
case CS42L42_FSYNC_PW_UPPER:
case CS42L42_FSYNC_P_LOWER:
case CS42L42_FSYNC_P_UPPER:
case CS42L42_ASP_CLK_CFG:
case CS42L42_ASP_FRM_CFG:
case CS42L42_FS_RATE_EN:
case CS42L42_IN_ASRC_CLK:
case CS42L42_OUT_ASRC_CLK:
case CS42L42_PLL_DIV_CFG1:
case CS42L42_ADC_OVFL_STATUS:
case CS42L42_MIXER_STATUS:
case CS42L42_SRC_STATUS:
case CS42L42_ASP_RX_STATUS:
case CS42L42_ASP_TX_STATUS:
case CS42L42_CODEC_STATUS:
case CS42L42_DET_INT_STATUS1:
case CS42L42_DET_INT_STATUS2:
case CS42L42_SRCPL_INT_STATUS:
case CS42L42_VPMON_STATUS:
case CS42L42_PLL_LOCK_STATUS:
case CS42L42_TSRS_PLUG_STATUS:
case CS42L42_ADC_OVFL_INT_MASK:
case CS42L42_MIXER_INT_MASK:
case CS42L42_SRC_INT_MASK:
case CS42L42_ASP_RX_INT_MASK:
case CS42L42_ASP_TX_INT_MASK:
case CS42L42_CODEC_INT_MASK:
case CS42L42_SRCPL_INT_MASK:
case CS42L42_VPMON_INT_MASK:
case CS42L42_PLL_LOCK_INT_MASK:
case CS42L42_TSRS_PLUG_INT_MASK:
case CS42L42_PLL_CTL1:
case CS42L42_PLL_DIV_FRAC0:
case CS42L42_PLL_DIV_FRAC1:
case CS42L42_PLL_DIV_FRAC2:
case CS42L42_PLL_DIV_INT:
case CS42L42_PLL_CTL3:
case CS42L42_PLL_CAL_RATIO:
case CS42L42_PLL_CTL4:
case CS42L42_LOAD_DET_RCSTAT:
case CS42L42_LOAD_DET_DONE:
case CS42L42_LOAD_DET_EN:
case CS42L42_HSBIAS_SC_AUTOCTL:
case CS42L42_WAKE_CTL:
case CS42L42_ADC_DISABLE_MUTE:
case CS42L42_TIPSENSE_CTL:
case CS42L42_MISC_DET_CTL:
case CS42L42_MIC_DET_CTL1:
case CS42L42_MIC_DET_CTL2:
case CS42L42_DET_STATUS1:
case CS42L42_DET_STATUS2:
case CS42L42_DET_INT1_MASK:
case CS42L42_DET_INT2_MASK:
case CS42L42_HS_BIAS_CTL:
case CS42L42_ADC_CTL:
case CS42L42_ADC_VOLUME:
case CS42L42_ADC_WNF_HPF_CTL:
case CS42L42_DAC_CTL1:
case CS42L42_DAC_CTL2:
case CS42L42_HP_CTL:
case CS42L42_CLASSH_CTL:
case CS42L42_MIXER_CHA_VOL:
case CS42L42_MIXER_ADC_VOL:
case CS42L42_MIXER_CHB_VOL:
case CS42L42_EQ_COEF_IN0:
case CS42L42_EQ_COEF_IN1:
case CS42L42_EQ_COEF_IN2:
case CS42L42_EQ_COEF_IN3:
case CS42L42_EQ_COEF_RW:
case CS42L42_EQ_COEF_OUT0:
case CS42L42_EQ_COEF_OUT1:
case CS42L42_EQ_COEF_OUT2:
case CS42L42_EQ_COEF_OUT3:
case CS42L42_EQ_INIT_STAT:
case CS42L42_EQ_START_FILT:
case CS42L42_EQ_MUTE_CTL:
case CS42L42_SP_RX_CH_SEL:
case CS42L42_SP_RX_ISOC_CTL:
case CS42L42_SP_RX_FS:
case CS42l42_SPDIF_CH_SEL:
case CS42L42_SP_TX_ISOC_CTL:
case CS42L42_SP_TX_FS:
case CS42L42_SPDIF_SW_CTL1:
case CS42L42_SRC_SDIN_FS:
case CS42L42_SRC_SDOUT_FS:
case CS42L42_SPDIF_CTL1:
case CS42L42_SPDIF_CTL2:
case CS42L42_SPDIF_CTL3:
case CS42L42_SPDIF_CTL4:
case CS42L42_ASP_TX_SZ_EN:
case CS42L42_ASP_TX_CH_EN:
case CS42L42_ASP_TX_CH_AP_RES:
case CS42L42_ASP_TX_CH1_BIT_MSB:
case CS42L42_ASP_TX_CH1_BIT_LSB:
case CS42L42_ASP_TX_HIZ_DLY_CFG:
case CS42L42_ASP_TX_CH2_BIT_MSB:
case CS42L42_ASP_TX_CH2_BIT_LSB:
case CS42L42_ASP_RX_DAI0_EN:
case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
case CS42L42_SUB_REVID:
return true;
default:
return false;
}
}
static bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case CS42L42_DEVID_AB:
case CS42L42_DEVID_CD:
case CS42L42_DEVID_E:
case CS42L42_MCLK_STATUS:
case CS42L42_TRSENSE_STATUS:
case CS42L42_HS_DET_STATUS:
case CS42L42_ADC_OVFL_STATUS:
case CS42L42_MIXER_STATUS:
case CS42L42_SRC_STATUS:
case CS42L42_ASP_RX_STATUS:
case CS42L42_ASP_TX_STATUS:
case CS42L42_CODEC_STATUS:
case CS42L42_DET_INT_STATUS1:
case CS42L42_DET_INT_STATUS2:
case CS42L42_SRCPL_INT_STATUS:
case CS42L42_VPMON_STATUS:
case CS42L42_PLL_LOCK_STATUS:
case CS42L42_TSRS_PLUG_STATUS:
case CS42L42_LOAD_DET_RCSTAT:
case CS42L42_LOAD_DET_DONE:
case CS42L42_DET_STATUS1:
case CS42L42_DET_STATUS2:
return true;
default:
return false;
}
}
static const struct regmap_range_cfg cs42l42_page_range = {
.name = "Pages",
.range_min = 0,
.range_max = CS42L42_MAX_REGISTER,
.selector_reg = CS42L42_PAGE_REGISTER,
.selector_mask = 0xff,
.selector_shift = 0,
.window_start = 0,
.window_len = 256,
};
static const struct regmap_config cs42l42_regmap = {
.reg_bits = 8,
.val_bits = 8,
.readable_reg = cs42l42_readable_register,
.volatile_reg = cs42l42_volatile_register,
.ranges = &cs42l42_page_range,
.num_ranges = 1,
.max_register = CS42L42_MAX_REGISTER,
.reg_defaults = cs42l42_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.use_single_read = true,
.use_single_write = true,
};
static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
static const char * const cs42l42_hpf_freq_text[] = {
"1.86Hz", "120Hz", "235Hz", "466Hz"
};
static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
CS42L42_ADC_HPF_CF_SHIFT,
cs42l42_hpf_freq_text);
static const char * const cs42l42_wnf3_freq_text[] = {
"160Hz", "180Hz", "200Hz", "220Hz",
"240Hz", "260Hz", "280Hz", "300Hz"
};
static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
CS42L42_ADC_WNF_CF_SHIFT,
cs42l42_wnf3_freq_text);
static const char * const cs42l42_wnf05_freq_text[] = {
"280Hz", "315Hz", "350Hz", "385Hz",
"420Hz", "455Hz", "490Hz", "525Hz"
};
static SOC_ENUM_SINGLE_DECL(cs42l42_wnf05_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
CS42L42_ADC_WNF_CF_SHIFT,
cs42l42_wnf05_freq_text);
static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
/* ADC Volume and Filter Controls */
SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
CS42L42_ADC_INV_SHIFT, true, false),
SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
CS42L42_ADC_WNF_EN_SHIFT, true, false),
SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
CS42L42_ADC_HPF_EN_SHIFT, true, false),
SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
SOC_ENUM("WNF 05dB Freq", cs42l42_wnf05_freq_enum),
/* DAC Volume and Filter Controls */
SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
CS42L42_DACA_INV_SHIFT, true, false),
SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
CS42L42_DACB_INV_SHIFT, true, false),
SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
CS42L42_DAC_HPF_EN_SHIFT, true, false),
SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
0x3f, 1, mixer_tlv)
};
static int cs42l42_hpdrv_evt(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
if (event & SND_SOC_DAPM_POST_PMU) {
/* Enable the channels */
snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
CS42L42_ASP_RX0_CH_EN_MASK,
(CS42L42_ASP_RX0_CH1_EN |
CS42L42_ASP_RX0_CH2_EN) <<
CS42L42_ASP_RX0_CH_EN_SHIFT);
/* Power up */
snd_soc_component_update_bits(component, CS42L42_PWR_CTL1,
CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
CS42L42_HP_PDN_MASK, 0);
} else if (event & SND_SOC_DAPM_PRE_PMD) {
/* Disable the channels */
snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
CS42L42_ASP_RX0_CH_EN_MASK, 0);
/* Power down */
snd_soc_component_update_bits(component, CS42L42_PWR_CTL1,
CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
CS42L42_HP_PDN_MASK,
CS42L42_ASP_DAI_PDN_MASK | CS42L42_MIXER_PDN_MASK |
CS42L42_HP_PDN_MASK);
} else {
dev_err(component->dev, "Invalid event 0x%x\n", event);
}
return 0;
}
static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("HP"),
SND_SOC_DAPM_AIF_IN("SDIN", NULL, 0, CS42L42_ASP_CLK_CFG,
CS42L42_ASP_SCLK_EN_SHIFT, false),
SND_SOC_DAPM_OUT_DRV_E("HPDRV", SND_SOC_NOPM, 0,
0, NULL, 0, cs42l42_hpdrv_evt,
SND_SOC_DAPM_POST_PMU |
SND_SOC_DAPM_PRE_PMD)
};
static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
{"SDIN", NULL, "Playback"},
{"HPDRV", NULL, "SDIN"},
{"HP", NULL, "HPDRV"}
};
static int cs42l42_set_bias_level(struct snd_soc_component *component,
enum snd_soc_bias_level level)
{
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
int ret;
switch (level) {
case SND_SOC_BIAS_ON:
break;
case SND_SOC_BIAS_PREPARE:
break;
case SND_SOC_BIAS_STANDBY:
if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
regcache_cache_only(cs42l42->regmap, false);
regcache_sync(cs42l42->regmap);
ret = regulator_bulk_enable(
ARRAY_SIZE(cs42l42->supplies),
cs42l42->supplies);
if (ret != 0) {
dev_err(component->dev,
"Failed to enable regulators: %d\n",
ret);
return ret;
}
}
break;
case SND_SOC_BIAS_OFF:
regcache_cache_only(cs42l42->regmap, true);
regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
cs42l42->supplies);
break;
}
return 0;
}
static int cs42l42_component_probe(struct snd_soc_component *component)
{
struct cs42l42_private *cs42l42 =
(struct cs42l42_private *)snd_soc_component_get_drvdata(component);
cs42l42->component = component;
return 0;
}
static const struct snd_soc_component_driver soc_component_dev_cs42l42 = {
.probe = cs42l42_component_probe,
.set_bias_level = cs42l42_set_bias_level,
.dapm_widgets = cs42l42_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets),
.dapm_routes = cs42l42_audio_map,
.num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map),
.controls = cs42l42_snd_controls,
.num_controls = ARRAY_SIZE(cs42l42_snd_controls),
.idle_bias_on = 1,
.endianness = 1,
.non_legacy_dai_naming = 1,
};
struct cs42l42_pll_params {
u32 sclk;
u8 mclk_div;
u8 mclk_src_sel;
u8 sclk_prediv;
u8 pll_div_int;
u32 pll_div_frac;
u8 pll_mode;
u8 pll_divout;
u32 mclk_int;
u8 pll_cal_ratio;
};
/*
* Common PLL Settings for given SCLK
* Table 4-5 from the Datasheet
*/
static const struct cs42l42_pll_params pll_ratio_table[] = {
{ 1536000, 0, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125 },
{ 2822400, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
{ 3000000, 0, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
{ 3072000, 0, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
{ 4000000, 0, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96 },
{ 4096000, 0, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94 },
{ 5644800, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128 },
{ 6000000, 0, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128 },
{ 6144000, 0, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125 },
{ 11289600, 0, 0, 0, 0, 0, 0, 0, 11289600, 0 },
{ 12000000, 0, 0, 0, 0, 0, 0, 0, 12000000, 0 },
{ 12288000, 0, 0, 0, 0, 0, 0, 0, 12288000, 0 },
{ 22579200, 1, 0, 0, 0, 0, 0, 0, 22579200, 0 },
{ 24000000, 1, 0, 0, 0, 0, 0, 0, 24000000, 0 },
{ 24576000, 1, 0, 0, 0, 0, 0, 0, 24576000, 0 }
};
static int cs42l42_pll_config(struct snd_soc_component *component)
{
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
int i;
u32 fsync;
for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
if (pll_ratio_table[i].sclk == cs42l42->sclk) {
/* Configure the internal sample rate */
snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
CS42L42_INTERNAL_FS_MASK,
((pll_ratio_table[i].mclk_int !=
12000000) &&
(pll_ratio_table[i].mclk_int !=
24000000)) <<
CS42L42_INTERNAL_FS_SHIFT);
/* Set the MCLK src (PLL or SCLK) and the divide
* ratio
*/
snd_soc_component_update_bits(component, CS42L42_MCLK_SRC_SEL,
CS42L42_MCLK_SRC_SEL_MASK |
CS42L42_MCLKDIV_MASK,
(pll_ratio_table[i].mclk_src_sel
<< CS42L42_MCLK_SRC_SEL_SHIFT) |
(pll_ratio_table[i].mclk_div <<
CS42L42_MCLKDIV_SHIFT));
/* Set up the LRCLK */
fsync = cs42l42->sclk / cs42l42->srate;
if (((fsync * cs42l42->srate) != cs42l42->sclk)
|| ((fsync % 2) != 0)) {
dev_err(component->dev,
"Unsupported sclk %d/sample rate %d\n",
cs42l42->sclk,
cs42l42->srate);
return -EINVAL;
}
/* Set the LRCLK period */
snd_soc_component_update_bits(component,
CS42L42_FSYNC_P_LOWER,
CS42L42_FSYNC_PERIOD_MASK,
CS42L42_FRAC0_VAL(fsync - 1) <<
CS42L42_FSYNC_PERIOD_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_FSYNC_P_UPPER,
CS42L42_FSYNC_PERIOD_MASK,
CS42L42_FRAC1_VAL(fsync - 1) <<
CS42L42_FSYNC_PERIOD_SHIFT);
/* Set the LRCLK to 50% duty cycle */
fsync = fsync / 2;
snd_soc_component_update_bits(component,
CS42L42_FSYNC_PW_LOWER,
CS42L42_FSYNC_PULSE_WIDTH_MASK,
CS42L42_FRAC0_VAL(fsync - 1) <<
CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_FSYNC_PW_UPPER,
CS42L42_FSYNC_PULSE_WIDTH_MASK,
CS42L42_FRAC1_VAL(fsync - 1) <<
CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_ASP_FRM_CFG,
CS42L42_ASP_5050_MASK,
CS42L42_ASP_5050_MASK);
/* Set the frame delay to 1.0 SCLK clocks */
snd_soc_component_update_bits(component, CS42L42_ASP_FRM_CFG,
CS42L42_ASP_FSD_MASK,
CS42L42_ASP_FSD_1_0 <<
CS42L42_ASP_FSD_SHIFT);
/* Set the sample rates (96k or lower) */
snd_soc_component_update_bits(component, CS42L42_FS_RATE_EN,
CS42L42_FS_EN_MASK,
(CS42L42_FS_EN_IASRC_96K |
CS42L42_FS_EN_OASRC_96K) <<
CS42L42_FS_EN_SHIFT);
/* Set the input/output internal MCLK clock ~12 MHz */
snd_soc_component_update_bits(component, CS42L42_IN_ASRC_CLK,
CS42L42_CLK_IASRC_SEL_MASK,
CS42L42_CLK_IASRC_SEL_12 <<
CS42L42_CLK_IASRC_SEL_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_OUT_ASRC_CLK,
CS42L42_CLK_OASRC_SEL_MASK,
CS42L42_CLK_OASRC_SEL_12 <<
CS42L42_CLK_OASRC_SEL_SHIFT);
if (pll_ratio_table[i].mclk_src_sel == 0) {
/* Pass the clock straight through */
snd_soc_component_update_bits(component,
CS42L42_PLL_CTL1,
CS42L42_PLL_START_MASK, 0);
} else {
/* Configure PLL per table 4-5 */
snd_soc_component_update_bits(component,
CS42L42_PLL_DIV_CFG1,
CS42L42_SCLK_PREDIV_MASK,
pll_ratio_table[i].sclk_prediv
<< CS42L42_SCLK_PREDIV_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_PLL_DIV_INT,
CS42L42_PLL_DIV_INT_MASK,
pll_ratio_table[i].pll_div_int
<< CS42L42_PLL_DIV_INT_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_PLL_DIV_FRAC0,
CS42L42_PLL_DIV_FRAC_MASK,
CS42L42_FRAC0_VAL(
pll_ratio_table[i].pll_div_frac)
<< CS42L42_PLL_DIV_FRAC_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_PLL_DIV_FRAC1,
CS42L42_PLL_DIV_FRAC_MASK,
CS42L42_FRAC1_VAL(
pll_ratio_table[i].pll_div_frac)
<< CS42L42_PLL_DIV_FRAC_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_PLL_DIV_FRAC2,
CS42L42_PLL_DIV_FRAC_MASK,
CS42L42_FRAC2_VAL(
pll_ratio_table[i].pll_div_frac)
<< CS42L42_PLL_DIV_FRAC_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_PLL_CTL4,
CS42L42_PLL_MODE_MASK,
pll_ratio_table[i].pll_mode
<< CS42L42_PLL_MODE_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_PLL_CTL3,
CS42L42_PLL_DIVOUT_MASK,
pll_ratio_table[i].pll_divout
<< CS42L42_PLL_DIVOUT_SHIFT);
snd_soc_component_update_bits(component,
CS42L42_PLL_CAL_RATIO,
CS42L42_PLL_CAL_RATIO_MASK,
pll_ratio_table[i].pll_cal_ratio
<< CS42L42_PLL_CAL_RATIO_SHIFT);
}
return 0;
}
}
return -EINVAL;
}
static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_component *component = codec_dai->component;
u32 asp_cfg_val = 0;
switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
case SND_SOC_DAIFMT_CBS_CFM:
asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
CS42L42_ASP_MODE_SHIFT;
break;
case SND_SOC_DAIFMT_CBS_CFS:
asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
CS42L42_ASP_MODE_SHIFT;
break;
default:
return -EINVAL;
}
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
break;
default:
return -EINVAL;
}
/* Bitclock/frame inversion */
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
break;
case SND_SOC_DAIFMT_NB_IF:
asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
break;
case SND_SOC_DAIFMT_IB_NF:
break;
case SND_SOC_DAIFMT_IB_IF:
asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
break;
}
snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
CS42L42_ASP_SCPOL_MASK |
CS42L42_ASP_LCPOL_MASK,
asp_cfg_val);
return 0;
}
static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_component *component = dai->component;
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
unsigned int width = (params_width(params) / 8) - 1;
unsigned int val = 0;
cs42l42->srate = params_rate(params);
switch(substream->stream) {
case SNDRV_PCM_STREAM_PLAYBACK:
val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
/* channel 1 on low LRCLK */
snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
CS42L42_ASP_RX_CH_AP_MASK |
CS42L42_ASP_RX_CH_RES_MASK, val);
/* Channel 2 on high LRCLK */
val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
CS42L42_ASP_RX_CH_AP_MASK |
CS42L42_ASP_RX_CH_RES_MASK, val);
break;
default:
break;
}
return cs42l42_pll_config(component);
}
static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
int clk_id, unsigned int freq, int dir)
{
struct snd_soc_component *component = dai->component;
struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
cs42l42->sclk = freq;
return 0;
}
static int cs42l42_mute(struct snd_soc_dai *dai, int mute, int direction)
{
struct snd_soc_component *component = dai->component;
unsigned int regval;
u8 fullScaleVol;
if (mute) {
/* Mark SCLK as not present to turn on the internal
* oscillator.
*/
snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH,
CS42L42_SCLK_PRESENT_MASK, 0);
snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
CS42L42_PLL_START_MASK,
0 << CS42L42_PLL_START_SHIFT);
/* Mute the headphone */
snd_soc_component_update_bits(component, CS42L42_HP_CTL,
CS42L42_HP_ANA_AMUTE_MASK |
CS42L42_HP_ANA_BMUTE_MASK,
CS42L42_HP_ANA_AMUTE_MASK |
CS42L42_HP_ANA_BMUTE_MASK);
} else {
snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
CS42L42_PLL_START_MASK,
1 << CS42L42_PLL_START_SHIFT);
/* Read the headphone load */
regval = snd_soc_component_read(component, CS42L42_LOAD_DET_RCSTAT);
if (((regval & CS42L42_RLA_STAT_MASK) >>
CS42L42_RLA_STAT_SHIFT) == CS42L42_RLA_STAT_15_OHM) {
fullScaleVol = CS42L42_HP_FULL_SCALE_VOL_MASK;
} else {
fullScaleVol = 0;
}
/* Un-mute the headphone, set the full scale volume flag */
snd_soc_component_update_bits(component, CS42L42_HP_CTL,
CS42L42_HP_ANA_AMUTE_MASK |
CS42L42_HP_ANA_BMUTE_MASK |
CS42L42_HP_FULL_SCALE_VOL_MASK, fullScaleVol);
/* Mark SCLK as present, turn off internal oscillator */
snd_soc_component_update_bits(component, CS42L42_OSC_SWITCH,
CS42L42_SCLK_PRESENT_MASK,
CS42L42_SCLK_PRESENT_MASK);
}
return 0;
}
#define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
SNDRV_PCM_FMTBIT_S24_LE |\
SNDRV_PCM_FMTBIT_S32_LE )
static const struct snd_soc_dai_ops cs42l42_ops = {
.hw_params = cs42l42_pcm_hw_params,
.set_fmt = cs42l42_set_dai_fmt,
.set_sysclk = cs42l42_set_sysclk,
.mute_stream = cs42l42_mute,
.no_capture_mute = 1,
};
static struct snd_soc_dai_driver cs42l42_dai = {
.name = "cs42l42",
.playback = {
.stream_name = "Playback",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = CS42L42_FORMATS,
},
.capture = {
.stream_name = "Capture",
.channels_min = 1,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_8000_192000,
.formats = CS42L42_FORMATS,
},
.ops = &cs42l42_ops,
};
static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
{
unsigned int hs_det_status;
unsigned int int_status;
/* Mask the auto detect interrupt */
regmap_update_bits(cs42l42->regmap,
CS42L42_CODEC_INT_MASK,
CS42L42_PDN_DONE_MASK |
CS42L42_HSDET_AUTO_DONE_MASK,
(1 << CS42L42_PDN_DONE_SHIFT) |
(1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
/* Set hs detect to automatic, disabled mode */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSDET_CTL2,
CS42L42_HSDET_CTRL_MASK |
CS42L42_HSDET_SET_MASK |
CS42L42_HSBIAS_REF_MASK |
CS42L42_HSDET_AUTO_TIME_MASK,
(2 << CS42L42_HSDET_CTRL_SHIFT) |
(2 << CS42L42_HSDET_SET_SHIFT) |
(0 << CS42L42_HSBIAS_REF_SHIFT) |
(3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
/* Read and save the hs detection result */
regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
CS42L42_HSDET_TYPE_SHIFT;
/* Set up button detection */
if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
(cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
/* Set auto HS bias settings to default */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSBIAS_SC_AUTOCTL,
CS42L42_HSBIAS_SENSE_EN_MASK |
CS42L42_AUTO_HSBIAS_HIZ_MASK |
CS42L42_TIP_SENSE_EN_MASK |
CS42L42_HSBIAS_SENSE_TRIP_MASK,
(0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
(0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
(0 << CS42L42_TIP_SENSE_EN_SHIFT) |
(3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
/* Set up hs detect level sensitivity */
regmap_update_bits(cs42l42->regmap,
CS42L42_MIC_DET_CTL1,
CS42L42_LATCH_TO_VP_MASK |
CS42L42_EVENT_STAT_SEL_MASK |
CS42L42_HS_DET_LEVEL_MASK,
(1 << CS42L42_LATCH_TO_VP_SHIFT) |
(0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
(cs42l42->bias_thresholds[0] <<
CS42L42_HS_DET_LEVEL_SHIFT));
/* Set auto HS bias settings to default */
regmap_update_bits(cs42l42->regmap,
CS42L42_HSBIAS_SC_AUTOCTL,
CS42L42_HSBIAS_SENSE_EN_MASK |
CS42L42_AUTO_HSBIAS_HIZ_MASK |
CS42L42_TIP_SENSE_EN_MASK |
CS42L42_HSBIAS_SENSE_TRIP_MASK,
(1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
(1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
(0 << CS42L42_TIP_SENSE_EN_SHIFT) |
(3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
/* Turn on level detect circuitry */
regmap_update_bits(cs42l42->regmap,
CS42L42_MISC_DET_CTL,