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amdgpu_smu.c
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amdgpu_smu.c
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/*
* Copyright 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#define SWSMU_CODE_LAYER_L1
#include <linux/firmware.h>
#include <linux/pci.h>
#include "amdgpu.h"
#include "amdgpu_smu.h"
#include "smu_internal.h"
#include "atom.h"
#include "arcturus_ppt.h"
#include "navi10_ppt.h"
#include "sienna_cichlid_ppt.h"
#include "renoir_ppt.h"
#include "vangogh_ppt.h"
#include "aldebaran_ppt.h"
#include "yellow_carp_ppt.h"
#include "cyan_skillfish_ppt.h"
#include "amd_pcie.h"
/*
* DO NOT use these for err/warn/info/debug messages.
* Use dev_err, dev_warn, dev_info and dev_dbg instead.
* They are more MGPU friendly.
*/
#undef pr_err
#undef pr_warn
#undef pr_info
#undef pr_debug
static const struct amd_pm_funcs swsmu_pm_funcs;
static int smu_force_smuclk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t mask);
static int smu_handle_task(struct smu_context *smu,
enum amd_dpm_forced_level level,
enum amd_pp_task task_id,
bool lock_needed);
static int smu_reset(struct smu_context *smu);
static int smu_set_fan_speed_pwm(void *handle, u32 speed);
static int smu_set_fan_control_mode(struct smu_context *smu, int value);
static int smu_set_power_limit(void *handle, uint32_t limit);
static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
static int smu_sys_get_pp_feature_mask(void *handle,
char *buf)
{
struct smu_context *smu = handle;
int size = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
mutex_lock(&smu->mutex);
size = smu_get_pp_feature_mask(smu, buf);
mutex_unlock(&smu->mutex);
return size;
}
static int smu_sys_set_pp_feature_mask(void *handle,
uint64_t new_mask)
{
struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
mutex_lock(&smu->mutex);
ret = smu_set_pp_feature_mask(smu, new_mask);
mutex_unlock(&smu->mutex);
return ret;
}
int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
{
int ret = 0;
struct smu_context *smu = &adev->smu;
if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
*value = smu_get_gfx_off_status(smu);
else
ret = -EINVAL;
return ret;
}
int smu_set_soft_freq_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t min,
uint32_t max)
{
int ret = 0;
mutex_lock(&smu->mutex);
if (smu->ppt_funcs->set_soft_freq_limited_range)
ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
clk_type,
min,
max);
mutex_unlock(&smu->mutex);
return ret;
}
int smu_get_dpm_freq_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *min,
uint32_t *max)
{
int ret = 0;
if (!min && !max)
return -EINVAL;
mutex_lock(&smu->mutex);
if (smu->ppt_funcs->get_dpm_ultimate_freq)
ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
clk_type,
min,
max);
mutex_unlock(&smu->mutex);
return ret;
}
static u32 smu_get_mclk(void *handle, bool low)
{
struct smu_context *smu = handle;
uint32_t clk_freq;
int ret = 0;
ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
low ? &clk_freq : NULL,
!low ? &clk_freq : NULL);
if (ret)
return 0;
return clk_freq * 100;
}
static u32 smu_get_sclk(void *handle, bool low)
{
struct smu_context *smu = handle;
uint32_t clk_freq;
int ret = 0;
ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
low ? &clk_freq : NULL,
!low ? &clk_freq : NULL);
if (ret)
return 0;
return clk_freq * 100;
}
static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
bool enable)
{
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
int ret = 0;
if (!smu->ppt_funcs->dpm_set_vcn_enable)
return 0;
if (atomic_read(&power_gate->vcn_gated) ^ enable)
return 0;
ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
if (!ret)
atomic_set(&power_gate->vcn_gated, !enable);
return ret;
}
static int smu_dpm_set_vcn_enable(struct smu_context *smu,
bool enable)
{
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
int ret = 0;
mutex_lock(&power_gate->vcn_gate_lock);
ret = smu_dpm_set_vcn_enable_locked(smu, enable);
mutex_unlock(&power_gate->vcn_gate_lock);
return ret;
}
static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu,
bool enable)
{
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
int ret = 0;
if (!smu->ppt_funcs->dpm_set_jpeg_enable)
return 0;
if (atomic_read(&power_gate->jpeg_gated) ^ enable)
return 0;
ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
if (!ret)
atomic_set(&power_gate->jpeg_gated, !enable);
return ret;
}
static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
bool enable)
{
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
int ret = 0;
mutex_lock(&power_gate->jpeg_gate_lock);
ret = smu_dpm_set_jpeg_enable_locked(smu, enable);
mutex_unlock(&power_gate->jpeg_gate_lock);
return ret;
}
/**
* smu_dpm_set_power_gate - power gate/ungate the specific IP block
*
* @handle: smu_context pointer
* @block_type: the IP block to power gate/ungate
* @gate: to power gate if true, ungate otherwise
*
* This API uses no smu->mutex lock protection due to:
* 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
* This is guarded to be race condition free by the caller.
* 2. Or get called on user setting request of power_dpm_force_performance_level.
* Under this case, the smu->mutex lock protection is already enforced on
* the parent API smu_force_performance_level of the call path.
*/
static int smu_dpm_set_power_gate(void *handle,
uint32_t block_type,
bool gate)
{
struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
switch (block_type) {
/*
* Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
* AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
*/
case AMD_IP_BLOCK_TYPE_UVD:
case AMD_IP_BLOCK_TYPE_VCN:
ret = smu_dpm_set_vcn_enable(smu, !gate);
if (ret)
dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
gate ? "gate" : "ungate");
break;
case AMD_IP_BLOCK_TYPE_GFX:
ret = smu_gfx_off_control(smu, gate);
if (ret)
dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
gate ? "enable" : "disable");
break;
case AMD_IP_BLOCK_TYPE_SDMA:
ret = smu_powergate_sdma(smu, gate);
if (ret)
dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
gate ? "gate" : "ungate");
break;
case AMD_IP_BLOCK_TYPE_JPEG:
ret = smu_dpm_set_jpeg_enable(smu, !gate);
if (ret)
dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
gate ? "gate" : "ungate");
break;
default:
dev_err(smu->adev->dev, "Unsupported block type!\n");
return -EINVAL;
}
return ret;
}
/**
* smu_set_user_clk_dependencies - set user profile clock dependencies
*
* @smu: smu_context pointer
* @clk: enum smu_clk_type type
*
* Enable/Disable the clock dependency for the @clk type.
*/
static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
{
if (smu->adev->in_suspend)
return;
if (clk == SMU_MCLK) {
smu->user_dpm_profile.clk_dependency = 0;
smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
} else if (clk == SMU_FCLK) {
/* MCLK takes precedence over FCLK */
if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
return;
smu->user_dpm_profile.clk_dependency = 0;
smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
} else if (clk == SMU_SOCCLK) {
/* MCLK takes precedence over SOCCLK */
if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
return;
smu->user_dpm_profile.clk_dependency = 0;
smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
} else
/* Add clk dependencies here, if any */
return;
}
/**
* smu_restore_dpm_user_profile - reinstate user dpm profile
*
* @smu: smu_context pointer
*
* Restore the saved user power configurations include power limit,
* clock frequencies, fan control mode and fan speed.
*/
static void smu_restore_dpm_user_profile(struct smu_context *smu)
{
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
int ret = 0;
if (!smu->adev->in_suspend)
return;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return;
/* Enable restore flag */
smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
/* set the user dpm power limit */
if (smu->user_dpm_profile.power_limit) {
ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
if (ret)
dev_err(smu->adev->dev, "Failed to set power limit value\n");
}
/* set the user dpm clock configurations */
if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
enum smu_clk_type clk_type;
for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
/*
* Iterate over smu clk type and force the saved user clk
* configs, skip if clock dependency is enabled
*/
if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
smu->user_dpm_profile.clk_mask[clk_type]) {
ret = smu_force_smuclk_levels(smu, clk_type,
smu->user_dpm_profile.clk_mask[clk_type]);
if (ret)
dev_err(smu->adev->dev,
"Failed to set clock type = %d\n", clk_type);
}
}
}
/* set the user dpm fan configurations */
if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
if (ret) {
smu->user_dpm_profile.fan_speed_pwm = 0;
smu->user_dpm_profile.fan_speed_rpm = 0;
smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
}
if (smu->user_dpm_profile.fan_speed_pwm) {
ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm);
if (ret)
dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n");
}
if (smu->user_dpm_profile.fan_speed_rpm) {
ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
if (ret)
dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n");
}
}
/* Restore user customized OD settings */
if (smu->user_dpm_profile.user_od) {
if (smu->ppt_funcs->restore_user_od_settings) {
ret = smu->ppt_funcs->restore_user_od_settings(smu);
if (ret)
dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
}
}
/* Disable restore flag */
smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
}
static int smu_get_power_num_states(void *handle,
struct pp_states_info *state_info)
{
if (!state_info)
return -EINVAL;
/* not support power state */
memset(state_info, 0, sizeof(struct pp_states_info));
state_info->nums = 1;
state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
return 0;
}
bool is_support_sw_smu(struct amdgpu_device *adev)
{
if (adev->asic_type >= CHIP_ARCTURUS)
return true;
return false;
}
bool is_support_cclk_dpm(struct amdgpu_device *adev)
{
struct smu_context *smu = &adev->smu;
if (!is_support_sw_smu(adev))
return false;
if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
return false;
return true;
}
static int smu_sys_get_pp_table(void *handle,
char **table)
{
struct smu_context *smu = handle;
struct smu_table_context *smu_table = &smu->smu_table;
uint32_t powerplay_table_size;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
return -EINVAL;
mutex_lock(&smu->mutex);
if (smu_table->hardcode_pptable)
*table = smu_table->hardcode_pptable;
else
*table = smu_table->power_play_table;
powerplay_table_size = smu_table->power_play_table_size;
mutex_unlock(&smu->mutex);
return powerplay_table_size;
}
static int smu_sys_set_pp_table(void *handle,
const char *buf,
size_t size)
{
struct smu_context *smu = handle;
struct smu_table_context *smu_table = &smu->smu_table;
ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
if (header->usStructureSize != size) {
dev_err(smu->adev->dev, "pp table size not matched !\n");
return -EIO;
}
mutex_lock(&smu->mutex);
if (!smu_table->hardcode_pptable)
smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
if (!smu_table->hardcode_pptable) {
ret = -ENOMEM;
goto failed;
}
memcpy(smu_table->hardcode_pptable, buf, size);
smu_table->power_play_table = smu_table->hardcode_pptable;
smu_table->power_play_table_size = size;
/*
* Special hw_fini action(for Navi1x, the DPMs disablement will be
* skipped) may be needed for custom pptable uploading.
*/
smu->uploading_custom_pp_table = true;
ret = smu_reset(smu);
if (ret)
dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
smu->uploading_custom_pp_table = false;
failed:
mutex_unlock(&smu->mutex);
return ret;
}
static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
{
struct smu_feature *feature = &smu->smu_feature;
int ret = 0;
uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
SMU_FEATURE_MAX/32);
if (ret)
return ret;
bitmap_or(feature->allowed, feature->allowed,
(unsigned long *)allowed_feature_mask,
feature->feature_num);
return ret;
}
static int smu_set_funcs(struct amdgpu_device *adev)
{
struct smu_context *smu = &adev->smu;
if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
smu->od_enabled = true;
switch (adev->asic_type) {
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
navi10_set_ppt_funcs(smu);
break;
case CHIP_ARCTURUS:
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
arcturus_set_ppt_funcs(smu);
/* OD is not supported on Arcturus */
smu->od_enabled =false;
break;
case CHIP_SIENNA_CICHLID:
case CHIP_NAVY_FLOUNDER:
case CHIP_DIMGREY_CAVEFISH:
case CHIP_BEIGE_GOBY:
sienna_cichlid_set_ppt_funcs(smu);
break;
case CHIP_ALDEBARAN:
aldebaran_set_ppt_funcs(smu);
/* Enable pp_od_clk_voltage node */
smu->od_enabled = true;
break;
case CHIP_RENOIR:
renoir_set_ppt_funcs(smu);
break;
case CHIP_VANGOGH:
vangogh_set_ppt_funcs(smu);
break;
case CHIP_YELLOW_CARP:
yellow_carp_set_ppt_funcs(smu);
break;
case CHIP_CYAN_SKILLFISH:
cyan_skillfish_set_ppt_funcs(smu);
break;
default:
return -EINVAL;
}
return 0;
}
static int smu_early_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = &adev->smu;
smu->adev = adev;
smu->pm_enabled = !!amdgpu_dpm;
smu->is_apu = false;
mutex_init(&smu->mutex);
mutex_init(&smu->smu_baco.mutex);
smu->smu_baco.state = SMU_BACO_STATE_EXIT;
smu->smu_baco.platform_support = false;
smu->user_dpm_profile.fan_mode = -1;
adev->powerplay.pp_handle = smu;
adev->powerplay.pp_funcs = &swsmu_pm_funcs;
return smu_set_funcs(adev);
}
static int smu_set_default_dpm_table(struct smu_context *smu)
{
struct smu_power_context *smu_power = &smu->smu_power;
struct smu_power_gate *power_gate = &smu_power->power_gate;
int vcn_gate, jpeg_gate;
int ret = 0;
if (!smu->ppt_funcs->set_default_dpm_table)
return 0;
mutex_lock(&power_gate->vcn_gate_lock);
mutex_lock(&power_gate->jpeg_gate_lock);
vcn_gate = atomic_read(&power_gate->vcn_gated);
jpeg_gate = atomic_read(&power_gate->jpeg_gated);
ret = smu_dpm_set_vcn_enable_locked(smu, true);
if (ret)
goto err0_out;
ret = smu_dpm_set_jpeg_enable_locked(smu, true);
if (ret)
goto err1_out;
ret = smu->ppt_funcs->set_default_dpm_table(smu);
if (ret)
dev_err(smu->adev->dev,
"Failed to setup default dpm clock tables!\n");
smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate);
err1_out:
smu_dpm_set_vcn_enable_locked(smu, !vcn_gate);
err0_out:
mutex_unlock(&power_gate->jpeg_gate_lock);
mutex_unlock(&power_gate->vcn_gate_lock);
return ret;
}
static int smu_late_init(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct smu_context *smu = &adev->smu;
int ret = 0;
smu_set_fine_grain_gfx_freq_parameters(smu);
if (!smu->pm_enabled)
return 0;
ret = smu_post_init(smu);
if (ret) {
dev_err(adev->dev, "Failed to post smu init!\n");
return ret;
}
if (adev->asic_type == CHIP_YELLOW_CARP)
return 0;
if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
ret = smu_set_default_od_settings(smu);
if (ret) {
dev_err(adev->dev, "Failed to setup default OD settings!\n");
return ret;
}
}
ret = smu_populate_umd_state_clk(smu);
if (ret) {
dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
return ret;
}
ret = smu_get_asic_power_limits(smu,
&smu->current_power_limit,
&smu->default_power_limit,
&smu->max_power_limit);
if (ret) {
dev_err(adev->dev, "Failed to get asic power limits!\n");
return ret;
}
if (!amdgpu_sriov_vf(adev))
smu_get_unique_id(smu);
smu_get_fan_parameters(smu);
smu_handle_task(&adev->smu,
smu->smu_dpm.dpm_level,
AMD_PP_TASK_COMPLETE_INIT,
false);
smu_restore_dpm_user_profile(smu);
return 0;
}
static int smu_init_fb_allocations(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
struct smu_table_context *smu_table = &smu->smu_table;
struct smu_table *tables = smu_table->tables;
struct smu_table *driver_table = &(smu_table->driver_table);
uint32_t max_table_size = 0;
int ret, i;
/* VRAM allocation for tool table */
if (tables[SMU_TABLE_PMSTATUSLOG].size) {
ret = amdgpu_bo_create_kernel(adev,
tables[SMU_TABLE_PMSTATUSLOG].size,
tables[SMU_TABLE_PMSTATUSLOG].align,
tables[SMU_TABLE_PMSTATUSLOG].domain,
&tables[SMU_TABLE_PMSTATUSLOG].bo,
&tables[SMU_TABLE_PMSTATUSLOG].mc_address,
&tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
if (ret) {
dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
return ret;
}
}
/* VRAM allocation for driver table */
for (i = 0; i < SMU_TABLE_COUNT; i++) {
if (tables[i].size == 0)
continue;
if (i == SMU_TABLE_PMSTATUSLOG)
continue;
if (max_table_size < tables[i].size)
max_table_size = tables[i].size;
}
driver_table->size = max_table_size;
driver_table->align = PAGE_SIZE;
driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
ret = amdgpu_bo_create_kernel(adev,
driver_table->size,
driver_table->align,
driver_table->domain,
&driver_table->bo,
&driver_table->mc_address,
&driver_table->cpu_addr);
if (ret) {
dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
&tables[SMU_TABLE_PMSTATUSLOG].mc_address,
&tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
}
return ret;
}
static int smu_fini_fb_allocations(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct smu_table *tables = smu_table->tables;
struct smu_table *driver_table = &(smu_table->driver_table);
if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
&tables[SMU_TABLE_PMSTATUSLOG].mc_address,
&tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
amdgpu_bo_free_kernel(&driver_table->bo,
&driver_table->mc_address,
&driver_table->cpu_addr);
return 0;
}
/**
* smu_alloc_memory_pool - allocate memory pool in the system memory
*
* @smu: amdgpu_device pointer
*
* This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
* and DramLogSetDramAddr can notify it changed.
*
* Returns 0 on success, error on failure.
*/
static int smu_alloc_memory_pool(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
struct smu_table_context *smu_table = &smu->smu_table;
struct smu_table *memory_pool = &smu_table->memory_pool;
uint64_t pool_size = smu->pool_size;
int ret = 0;
if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
return ret;
memory_pool->size = pool_size;
memory_pool->align = PAGE_SIZE;
memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
switch (pool_size) {
case SMU_MEMORY_POOL_SIZE_256_MB:
case SMU_MEMORY_POOL_SIZE_512_MB:
case SMU_MEMORY_POOL_SIZE_1_GB:
case SMU_MEMORY_POOL_SIZE_2_GB:
ret = amdgpu_bo_create_kernel(adev,
memory_pool->size,
memory_pool->align,
memory_pool->domain,
&memory_pool->bo,
&memory_pool->mc_address,
&memory_pool->cpu_addr);
if (ret)
dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
break;
default:
break;
}
return ret;
}
static int smu_free_memory_pool(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct smu_table *memory_pool = &smu_table->memory_pool;
if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
return 0;
amdgpu_bo_free_kernel(&memory_pool->bo,
&memory_pool->mc_address,
&memory_pool->cpu_addr);
memset(memory_pool, 0, sizeof(struct smu_table));
return 0;
}
static int smu_alloc_dummy_read_table(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct smu_table *dummy_read_1_table =
&smu_table->dummy_read_1_table;
struct amdgpu_device *adev = smu->adev;
int ret = 0;
dummy_read_1_table->size = 0x40000;
dummy_read_1_table->align = PAGE_SIZE;
dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
ret = amdgpu_bo_create_kernel(adev,
dummy_read_1_table->size,
dummy_read_1_table->align,
dummy_read_1_table->domain,
&dummy_read_1_table->bo,
&dummy_read_1_table->mc_address,
&dummy_read_1_table->cpu_addr);
if (ret)
dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
return ret;
}
static void smu_free_dummy_read_table(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
struct smu_table *dummy_read_1_table =
&smu_table->dummy_read_1_table;
amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
&dummy_read_1_table->mc_address,
&dummy_read_1_table->cpu_addr);
memset(dummy_read_1_table, 0, sizeof(struct smu_table));
}
static int smu_smc_table_sw_init(struct smu_context *smu)
{
int ret;
/**
* Create smu_table structure, and init smc tables such as
* TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
*/
ret = smu_init_smc_tables(smu);
if (ret) {
dev_err(smu->adev->dev, "Failed to init smc tables!\n");
return ret;
}
/**
* Create smu_power_context structure, and allocate smu_dpm_context and
* context size to fill the smu_power_context data.
*/
ret = smu_init_power(smu);
if (ret) {
dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
return ret;
}
/*
* allocate vram bos to store smc table contents.
*/
ret = smu_init_fb_allocations(smu);
if (ret)
return ret;
ret = smu_alloc_memory_pool(smu);
if (ret)
return ret;
ret = smu_alloc_dummy_read_table(smu);
if (ret)
return ret;
ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
if (ret)
return ret;
return 0;
}
static int smu_smc_table_sw_fini(struct smu_context *smu)
{
int ret;
smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
smu_free_dummy_read_table(smu);
ret = smu_free_memory_pool(smu);
if (ret)
return ret;
ret = smu_fini_fb_allocations(smu);
if (ret)
return ret;
ret = smu_fini_power(smu);
if (ret) {
dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
return ret;
}
ret = smu_fini_smc_tables(smu);
if (ret) {
dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
return ret;
}
return 0;
}
static void smu_throttling_logging_work_fn(struct work_struct *work)
{
struct smu_context *smu = container_of(work, struct smu_context,
throttling_logging_work);
smu_log_thermal_throttling(smu);
}