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pcie.c
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pcie.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* NXP Wireless LAN device driver: PCIE specific handling
*
* Copyright 2011-2020 NXP
*/
#include <linux/iopoll.h>
#include <linux/firmware.h>
#include "decl.h"
#include "ioctl.h"
#include "util.h"
#include "fw.h"
#include "main.h"
#include "wmm.h"
#include "11n.h"
#include "pcie.h"
#include "pcie_quirks.h"
#define PCIE_VERSION "1.0"
#define DRV_NAME "Marvell mwifiex PCIe"
static struct mwifiex_if_ops pcie_ops;
static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
.cmd_addr_lo = PCIE_SCRATCH_0_REG,
.cmd_addr_hi = PCIE_SCRATCH_1_REG,
.cmd_size = PCIE_SCRATCH_2_REG,
.fw_status = PCIE_SCRATCH_3_REG,
.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
.tx_rdptr = PCIE_SCRATCH_6_REG,
.tx_wrptr = PCIE_SCRATCH_7_REG,
.rx_rdptr = PCIE_SCRATCH_8_REG,
.rx_wrptr = PCIE_SCRATCH_9_REG,
.evt_rdptr = PCIE_SCRATCH_10_REG,
.evt_wrptr = PCIE_SCRATCH_11_REG,
.drv_rdy = PCIE_SCRATCH_12_REG,
.tx_start_ptr = 0,
.tx_mask = MWIFIEX_TXBD_MASK,
.tx_wrap_mask = 0,
.rx_mask = MWIFIEX_RXBD_MASK,
.rx_wrap_mask = 0,
.tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
.rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
.evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
.ring_flag_sop = 0,
.ring_flag_eop = 0,
.ring_flag_xs_sop = 0,
.ring_flag_xs_eop = 0,
.ring_tx_start_ptr = 0,
.pfu_enabled = 0,
.sleep_cookie = 1,
.msix_support = 0,
};
static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
.cmd_addr_lo = PCIE_SCRATCH_0_REG,
.cmd_addr_hi = PCIE_SCRATCH_1_REG,
.cmd_size = PCIE_SCRATCH_2_REG,
.fw_status = PCIE_SCRATCH_3_REG,
.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
.tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
.tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
.rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
.rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
.evt_rdptr = PCIE_SCRATCH_10_REG,
.evt_wrptr = PCIE_SCRATCH_11_REG,
.drv_rdy = PCIE_SCRATCH_12_REG,
.tx_start_ptr = 16,
.tx_mask = 0x03FF0000,
.tx_wrap_mask = 0x07FF0000,
.rx_mask = 0x000003FF,
.rx_wrap_mask = 0x000007FF,
.tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
.rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
.pfu_enabled = 1,
.sleep_cookie = 0,
.fw_dump_ctrl = PCIE_SCRATCH_13_REG,
.fw_dump_start = PCIE_SCRATCH_14_REG,
.fw_dump_end = 0xcff,
.fw_dump_host_ready = 0xee,
.fw_dump_read_done = 0xfe,
.msix_support = 0,
};
static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
.cmd_addr_lo = PCIE_SCRATCH_0_REG,
.cmd_addr_hi = PCIE_SCRATCH_1_REG,
.cmd_size = PCIE_SCRATCH_2_REG,
.fw_status = PCIE_SCRATCH_3_REG,
.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
.tx_rdptr = 0xC1A4,
.tx_wrptr = 0xC174,
.rx_rdptr = 0xC174,
.rx_wrptr = 0xC1A4,
.evt_rdptr = PCIE_SCRATCH_10_REG,
.evt_wrptr = PCIE_SCRATCH_11_REG,
.drv_rdy = PCIE_SCRATCH_12_REG,
.tx_start_ptr = 16,
.tx_mask = 0x0FFF0000,
.tx_wrap_mask = 0x1FFF0000,
.rx_mask = 0x00000FFF,
.rx_wrap_mask = 0x00001FFF,
.tx_rollover_ind = BIT(28),
.rx_rollover_ind = BIT(12),
.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
.pfu_enabled = 1,
.sleep_cookie = 0,
.fw_dump_ctrl = PCIE_SCRATCH_13_REG,
.fw_dump_start = PCIE_SCRATCH_14_REG,
.fw_dump_end = 0xcff,
.fw_dump_host_ready = 0xcc,
.fw_dump_read_done = 0xdd,
.msix_support = 0,
};
static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
{"ITCM", NULL, 0, 0xF0},
{"DTCM", NULL, 0, 0xF1},
{"SQRAM", NULL, 0, 0xF2},
{"IRAM", NULL, 0, 0xF3},
{"APU", NULL, 0, 0xF4},
{"CIU", NULL, 0, 0xF5},
{"ICU", NULL, 0, 0xF6},
{"MAC", NULL, 0, 0xF7},
};
static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
{"DUMP", NULL, 0, 0xDD},
};
static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
.reg = &mwifiex_reg_8766,
.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
.can_dump_fw = false,
.can_ext_scan = true,
};
static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
.reg = &mwifiex_reg_8897,
.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
.can_dump_fw = true,
.mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
.can_ext_scan = true,
};
static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
.reg = &mwifiex_reg_8997,
.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
.can_dump_fw = true,
.mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
.can_ext_scan = true,
};
static const struct of_device_id mwifiex_pcie_of_match_table[] __maybe_unused = {
{ .compatible = "pci11ab,2b42" },
{ .compatible = "pci1b4b,2b42" },
{ }
};
static int mwifiex_pcie_probe_of(struct device *dev)
{
if (!of_match_node(mwifiex_pcie_of_match_table, dev->of_node)) {
dev_err(dev, "required compatible string missing\n");
return -EINVAL;
}
return 0;
}
static void mwifiex_pcie_work(struct work_struct *work);
static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter);
static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter);
static int
mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb,
size_t size, int flags)
{
struct pcie_service_card *card = adapter->card;
struct mwifiex_dma_mapping mapping;
mapping.addr = dma_map_single(&card->dev->dev, skb->data, size, flags);
if (dma_mapping_error(&card->dev->dev, mapping.addr)) {
mwifiex_dbg(adapter, ERROR, "failed to map pci memory!\n");
return -1;
}
mapping.len = size;
mwifiex_store_mapping(skb, &mapping);
return 0;
}
static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter,
struct sk_buff *skb, int flags)
{
struct pcie_service_card *card = adapter->card;
struct mwifiex_dma_mapping mapping;
mwifiex_get_mapping(skb, &mapping);
dma_unmap_single(&card->dev->dev, mapping.addr, mapping.len, flags);
}
/*
* This function writes data into PCIE card register.
*/
static int mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data)
{
struct pcie_service_card *card = adapter->card;
iowrite32(data, card->pci_mmap1 + reg);
return 0;
}
/* This function reads data from PCIE card register.
*/
static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data)
{
struct pcie_service_card *card = adapter->card;
*data = ioread32(card->pci_mmap1 + reg);
if (*data == 0xffffffff)
return 0xffffffff;
return 0;
}
/* This function reads u8 data from PCIE card register. */
static int mwifiex_read_reg_byte(struct mwifiex_adapter *adapter,
int reg, u8 *data)
{
struct pcie_service_card *card = adapter->card;
*data = ioread8(card->pci_mmap1 + reg);
return 0;
}
/*
* This function reads sleep cookie and checks if FW is ready
*/
static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter)
{
u32 cookie_value;
struct pcie_service_card *card = adapter->card;
const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
if (!reg->sleep_cookie)
return true;
if (card->sleep_cookie_vbase) {
cookie_value = get_unaligned_le32(card->sleep_cookie_vbase);
mwifiex_dbg(adapter, INFO,
"info: ACCESS_HW: sleep cookie=0x%x\n",
cookie_value);
if (cookie_value == FW_AWAKE_COOKIE)
return true;
}
return false;
}
#ifdef CONFIG_PM_SLEEP
/*
* Kernel needs to suspend all functions separately. Therefore all
* registered functions must have drivers with suspend and resume
* methods. Failing that the kernel simply removes the whole card.
*
* If already not suspended, this function allocates and sends a host
* sleep activate request to the firmware and turns off the traffic.
*/
static int mwifiex_pcie_suspend(struct device *dev)
{
struct mwifiex_adapter *adapter;
struct pcie_service_card *card = dev_get_drvdata(dev);
/* Might still be loading firmware */
wait_for_completion(&card->fw_done);
adapter = card->adapter;
if (!adapter) {
dev_err(dev, "adapter is not valid\n");
return 0;
}
mwifiex_enable_wake(adapter);
/* Enable the Host Sleep */
if (!mwifiex_enable_hs(adapter)) {
mwifiex_dbg(adapter, ERROR,
"cmd: failed to suspend\n");
clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags);
mwifiex_disable_wake(adapter);
return -EFAULT;
}
flush_workqueue(adapter->workqueue);
/* Indicate device suspended */
set_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags);
clear_bit(MWIFIEX_IS_HS_ENABLING, &adapter->work_flags);
return 0;
}
/*
* Kernel needs to suspend all functions separately. Therefore all
* registered functions must have drivers with suspend and resume
* methods. Failing that the kernel simply removes the whole card.
*
* If already not resumed, this function turns on the traffic and
* sends a host sleep cancel request to the firmware.
*/
static int mwifiex_pcie_resume(struct device *dev)
{
struct mwifiex_adapter *adapter;
struct pcie_service_card *card = dev_get_drvdata(dev);
if (!card->adapter) {
dev_err(dev, "adapter structure is not valid\n");
return 0;
}
adapter = card->adapter;
if (!test_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags)) {
mwifiex_dbg(adapter, WARN,
"Device already resumed\n");
return 0;
}
clear_bit(MWIFIEX_IS_SUSPENDED, &adapter->work_flags);
mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA),
MWIFIEX_ASYNC_CMD);
mwifiex_disable_wake(adapter);
return 0;
}
#endif
/*
* This function probes an mwifiex device and registers it. It allocates
* the card structure, enables PCIE function number and initiates the
* device registration and initialization procedure by adding a logical
* interface.
*/
static int mwifiex_pcie_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct pcie_service_card *card;
int ret;
pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n",
pdev->vendor, pdev->device, pdev->revision);
card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
if (!card)
return -ENOMEM;
init_completion(&card->fw_done);
card->dev = pdev;
if (ent->driver_data) {
struct mwifiex_pcie_device *data = (void *)ent->driver_data;
card->pcie.reg = data->reg;
card->pcie.blksz_fw_dl = data->blksz_fw_dl;
card->pcie.tx_buf_size = data->tx_buf_size;
card->pcie.can_dump_fw = data->can_dump_fw;
card->pcie.mem_type_mapping_tbl = data->mem_type_mapping_tbl;
card->pcie.num_mem_types = data->num_mem_types;
card->pcie.can_ext_scan = data->can_ext_scan;
INIT_WORK(&card->work, mwifiex_pcie_work);
}
/* device tree node parsing and platform specific configuration*/
if (pdev->dev.of_node) {
ret = mwifiex_pcie_probe_of(&pdev->dev);
if (ret)
return ret;
}
/* check quirks */
mwifiex_initialize_quirks(card);
if (mwifiex_add_card(card, &card->fw_done, &pcie_ops,
MWIFIEX_PCIE, &pdev->dev)) {
pr_err("%s failed\n", __func__);
return -1;
}
return 0;
}
/*
* This function removes the interface and frees up the card structure.
*/
static void mwifiex_pcie_remove(struct pci_dev *pdev)
{
struct pcie_service_card *card;
struct mwifiex_adapter *adapter;
struct mwifiex_private *priv;
const struct mwifiex_pcie_card_reg *reg;
u32 fw_status;
card = pci_get_drvdata(pdev);
wait_for_completion(&card->fw_done);
adapter = card->adapter;
if (!adapter || !adapter->priv_num)
return;
reg = card->pcie.reg;
if (reg)
mwifiex_read_reg(adapter, reg->fw_status, &fw_status);
else
fw_status = -1;
if (fw_status == FIRMWARE_READY_PCIE && !adapter->mfg_mode) {
mwifiex_deauthenticate_all(adapter);
priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY);
mwifiex_disable_auto_ds(priv);
mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN);
}
mwifiex_remove_card(adapter);
}
static void mwifiex_pcie_shutdown(struct pci_dev *pdev)
{
mwifiex_pcie_remove(pdev);
return;
}
static void mwifiex_pcie_coredump(struct device *dev)
{
struct pci_dev *pdev;
struct pcie_service_card *card;
pdev = container_of(dev, struct pci_dev, dev);
card = pci_get_drvdata(pdev);
if (!test_and_set_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP,
&card->work_flags))
schedule_work(&card->work);
}
static const struct pci_device_id mwifiex_ids[] = {
{
PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8766P,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
.driver_data = (unsigned long)&mwifiex_pcie8766,
},
{
PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8897,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
.driver_data = (unsigned long)&mwifiex_pcie8897,
},
{
PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
.driver_data = (unsigned long)&mwifiex_pcie8997,
},
{
PCIE_VENDOR_ID_V2_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8997,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
.driver_data = (unsigned long)&mwifiex_pcie8997,
},
{},
};
MODULE_DEVICE_TABLE(pci, mwifiex_ids);
/*
* Cleanup all software without cleaning anything related to PCIe and HW.
*/
static void mwifiex_pcie_reset_prepare(struct pci_dev *pdev)
{
struct pcie_service_card *card = pci_get_drvdata(pdev);
struct mwifiex_adapter *adapter = card->adapter;
if (!adapter) {
dev_err(&pdev->dev, "%s: adapter structure is not valid\n",
__func__);
return;
}
mwifiex_dbg(adapter, INFO,
"%s: vendor=0x%4.04x device=0x%4.04x rev=%d Pre-FLR\n",
__func__, pdev->vendor, pdev->device, pdev->revision);
mwifiex_shutdown_sw(adapter);
clear_bit(MWIFIEX_IFACE_WORK_DEVICE_DUMP, &card->work_flags);
clear_bit(MWIFIEX_IFACE_WORK_CARD_RESET, &card->work_flags);
/* On MS Surface gen4+ devices FLR isn't effective to recover from
* hangups, so we power-cycle the card instead.
*/
if (card->quirks & QUIRK_FW_RST_D3COLD)
mwifiex_pcie_reset_d3cold_quirk(pdev);
mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__);
card->pci_reset_ongoing = true;
}
/*
* Kernel stores and restores PCIe function context before and after performing
* FLR respectively. Reconfigure the software and firmware including firmware
* redownload.
*/
static void mwifiex_pcie_reset_done(struct pci_dev *pdev)
{
struct pcie_service_card *card = pci_get_drvdata(pdev);
struct mwifiex_adapter *adapter = card->adapter;
int ret;
if (!adapter) {
dev_err(&pdev->dev, "%s: adapter structure is not valid\n",
__func__);
return;
}
mwifiex_dbg(adapter, INFO,
"%s: vendor=0x%4.04x device=0x%4.04x rev=%d Post-FLR\n",
__func__, pdev->vendor, pdev->device, pdev->revision);
ret = mwifiex_reinit_sw(adapter);
if (ret)
dev_err(&pdev->dev, "reinit failed: %d\n", ret);
else
mwifiex_dbg(adapter, INFO, "%s, successful\n", __func__);
card->pci_reset_ongoing = false;
}
static const struct pci_error_handlers mwifiex_pcie_err_handler = {
.reset_prepare = mwifiex_pcie_reset_prepare,
.reset_done = mwifiex_pcie_reset_done,
};
#ifdef CONFIG_PM_SLEEP
/* Power Management Hooks */
static SIMPLE_DEV_PM_OPS(mwifiex_pcie_pm_ops, mwifiex_pcie_suspend,
mwifiex_pcie_resume);
#endif
/* PCI Device Driver */
static struct pci_driver mwifiex_pcie = {
.name = "mwifiex_pcie",
.id_table = mwifiex_ids,
.probe = mwifiex_pcie_probe,
.remove = mwifiex_pcie_remove,
.driver = {
.coredump = mwifiex_pcie_coredump,
#ifdef CONFIG_PM_SLEEP
.pm = &mwifiex_pcie_pm_ops,
#endif
},
.shutdown = mwifiex_pcie_shutdown,
.err_handler = &mwifiex_pcie_err_handler,
};
/*
* This function adds delay loop to ensure FW is awake before proceeding.
*/
static void mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter *adapter)
{
int i = 0;
while (mwifiex_pcie_ok_to_access_hw(adapter)) {
i++;
usleep_range(10, 20);
/* 50ms max wait */
if (i == 5000)
break;
}
return;
}
static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter,
u32 max_delay_loop_cnt)
{
struct pcie_service_card *card = adapter->card;
u8 *buffer;
u32 sleep_cookie, count;
struct sk_buff *cmdrsp = card->cmdrsp_buf;
for (count = 0; count < max_delay_loop_cnt; count++) {
dma_sync_single_for_cpu(&card->dev->dev,
MWIFIEX_SKB_DMA_ADDR(cmdrsp),
sizeof(sleep_cookie), DMA_FROM_DEVICE);
buffer = cmdrsp->data;
sleep_cookie = get_unaligned_le32(buffer);
if (sleep_cookie == MWIFIEX_DEF_SLEEP_COOKIE) {
mwifiex_dbg(adapter, INFO,
"sleep cookie found at count %d\n", count);
break;
}
dma_sync_single_for_device(&card->dev->dev,
MWIFIEX_SKB_DMA_ADDR(cmdrsp),
sizeof(sleep_cookie),
DMA_FROM_DEVICE);
usleep_range(20, 30);
}
if (count >= max_delay_loop_cnt)
mwifiex_dbg(adapter, INFO,
"max count reached while accessing sleep cookie\n");
}
#define N_WAKEUP_TRIES_SHORT_INTERVAL 15
#define N_WAKEUP_TRIES_LONG_INTERVAL 35
/* This function wakes up the card by reading fw_status register. */
static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter)
{
struct pcie_service_card *card = adapter->card;
const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
int retval __maybe_unused;
mwifiex_dbg(adapter, EVENT,
"event: Wakeup device...\n");
if (reg->sleep_cookie)
mwifiex_pcie_dev_wakeup_delay(adapter);
/* The 88W8897 PCIe+USB firmware (latest version 15.68.19.p21) sometimes
* appears to ignore or miss our wakeup request, so we continue trying
* until we receive an interrupt from the card.
*/
if (read_poll_timeout(mwifiex_write_reg, retval,
READ_ONCE(adapter->int_status) != 0,
500, 500 * N_WAKEUP_TRIES_SHORT_INTERVAL,
false,
adapter, reg->fw_status, FIRMWARE_READY_PCIE)) {
if (read_poll_timeout(mwifiex_write_reg, retval,
READ_ONCE(adapter->int_status) != 0,
10000, 10000 * N_WAKEUP_TRIES_LONG_INTERVAL,
false,
adapter, reg->fw_status, FIRMWARE_READY_PCIE)) {
mwifiex_dbg(adapter, ERROR,
"Firmware didn't wake up\n");
return -EIO;
}
}
if (reg->sleep_cookie) {
mwifiex_pcie_dev_wakeup_delay(adapter);
mwifiex_dbg(adapter, INFO,
"PCIE wakeup: Setting PS_STATE_AWAKE\n");
adapter->ps_state = PS_STATE_AWAKE;
}
return 0;
}
/*
* This function is called after the card has woken up.
*
* The card configuration register is reset.
*/
static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter)
{
mwifiex_dbg(adapter, CMD,
"cmd: Wakeup device completed\n");
return 0;
}
/*
* This function disables the host interrupt.
*
* The host interrupt mask is read, the disable bit is reset and
* written back to the card host interrupt mask register.
*/
static int mwifiex_pcie_disable_host_int(struct mwifiex_adapter *adapter)
{
if (mwifiex_pcie_ok_to_access_hw(adapter)) {
if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
0x00000000)) {
mwifiex_dbg(adapter, ERROR,
"Disable host interrupt failed\n");
return -1;
}
}
atomic_set(&adapter->tx_hw_pending, 0);
return 0;
}
static void mwifiex_pcie_disable_host_int_noerr(struct mwifiex_adapter *adapter)
{
WARN_ON(mwifiex_pcie_disable_host_int(adapter));
}
/*
* This function enables the host interrupt.
*
* The host interrupt enable mask is written to the card
* host interrupt mask register.
*/
static int mwifiex_pcie_enable_host_int(struct mwifiex_adapter *adapter)
{
if (mwifiex_pcie_ok_to_access_hw(adapter)) {
/* Simply write the mask to the register */
if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK,
HOST_INTR_MASK)) {
mwifiex_dbg(adapter, ERROR,
"Enable host interrupt failed\n");
return -1;
}
}
return 0;
}
/*
* This function initializes TX buffer ring descriptors
*/
static int mwifiex_init_txq_ring(struct mwifiex_adapter *adapter)
{
struct pcie_service_card *card = adapter->card;
const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
struct mwifiex_pcie_buf_desc *desc;
struct mwifiex_pfu_buf_desc *desc2;
int i;
for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
card->tx_buf_list[i] = NULL;
if (reg->pfu_enabled) {
card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
(sizeof(*desc2) * i);
desc2 = card->txbd_ring[i];
memset(desc2, 0, sizeof(*desc2));
} else {
card->txbd_ring[i] = (void *)card->txbd_ring_vbase +
(sizeof(*desc) * i);
desc = card->txbd_ring[i];
memset(desc, 0, sizeof(*desc));
}
}
return 0;
}
/* This function initializes RX buffer ring descriptors. Each SKB is allocated
* here and after mapping PCI memory, its physical address is assigned to
* PCIE Rx buffer descriptor's physical address.
*/
static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter)
{
struct pcie_service_card *card = adapter->card;
const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
struct sk_buff *skb;
struct mwifiex_pcie_buf_desc *desc;
struct mwifiex_pfu_buf_desc *desc2;
dma_addr_t buf_pa;
int i;
for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
/* Allocate skb here so that firmware can DMA data from it */
skb = mwifiex_alloc_dma_align_buf(MWIFIEX_RX_DATA_BUF_SIZE,
GFP_KERNEL);
if (!skb) {
mwifiex_dbg(adapter, ERROR,
"Unable to allocate skb for RX ring.\n");
return -ENOMEM;
}
if (mwifiex_map_pci_memory(adapter, skb,
MWIFIEX_RX_DATA_BUF_SIZE,
DMA_FROM_DEVICE)) {
kfree_skb(skb);
return -ENOMEM;
}
buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
mwifiex_dbg(adapter, INFO,
"info: RX ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
skb, skb->len, skb->data, (u32)buf_pa,
(u32)((u64)buf_pa >> 32));
card->rx_buf_list[i] = skb;
if (reg->pfu_enabled) {
card->rxbd_ring[i] = (void *)card->rxbd_ring_vbase +
(sizeof(*desc2) * i);
desc2 = card->rxbd_ring[i];
desc2->paddr = buf_pa;
desc2->len = (u16)skb->len;
desc2->frag_len = (u16)skb->len;
desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop;
desc2->offset = 0;
} else {
card->rxbd_ring[i] = (void *)(card->rxbd_ring_vbase +
(sizeof(*desc) * i));
desc = card->rxbd_ring[i];
desc->paddr = buf_pa;
desc->len = (u16)skb->len;
desc->flags = 0;
}
}
return 0;
}
/* This function initializes event buffer ring descriptors. Each SKB is
* allocated here and after mapping PCI memory, its physical address is assigned
* to PCIE Rx buffer descriptor's physical address
*/
static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter)
{
struct pcie_service_card *card = adapter->card;
struct mwifiex_evt_buf_desc *desc;
struct sk_buff *skb;
dma_addr_t buf_pa;
int i;
for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
/* Allocate skb here so that firmware can DMA data from it */
skb = dev_alloc_skb(MAX_EVENT_SIZE);
if (!skb) {
mwifiex_dbg(adapter, ERROR,
"Unable to allocate skb for EVENT buf.\n");
return -ENOMEM;
}
skb_put(skb, MAX_EVENT_SIZE);
if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE,
DMA_FROM_DEVICE)) {
kfree_skb(skb);
return -ENOMEM;
}
buf_pa = MWIFIEX_SKB_DMA_ADDR(skb);
mwifiex_dbg(adapter, EVENT,
"info: EVT ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n",
skb, skb->len, skb->data, (u32)buf_pa,
(u32)((u64)buf_pa >> 32));
card->evt_buf_list[i] = skb;
card->evtbd_ring[i] = (void *)(card->evtbd_ring_vbase +
(sizeof(*desc) * i));
desc = card->evtbd_ring[i];
desc->paddr = buf_pa;
desc->len = (u16)skb->len;
desc->flags = 0;
}
return 0;
}
/* This function cleans up TX buffer rings. If any of the buffer list has valid
* SKB address, associated SKB is freed.
*/
static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter)
{
struct pcie_service_card *card = adapter->card;
const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
struct sk_buff *skb;
struct mwifiex_pcie_buf_desc *desc;
struct mwifiex_pfu_buf_desc *desc2;
int i;
for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
if (reg->pfu_enabled) {
desc2 = card->txbd_ring[i];
if (card->tx_buf_list[i]) {
skb = card->tx_buf_list[i];
mwifiex_unmap_pci_memory(adapter, skb,
DMA_TO_DEVICE);
dev_kfree_skb_any(skb);
}
memset(desc2, 0, sizeof(*desc2));
} else {
desc = card->txbd_ring[i];
if (card->tx_buf_list[i]) {
skb = card->tx_buf_list[i];
mwifiex_unmap_pci_memory(adapter, skb,
DMA_TO_DEVICE);
dev_kfree_skb_any(skb);
}
memset(desc, 0, sizeof(*desc));
}
card->tx_buf_list[i] = NULL;
}
atomic_set(&adapter->tx_hw_pending, 0);
return;
}
/* This function cleans up RX buffer rings. If any of the buffer list has valid
* SKB address, associated SKB is freed.
*/
static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter)
{
struct pcie_service_card *card = adapter->card;
const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
struct mwifiex_pcie_buf_desc *desc;
struct mwifiex_pfu_buf_desc *desc2;
struct sk_buff *skb;
int i;
for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) {
if (reg->pfu_enabled) {
desc2 = card->rxbd_ring[i];
if (card->rx_buf_list[i]) {
skb = card->rx_buf_list[i];
mwifiex_unmap_pci_memory(adapter, skb,
DMA_FROM_DEVICE);
dev_kfree_skb_any(skb);
}
memset(desc2, 0, sizeof(*desc2));
} else {
desc = card->rxbd_ring[i];
if (card->rx_buf_list[i]) {
skb = card->rx_buf_list[i];
mwifiex_unmap_pci_memory(adapter, skb,
DMA_FROM_DEVICE);
dev_kfree_skb_any(skb);
}
memset(desc, 0, sizeof(*desc));
}
card->rx_buf_list[i] = NULL;
}
return;
}
/* This function cleans up event buffer rings. If any of the buffer list has
* valid SKB address, associated SKB is freed.
*/
static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter)
{
struct pcie_service_card *card = adapter->card;
struct mwifiex_evt_buf_desc *desc;
struct sk_buff *skb;
int i;
for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) {
desc = card->evtbd_ring[i];
if (card->evt_buf_list[i]) {
skb = card->evt_buf_list[i];
mwifiex_unmap_pci_memory(adapter, skb,
DMA_FROM_DEVICE);
dev_kfree_skb_any(skb);
}
card->evt_buf_list[i] = NULL;
memset(desc, 0, sizeof(*desc));
}
return;
}
/* This function creates buffer descriptor ring for TX
*/
static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter)
{
struct pcie_service_card *card = adapter->card;
const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
/*
* driver maintaines the write pointer and firmware maintaines the read
* pointer. The write pointer starts at 0 (zero) while the read pointer
* starts at zero with rollover bit set
*/
card->txbd_wrptr = 0;
if (reg->pfu_enabled)