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dc_resource.c
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dc_resource.c
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/*
* Copyright 2012-15 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include <linux/slab.h>
#include "dm_services.h"
#include "resource.h"
#include "include/irq_service_interface.h"
#include "link_encoder.h"
#include "stream_encoder.h"
#include "opp.h"
#include "timing_generator.h"
#include "transform.h"
#include "dccg.h"
#include "dchubbub.h"
#include "dpp.h"
#include "core_types.h"
#include "set_mode_types.h"
#include "virtual/virtual_stream_encoder.h"
#include "dpcd_defs.h"
#if defined(CONFIG_DRM_AMD_DC_SI)
#include "dce60/dce60_resource.h"
#endif
#include "dce80/dce80_resource.h"
#include "dce100/dce100_resource.h"
#include "dce110/dce110_resource.h"
#include "dce112/dce112_resource.h"
#include "dce120/dce120_resource.h"
#if defined(CONFIG_DRM_AMD_DC_DCN)
#include "dcn10/dcn10_resource.h"
#include "dcn20/dcn20_resource.h"
#include "dcn21/dcn21_resource.h"
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
#include "../dcn30/dcn30_resource.h"
#endif
#define DC_LOGGER_INIT(logger)
enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
{
enum dce_version dc_version = DCE_VERSION_UNKNOWN;
switch (asic_id.chip_family) {
#if defined(CONFIG_DRM_AMD_DC_SI)
case FAMILY_SI:
if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
dc_version = DCE_VERSION_6_0;
else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
dc_version = DCE_VERSION_6_4;
else
dc_version = DCE_VERSION_6_1;
break;
#endif
case FAMILY_CI:
dc_version = DCE_VERSION_8_0;
break;
case FAMILY_KV:
if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
dc_version = DCE_VERSION_8_3;
else
dc_version = DCE_VERSION_8_1;
break;
case FAMILY_CZ:
dc_version = DCE_VERSION_11_0;
break;
case FAMILY_VI:
if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
dc_version = DCE_VERSION_10_0;
break;
}
if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
dc_version = DCE_VERSION_11_2;
}
if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
dc_version = DCE_VERSION_11_22;
break;
case FAMILY_AI:
if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
dc_version = DCE_VERSION_12_1;
else
dc_version = DCE_VERSION_12_0;
break;
#if defined(CONFIG_DRM_AMD_DC_DCN)
case FAMILY_RV:
dc_version = DCN_VERSION_1_0;
if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_1_01;
if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_2_1;
if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_2_1;
break;
#endif
case FAMILY_NV:
dc_version = DCN_VERSION_2_0;
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
dc_version = DCN_VERSION_3_0;
#endif
break;
default:
dc_version = DCE_VERSION_UNKNOWN;
break;
}
return dc_version;
}
struct resource_pool *dc_create_resource_pool(struct dc *dc,
const struct dc_init_data *init_data,
enum dce_version dc_version)
{
struct resource_pool *res_pool = NULL;
switch (dc_version) {
#if defined(CONFIG_DRM_AMD_DC_SI)
case DCE_VERSION_6_0:
res_pool = dce60_create_resource_pool(
init_data->num_virtual_links, dc);
break;
case DCE_VERSION_6_1:
res_pool = dce61_create_resource_pool(
init_data->num_virtual_links, dc);
break;
case DCE_VERSION_6_4:
res_pool = dce64_create_resource_pool(
init_data->num_virtual_links, dc);
break;
#endif
case DCE_VERSION_8_0:
res_pool = dce80_create_resource_pool(
init_data->num_virtual_links, dc);
break;
case DCE_VERSION_8_1:
res_pool = dce81_create_resource_pool(
init_data->num_virtual_links, dc);
break;
case DCE_VERSION_8_3:
res_pool = dce83_create_resource_pool(
init_data->num_virtual_links, dc);
break;
case DCE_VERSION_10_0:
res_pool = dce100_create_resource_pool(
init_data->num_virtual_links, dc);
break;
case DCE_VERSION_11_0:
res_pool = dce110_create_resource_pool(
init_data->num_virtual_links, dc,
init_data->asic_id);
break;
case DCE_VERSION_11_2:
case DCE_VERSION_11_22:
res_pool = dce112_create_resource_pool(
init_data->num_virtual_links, dc);
break;
case DCE_VERSION_12_0:
case DCE_VERSION_12_1:
res_pool = dce120_create_resource_pool(
init_data->num_virtual_links, dc);
break;
#if defined(CONFIG_DRM_AMD_DC_DCN)
case DCN_VERSION_1_0:
case DCN_VERSION_1_01:
res_pool = dcn10_create_resource_pool(init_data, dc);
break;
case DCN_VERSION_2_0:
res_pool = dcn20_create_resource_pool(init_data, dc);
break;
case DCN_VERSION_2_1:
res_pool = dcn21_create_resource_pool(init_data, dc);
break;
#endif
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
case DCN_VERSION_3_0:
res_pool = dcn30_create_resource_pool(init_data, dc);
break;
#endif
default:
break;
}
if (res_pool != NULL) {
if (dc->ctx->dc_bios->fw_info_valid) {
res_pool->ref_clocks.xtalin_clock_inKhz =
dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
/* initialize with firmware data first, no all
* ASIC have DCCG SW component. FPGA or
* simulation need initialization of
* dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
* with xtalin_clock_inKhz
*/
res_pool->ref_clocks.dccg_ref_clock_inKhz =
res_pool->ref_clocks.xtalin_clock_inKhz;
res_pool->ref_clocks.dchub_ref_clock_inKhz =
res_pool->ref_clocks.xtalin_clock_inKhz;
} else
ASSERT_CRITICAL(false);
}
return res_pool;
}
void dc_destroy_resource_pool(struct dc *dc)
{
if (dc) {
if (dc->res_pool)
dc->res_pool->funcs->destroy(&dc->res_pool);
kfree(dc->hwseq);
}
}
static void update_num_audio(
const struct resource_straps *straps,
unsigned int *num_audio,
struct audio_support *aud_support)
{
aud_support->dp_audio = true;
aud_support->hdmi_audio_native = false;
aud_support->hdmi_audio_on_dongle = false;
if (straps->hdmi_disable == 0) {
if (straps->dc_pinstraps_audio & 0x2) {
aud_support->hdmi_audio_on_dongle = true;
aud_support->hdmi_audio_native = true;
}
}
switch (straps->audio_stream_number) {
case 0: /* multi streams supported */
break;
case 1: /* multi streams not supported */
*num_audio = 1;
break;
default:
DC_ERR("DC: unexpected audio fuse!\n");
}
}
bool resource_construct(
unsigned int num_virtual_links,
struct dc *dc,
struct resource_pool *pool,
const struct resource_create_funcs *create_funcs)
{
struct dc_context *ctx = dc->ctx;
const struct resource_caps *caps = pool->res_cap;
int i;
unsigned int num_audio = caps->num_audio;
struct resource_straps straps = {0};
if (create_funcs->read_dce_straps)
create_funcs->read_dce_straps(dc->ctx, &straps);
pool->audio_count = 0;
if (create_funcs->create_audio) {
/* find the total number of streams available via the
* AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
* registers (one for each pin) starting from pin 1
* up to the max number of audio pins.
* We stop on the first pin where
* PORT_CONNECTIVITY == 1 (as instructed by HW team).
*/
update_num_audio(&straps, &num_audio, &pool->audio_support);
for (i = 0; i < caps->num_audio; i++) {
struct audio *aud = create_funcs->create_audio(ctx, i);
if (aud == NULL) {
DC_ERR("DC: failed to create audio!\n");
return false;
}
if (!aud->funcs->endpoint_valid(aud)) {
aud->funcs->destroy(&aud);
break;
}
pool->audios[i] = aud;
pool->audio_count++;
}
}
pool->stream_enc_count = 0;
if (create_funcs->create_stream_encoder) {
for (i = 0; i < caps->num_stream_encoder; i++) {
pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
if (pool->stream_enc[i] == NULL)
DC_ERR("DC: failed to create stream_encoder!\n");
pool->stream_enc_count++;
}
}
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
for (i = 0; i < caps->num_mpc_3dlut; i++) {
pool->mpc_lut[i] = dc_create_3dlut_func();
if (pool->mpc_lut[i] == NULL)
DC_ERR("DC: failed to create MPC 3dlut!\n");
pool->mpc_shaper[i] = dc_create_transfer_func();
if (pool->mpc_shaper[i] == NULL)
DC_ERR("DC: failed to create MPC shaper!\n");
}
#endif
dc->caps.dynamic_audio = false;
if (pool->audio_count < pool->stream_enc_count) {
dc->caps.dynamic_audio = true;
}
for (i = 0; i < num_virtual_links; i++) {
pool->stream_enc[pool->stream_enc_count] =
virtual_stream_encoder_create(
ctx, ctx->dc_bios);
if (pool->stream_enc[pool->stream_enc_count] == NULL) {
DC_ERR("DC: failed to create stream_encoder!\n");
return false;
}
pool->stream_enc_count++;
}
dc->hwseq = create_funcs->create_hwseq(ctx);
return true;
}
static int find_matching_clock_source(
const struct resource_pool *pool,
struct clock_source *clock_source)
{
int i;
for (i = 0; i < pool->clk_src_count; i++) {
if (pool->clock_sources[i] == clock_source)
return i;
}
return -1;
}
void resource_unreference_clock_source(
struct resource_context *res_ctx,
const struct resource_pool *pool,
struct clock_source *clock_source)
{
int i = find_matching_clock_source(pool, clock_source);
if (i > -1)
res_ctx->clock_source_ref_count[i]--;
if (pool->dp_clock_source == clock_source)
res_ctx->dp_clock_source_ref_count--;
}
void resource_reference_clock_source(
struct resource_context *res_ctx,
const struct resource_pool *pool,
struct clock_source *clock_source)
{
int i = find_matching_clock_source(pool, clock_source);
if (i > -1)
res_ctx->clock_source_ref_count[i]++;
if (pool->dp_clock_source == clock_source)
res_ctx->dp_clock_source_ref_count++;
}
int resource_get_clock_source_reference(
struct resource_context *res_ctx,
const struct resource_pool *pool,
struct clock_source *clock_source)
{
int i = find_matching_clock_source(pool, clock_source);
if (i > -1)
return res_ctx->clock_source_ref_count[i];
if (pool->dp_clock_source == clock_source)
return res_ctx->dp_clock_source_ref_count;
return -1;
}
bool resource_are_streams_timing_synchronizable(
struct dc_stream_state *stream1,
struct dc_stream_state *stream2)
{
if (stream1->timing.h_total != stream2->timing.h_total)
return false;
if (stream1->timing.v_total != stream2->timing.v_total)
return false;
if (stream1->timing.h_addressable
!= stream2->timing.h_addressable)
return false;
if (stream1->timing.v_addressable
!= stream2->timing.v_addressable)
return false;
if (stream1->timing.v_front_porch
!= stream2->timing.v_front_porch)
return false;
if (stream1->timing.pix_clk_100hz
!= stream2->timing.pix_clk_100hz)
return false;
if (stream1->clamping.c_depth != stream2->clamping.c_depth)
return false;
if (stream1->phy_pix_clk != stream2->phy_pix_clk
&& (!dc_is_dp_signal(stream1->signal)
|| !dc_is_dp_signal(stream2->signal)))
return false;
if (stream1->view_format != stream2->view_format)
return false;
if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
return false;
return true;
}
static bool is_dp_and_hdmi_sharable(
struct dc_stream_state *stream1,
struct dc_stream_state *stream2)
{
if (stream1->ctx->dc->caps.disable_dp_clk_share)
return false;
if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
stream2->clamping.c_depth != COLOR_DEPTH_888)
return false;
return true;
}
static bool is_sharable_clk_src(
const struct pipe_ctx *pipe_with_clk_src,
const struct pipe_ctx *pipe)
{
if (pipe_with_clk_src->clock_source == NULL)
return false;
if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
return false;
if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
(dc_is_dp_signal(pipe->stream->signal) &&
!is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
pipe->stream)))
return false;
if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
&& dc_is_dual_link_signal(pipe->stream->signal))
return false;
if (dc_is_hdmi_signal(pipe->stream->signal)
&& dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
return false;
if (!resource_are_streams_timing_synchronizable(
pipe_with_clk_src->stream, pipe->stream))
return false;
return true;
}
struct clock_source *resource_find_used_clk_src_for_sharing(
struct resource_context *res_ctx,
struct pipe_ctx *pipe_ctx)
{
int i;
for (i = 0; i < MAX_PIPES; i++) {
if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
return res_ctx->pipe_ctx[i].clock_source;
}
return NULL;
}
static enum pixel_format convert_pixel_format_to_dalsurface(
enum surface_pixel_format surface_pixel_format)
{
enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
switch (surface_pixel_format) {
case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
dal_pixel_format = PIXEL_FORMAT_INDEX8;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
dal_pixel_format = PIXEL_FORMAT_RGB565;
break;
case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
dal_pixel_format = PIXEL_FORMAT_RGB565;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
dal_pixel_format = PIXEL_FORMAT_ARGB8888;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
dal_pixel_format = PIXEL_FORMAT_ARGB8888;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
dal_pixel_format = PIXEL_FORMAT_FP16;
break;
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
dal_pixel_format = PIXEL_FORMAT_420BPP8;
break;
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
dal_pixel_format = PIXEL_FORMAT_420BPP10;
break;
case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
default:
dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
break;
}
return dal_pixel_format;
}
static inline void get_vp_scan_direction(
enum dc_rotation_angle rotation,
bool horizontal_mirror,
bool *orthogonal_rotation,
bool *flip_vert_scan_dir,
bool *flip_horz_scan_dir)
{
*orthogonal_rotation = false;
*flip_vert_scan_dir = false;
*flip_horz_scan_dir = false;
if (rotation == ROTATION_ANGLE_180) {
*flip_vert_scan_dir = true;
*flip_horz_scan_dir = true;
} else if (rotation == ROTATION_ANGLE_90) {
*orthogonal_rotation = true;
*flip_horz_scan_dir = true;
} else if (rotation == ROTATION_ANGLE_270) {
*orthogonal_rotation = true;
*flip_vert_scan_dir = true;
}
if (horizontal_mirror)
*flip_horz_scan_dir = !*flip_horz_scan_dir;
}
int get_num_mpc_splits(struct pipe_ctx *pipe)
{
int mpc_split_count = 0;
struct pipe_ctx *other_pipe = pipe->bottom_pipe;
while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
mpc_split_count++;
other_pipe = other_pipe->bottom_pipe;
}
other_pipe = pipe->top_pipe;
while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
mpc_split_count++;
other_pipe = other_pipe->top_pipe;
}
return mpc_split_count;
}
int get_num_odm_splits(struct pipe_ctx *pipe)
{
int odm_split_count = 0;
struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
while (next_pipe) {
odm_split_count++;
next_pipe = next_pipe->next_odm_pipe;
}
pipe = pipe->prev_odm_pipe;
while (pipe) {
odm_split_count++;
pipe = pipe->prev_odm_pipe;
}
return odm_split_count;
}
static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int *split_count, int *split_idx)
{
*split_count = get_num_odm_splits(pipe_ctx);
*split_idx = 0;
if (*split_count == 0) {
/*Check for mpc split*/
struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
*split_count = get_num_mpc_splits(pipe_ctx);
while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
(*split_idx)++;
split_pipe = split_pipe->top_pipe;
}
} else {
/*Get odm split index*/
struct pipe_ctx *split_pipe = pipe_ctx->prev_odm_pipe;
while (split_pipe) {
(*split_idx)++;
split_pipe = split_pipe->prev_odm_pipe;
}
}
}
static void calculate_viewport(struct pipe_ctx *pipe_ctx)
{
const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
const struct dc_stream_state *stream = pipe_ctx->stream;
struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
struct rect surf_src = plane_state->src_rect;
struct rect clip, dest;
int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
|| data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
int split_count = 0;
int split_idx = 0;
bool orthogonal_rotation, flip_y_start, flip_x_start;
calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE ||
stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
split_count = 0;
split_idx = 0;
}
/* The actual clip is an intersection between stream
* source and surface clip
*/
dest = plane_state->dst_rect;
clip.x = stream->src.x > plane_state->clip_rect.x ?
stream->src.x : plane_state->clip_rect.x;
clip.width = stream->src.x + stream->src.width <
plane_state->clip_rect.x + plane_state->clip_rect.width ?
stream->src.x + stream->src.width - clip.x :
plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ;
clip.y = stream->src.y > plane_state->clip_rect.y ?
stream->src.y : plane_state->clip_rect.y;
clip.height = stream->src.y + stream->src.height <
plane_state->clip_rect.y + plane_state->clip_rect.height ?
stream->src.y + stream->src.height - clip.y :
plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ;
/*
* Need to calculate how scan origin is shifted in vp space
* to correctly rotate clip and dst
*/
get_vp_scan_direction(
plane_state->rotation,
plane_state->horizontal_mirror,
&orthogonal_rotation,
&flip_y_start,
&flip_x_start);
if (orthogonal_rotation) {
swap(clip.x, clip.y);
swap(clip.width, clip.height);
swap(dest.x, dest.y);
swap(dest.width, dest.height);
}
if (flip_x_start) {
clip.x = dest.x + dest.width - clip.x - clip.width;
dest.x = 0;
}
if (flip_y_start) {
clip.y = dest.y + dest.height - clip.y - clip.height;
dest.y = 0;
}
/* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio
* num_pixels = clip.num_pix * scl_ratio
*/
data->viewport.x = surf_src.x + (clip.x - dest.x) * surf_src.width / dest.width;
data->viewport.width = clip.width * surf_src.width / dest.width;
data->viewport.y = surf_src.y + (clip.y - dest.y) * surf_src.height / dest.height;
data->viewport.height = clip.height * surf_src.height / dest.height;
/* Handle split */
if (split_count) {
/* extra pixels in the division remainder need to go to pipes after
* the extra pixel index minus one(epimo) defined here as:
*/
int epimo = 0;
if (orthogonal_rotation) {
if (flip_y_start)
split_idx = split_count - split_idx;
epimo = split_count - data->viewport.height % (split_count + 1);
data->viewport.y += (data->viewport.height / (split_count + 1)) * split_idx;
if (split_idx > epimo)
data->viewport.y += split_idx - epimo - 1;
data->viewport.height = data->viewport.height / (split_count + 1) + (split_idx > epimo ? 1 : 0);
} else {
if (flip_x_start)
split_idx = split_count - split_idx;
epimo = split_count - data->viewport.width % (split_count + 1);
data->viewport.x += (data->viewport.width / (split_count + 1)) * split_idx;
if (split_idx > epimo)
data->viewport.x += split_idx - epimo - 1;
data->viewport.width = data->viewport.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
}
}
/* Round down, compensate in init */
data->viewport_c.x = data->viewport.x / vpc_div;
data->viewport_c.y = data->viewport.y / vpc_div;
data->inits.h_c = (data->viewport.x % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
data->inits.v_c = (data->viewport.y % vpc_div) != 0 ? dc_fixpt_half : dc_fixpt_zero;
/* Round up, assume original video size always even dimensions */
data->viewport_c.width = (data->viewport.width + vpc_div - 1) / vpc_div;
data->viewport_c.height = (data->viewport.height + vpc_div - 1) / vpc_div;
data->viewport_unadjusted = data->viewport;
data->viewport_c_unadjusted = data->viewport_c;
}
static void calculate_recout(struct pipe_ctx *pipe_ctx)
{
const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
const struct dc_stream_state *stream = pipe_ctx->stream;
struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
struct rect surf_clip = plane_state->clip_rect;
bool pri_split_tb = pipe_ctx->bottom_pipe &&
pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state &&
stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
bool sec_split_tb = pipe_ctx->top_pipe &&
pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state &&
stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM;
int split_count = 0;
int split_idx = 0;
calculate_split_count_and_index(pipe_ctx, &split_count, &split_idx);
/*
* Only the leftmost ODM pipe should be offset by a nonzero distance
*/
if (!pipe_ctx->prev_odm_pipe) {
data->recout.x = stream->dst.x;
if (stream->src.x < surf_clip.x)
data->recout.x += (surf_clip.x - stream->src.x) * stream->dst.width
/ stream->src.width;
} else
data->recout.x = 0;
data->recout.width = surf_clip.width * stream->dst.width / stream->src.width;
if (data->recout.width + data->recout.x > stream->dst.x + stream->dst.width)
data->recout.width = stream->dst.x + stream->dst.width - data->recout.x;
data->recout.y = stream->dst.y;
if (stream->src.y < surf_clip.y)
data->recout.y += (surf_clip.y - stream->src.y) * stream->dst.height
/ stream->src.height;
data->recout.height = surf_clip.height * stream->dst.height / stream->src.height;
if (data->recout.height + data->recout.y > stream->dst.y + stream->dst.height)
data->recout.height = stream->dst.y + stream->dst.height - data->recout.y;
/* Handle h & v split, handle rotation using viewport */
if (sec_split_tb) {
data->recout.y += data->recout.height / 2;
/* Floor primary pipe, ceil 2ndary pipe */
data->recout.height = (data->recout.height + 1) / 2;
} else if (pri_split_tb)
data->recout.height /= 2;
else if (split_count) {
/* extra pixels in the division remainder need to go to pipes after
* the extra pixel index minus one(epimo) defined here as:
*/
int epimo = split_count - data->recout.width % (split_count + 1);
/*no recout offset due to odm */
if (!pipe_ctx->next_odm_pipe && !pipe_ctx->prev_odm_pipe) {
data->recout.x += (data->recout.width / (split_count + 1)) * split_idx;
if (split_idx > epimo)
data->recout.x += split_idx - epimo - 1;
}
data->recout.width = data->recout.width / (split_count + 1) + (split_idx > epimo ? 1 : 0);
}
}
static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
{
const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
const struct dc_stream_state *stream = pipe_ctx->stream;
struct rect surf_src = plane_state->src_rect;
const int in_w = stream->src.width;
const int in_h = stream->src.height;
const int out_w = stream->dst.width;
const int out_h = stream->dst.height;
/*Swap surf_src height and width since scaling ratios are in recout rotation*/
if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
swap(surf_src.height, surf_src.width);
pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
surf_src.width,
plane_state->dst_rect.width);
pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
surf_src.height,
plane_state->dst_rect.height);
if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
|| pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
}
pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
pipe_ctx->plane_res.scl_data.ratios.horz, 19);
pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
pipe_ctx->plane_res.scl_data.ratios.vert, 19);
pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
}
static inline void adjust_vp_and_init_for_seamless_clip(
bool flip_scan_dir,
int recout_skip,
int src_size,
int taps,
struct fixed31_32 ratio,
struct fixed31_32 *init,
int *vp_offset,
int *vp_size)
{
if (!flip_scan_dir) {
/* Adjust for viewport end clip-off */
if ((*vp_offset + *vp_size) < src_size) {
int vp_clip = src_size - *vp_size - *vp_offset;
int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
int_part = int_part > 0 ? int_part : 0;
*vp_size += int_part < vp_clip ? int_part : vp_clip;
}
/* Adjust for non-0 viewport offset */
if (*vp_offset) {
int int_part;
*init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
int_part = dc_fixpt_floor(*init) - *vp_offset;
if (int_part < taps) {
int int_adj = *vp_offset >= (taps - int_part) ?
(taps - int_part) : *vp_offset;
*vp_offset -= int_adj;
*vp_size += int_adj;
int_part += int_adj;
} else if (int_part > taps) {
*vp_offset += int_part - taps;
*vp_size -= int_part - taps;
int_part = taps;
}
init->value &= 0xffffffff;
*init = dc_fixpt_add_int(*init, int_part);
}
} else {
/* Adjust for non-0 viewport offset */
if (*vp_offset) {
int int_part = dc_fixpt_floor(dc_fixpt_sub(*init, ratio));
int_part = int_part > 0 ? int_part : 0;
*vp_size += int_part < *vp_offset ? int_part : *vp_offset;
*vp_offset -= int_part < *vp_offset ? int_part : *vp_offset;
}
/* Adjust for viewport end clip-off */
if ((*vp_offset + *vp_size) < src_size) {
int int_part;
int end_offset = src_size - *vp_offset - *vp_size;
/*
* this is init if vp had no offset, keep in mind this is from the
* right side of vp due to scan direction
*/
*init = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_skip));
/*
* this is the difference between first pixel of viewport available to read
* and init position, takning into account scan direction
*/
int_part = dc_fixpt_floor(*init) - end_offset;
if (int_part < taps) {
int int_adj = end_offset >= (taps - int_part) ?
(taps - int_part) : end_offset;
*vp_size += int_adj;
int_part += int_adj;
} else if (int_part > taps) {
*vp_size += int_part - taps;
int_part = taps;
}
init->value &= 0xffffffff;
*init = dc_fixpt_add_int(*init, int_part);
}
}
}
static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx)
{
const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
const struct dc_stream_state *stream = pipe_ctx->stream;
struct pipe_ctx *odm_pipe = pipe_ctx;
struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
struct rect src = pipe_ctx->plane_state->src_rect;
int recout_skip_h, recout_skip_v, surf_size_h, surf_size_v;
int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
|| data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
int odm_idx = 0;
/*
* Need to calculate the scan direction for viewport to make adjustments
*/
get_vp_scan_direction(
plane_state->rotation,
plane_state->horizontal_mirror,
&orthogonal_rotation,
&flip_vert_scan_dir,
&flip_horz_scan_dir);
/* Calculate src rect rotation adjusted to recout space */
surf_size_h = src.x + src.width;
surf_size_v = src.y + src.height;
if (flip_horz_scan_dir)
src.x = 0;
if (flip_vert_scan_dir)
src.y = 0;
if (orthogonal_rotation) {
swap(src.x, src.y);
swap(src.width, src.height);
}
/*modified recout_skip_h calculation due to odm having no recout offset*/