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dc.c
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dc.c
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Avionic Design GmbH
* Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
*/
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
#include <linux/iommu.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <soc/tegra/pmc.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_debugfs.h>
#include <drm/drm_fourcc.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_vblank.h>
#include "dc.h"
#include "drm.h"
#include "gem.h"
#include "hub.h"
#include "plane.h"
static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
struct drm_crtc_state *state);
static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
{
stats->frames = 0;
stats->vblank = 0;
stats->underflow = 0;
stats->overflow = 0;
}
/* Reads the active copy of a register. */
static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
{
u32 value;
tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
value = tegra_dc_readl(dc, offset);
tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
return value;
}
static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
unsigned int offset)
{
if (offset >= 0x500 && offset <= 0x638) {
offset = 0x000 + (offset - 0x500);
return plane->offset + offset;
}
if (offset >= 0x700 && offset <= 0x719) {
offset = 0x180 + (offset - 0x700);
return plane->offset + offset;
}
if (offset >= 0x800 && offset <= 0x839) {
offset = 0x1c0 + (offset - 0x800);
return plane->offset + offset;
}
dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
return plane->offset + offset;
}
static inline u32 tegra_plane_readl(struct tegra_plane *plane,
unsigned int offset)
{
return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
}
static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
unsigned int offset)
{
tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
}
bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
{
struct device_node *np = dc->dev->of_node;
struct of_phandle_iterator it;
int err;
of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
if (it.node == dev->of_node)
return true;
return false;
}
/*
* Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
* *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
* Latching happens mmediately if the display controller is in STOP mode or
* on the next frame boundary otherwise.
*
* Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
* ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
* are written. When the *_ACT_REQ bits are written, the ARM copy is latched
* into the ACTIVE copy, either immediately if the display controller is in
* STOP mode, or at the next frame boundary otherwise.
*/
void tegra_dc_commit(struct tegra_dc *dc)
{
tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
}
static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
unsigned int bpp)
{
fixed20_12 outf = dfixed_init(out);
fixed20_12 inf = dfixed_init(in);
u32 dda_inc;
int max;
if (v)
max = 15;
else {
switch (bpp) {
case 2:
max = 8;
break;
default:
WARN_ON_ONCE(1);
/* fallthrough */
case 4:
max = 4;
break;
}
}
outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
inf.full -= dfixed_const(1);
dda_inc = dfixed_div(inf, outf);
dda_inc = min_t(u32, dda_inc, dfixed_const(max));
return dda_inc;
}
static inline u32 compute_initial_dda(unsigned int in)
{
fixed20_12 inf = dfixed_init(in);
return dfixed_frac(inf);
}
static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane)
{
u32 background[3] = {
BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE,
};
u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) |
BLEND_COLOR_KEY_NONE;
u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255);
struct tegra_plane_state *state;
u32 blending[2];
unsigned int i;
/* disable blending for non-overlapping case */
tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY);
tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN);
state = to_tegra_plane_state(plane->base.state);
if (state->opaque) {
/*
* Since custom fix-weight blending isn't utilized and weight
* of top window is set to max, we can enforce dependent
* blending which in this case results in transparent bottom
* window if top window is opaque and if top window enables
* alpha blending, then bottom window is getting alpha value
* of 1 minus the sum of alpha components of the overlapping
* plane.
*/
background[0] |= BLEND_CONTROL_DEPENDENT;
background[1] |= BLEND_CONTROL_DEPENDENT;
/*
* The region where three windows overlap is the intersection
* of the two regions where two windows overlap. It contributes
* to the area if all of the windows on top of it have an alpha
* component.
*/
switch (state->base.normalized_zpos) {
case 0:
if (state->blending[0].alpha &&
state->blending[1].alpha)
background[2] |= BLEND_CONTROL_DEPENDENT;
break;
case 1:
background[2] |= BLEND_CONTROL_DEPENDENT;
break;
}
} else {
/*
* Enable alpha blending if pixel format has an alpha
* component.
*/
foreground |= BLEND_CONTROL_ALPHA;
/*
* If any of the windows on top of this window is opaque, it
* will completely conceal this window within that area. If
* top window has an alpha component, it is blended over the
* bottom window.
*/
for (i = 0; i < 2; i++) {
if (state->blending[i].alpha &&
state->blending[i].top)
background[i] |= BLEND_CONTROL_DEPENDENT;
}
switch (state->base.normalized_zpos) {
case 0:
if (state->blending[0].alpha &&
state->blending[1].alpha)
background[2] |= BLEND_CONTROL_DEPENDENT;
break;
case 1:
/*
* When both middle and topmost windows have an alpha,
* these windows a mixed together and then the result
* is blended over the bottom window.
*/
if (state->blending[0].alpha &&
state->blending[0].top)
background[2] |= BLEND_CONTROL_ALPHA;
if (state->blending[1].alpha &&
state->blending[1].top)
background[2] |= BLEND_CONTROL_ALPHA;
break;
}
}
switch (state->base.normalized_zpos) {
case 0:
tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X);
tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y);
tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
break;
case 1:
/*
* If window B / C is topmost, then X / Y registers are
* matching the order of blending[...] state indices,
* otherwise a swap is required.
*/
if (!state->blending[0].top && state->blending[1].top) {
blending[0] = foreground;
blending[1] = background[1];
} else {
blending[0] = background[0];
blending[1] = foreground;
}
tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X);
tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y);
tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY);
break;
case 2:
tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X);
tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y);
tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY);
break;
}
}
static void tegra_plane_setup_blending(struct tegra_plane *plane,
const struct tegra_dc_window *window)
{
u32 value;
value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT);
value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 |
BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC |
BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC;
tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT);
value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL);
}
static bool
tegra_plane_use_horizontal_filtering(struct tegra_plane *plane,
const struct tegra_dc_window *window)
{
struct tegra_dc *dc = plane->dc;
if (window->src.w == window->dst.w)
return false;
if (plane->index == 0 && dc->soc->has_win_a_without_filters)
return false;
return true;
}
static bool
tegra_plane_use_vertical_filtering(struct tegra_plane *plane,
const struct tegra_dc_window *window)
{
struct tegra_dc *dc = plane->dc;
if (window->src.h == window->dst.h)
return false;
if (plane->index == 0 && dc->soc->has_win_a_without_filters)
return false;
if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter)
return false;
return true;
}
static void tegra_dc_setup_window(struct tegra_plane *plane,
const struct tegra_dc_window *window)
{
unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
struct tegra_dc *dc = plane->dc;
bool yuv, planar;
u32 value;
/*
* For YUV planar modes, the number of bytes per pixel takes into
* account only the luma component and therefore is 1.
*/
yuv = tegra_plane_format_is_yuv(window->format, &planar);
if (!yuv)
bpp = window->bits_per_pixel / 8;
else
bpp = planar ? 1 : 2;
tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
tegra_plane_writel(plane, value, DC_WIN_POSITION);
value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
tegra_plane_writel(plane, value, DC_WIN_SIZE);
h_offset = window->src.x * bpp;
v_offset = window->src.y;
h_size = window->src.w * bpp;
v_size = window->src.h;
value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
/*
* For DDA computations the number of bytes per pixel for YUV planar
* modes needs to take into account all Y, U and V components.
*/
if (yuv && planar)
bpp = 2;
h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
h_dda = compute_initial_dda(window->src.x);
v_dda = compute_initial_dda(window->src.y);
tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
if (yuv && planar) {
tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
value = window->stride[1] << 16 | window->stride[0];
tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
} else {
tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
}
if (window->bottom_up)
v_offset += window->src.h - 1;
tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
if (dc->soc->supports_block_linear) {
unsigned long height = window->tiling.value;
switch (window->tiling.mode) {
case TEGRA_BO_TILING_MODE_PITCH:
value = DC_WINBUF_SURFACE_KIND_PITCH;
break;
case TEGRA_BO_TILING_MODE_TILED:
value = DC_WINBUF_SURFACE_KIND_TILED;
break;
case TEGRA_BO_TILING_MODE_BLOCK:
value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
DC_WINBUF_SURFACE_KIND_BLOCK;
break;
}
tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
} else {
switch (window->tiling.mode) {
case TEGRA_BO_TILING_MODE_PITCH:
value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
DC_WIN_BUFFER_ADDR_MODE_LINEAR;
break;
case TEGRA_BO_TILING_MODE_TILED:
value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
DC_WIN_BUFFER_ADDR_MODE_TILE;
break;
case TEGRA_BO_TILING_MODE_BLOCK:
/*
* No need to handle this here because ->atomic_check
* will already have filtered it out.
*/
break;
}
tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
}
value = WIN_ENABLE;
if (yuv) {
/* setup default colorspace conversion coefficients */
tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
value |= CSC_ENABLE;
} else if (window->bits_per_pixel < 24) {
value |= COLOR_EXPAND;
}
if (window->bottom_up)
value |= V_DIRECTION;
if (tegra_plane_use_horizontal_filtering(plane, window)) {
/*
* Enable horizontal 6-tap filter and set filtering
* coefficients to the default values defined in TRM.
*/
tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0));
tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1));
tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2));
tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3));
tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4));
tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5));
tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6));
tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7));
tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8));
tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9));
tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10));
tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11));
tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12));
tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13));
tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14));
tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15));
value |= H_FILTER;
}
if (tegra_plane_use_vertical_filtering(plane, window)) {
unsigned int i, k;
/*
* Enable vertical 2-tap filter and set filtering
* coefficients to the default values defined in TRM.
*/
for (i = 0, k = 128; i < 16; i++, k -= 8)
tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i));
value |= V_FILTER;
}
tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
if (dc->soc->has_legacy_blending)
tegra_plane_setup_blending_legacy(plane);
else
tegra_plane_setup_blending(plane, window);
}
static const u32 tegra20_primary_formats[] = {
DRM_FORMAT_ARGB4444,
DRM_FORMAT_ARGB1555,
DRM_FORMAT_RGB565,
DRM_FORMAT_RGBA5551,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_ARGB8888,
/* non-native formats */
DRM_FORMAT_XRGB1555,
DRM_FORMAT_RGBX5551,
DRM_FORMAT_XBGR8888,
DRM_FORMAT_XRGB8888,
};
static const u64 tegra20_modifiers[] = {
DRM_FORMAT_MOD_LINEAR,
DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED,
DRM_FORMAT_MOD_INVALID
};
static const u32 tegra114_primary_formats[] = {
DRM_FORMAT_ARGB4444,
DRM_FORMAT_ARGB1555,
DRM_FORMAT_RGB565,
DRM_FORMAT_RGBA5551,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_ARGB8888,
/* new on Tegra114 */
DRM_FORMAT_ABGR4444,
DRM_FORMAT_ABGR1555,
DRM_FORMAT_BGRA5551,
DRM_FORMAT_XRGB1555,
DRM_FORMAT_RGBX5551,
DRM_FORMAT_XBGR1555,
DRM_FORMAT_BGRX5551,
DRM_FORMAT_BGR565,
DRM_FORMAT_BGRA8888,
DRM_FORMAT_RGBA8888,
DRM_FORMAT_XRGB8888,
DRM_FORMAT_XBGR8888,
};
static const u32 tegra124_primary_formats[] = {
DRM_FORMAT_ARGB4444,
DRM_FORMAT_ARGB1555,
DRM_FORMAT_RGB565,
DRM_FORMAT_RGBA5551,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_ARGB8888,
/* new on Tegra114 */
DRM_FORMAT_ABGR4444,
DRM_FORMAT_ABGR1555,
DRM_FORMAT_BGRA5551,
DRM_FORMAT_XRGB1555,
DRM_FORMAT_RGBX5551,
DRM_FORMAT_XBGR1555,
DRM_FORMAT_BGRX5551,
DRM_FORMAT_BGR565,
DRM_FORMAT_BGRA8888,
DRM_FORMAT_RGBA8888,
DRM_FORMAT_XRGB8888,
DRM_FORMAT_XBGR8888,
/* new on Tegra124 */
DRM_FORMAT_RGBX8888,
DRM_FORMAT_BGRX8888,
};
static const u64 tegra124_modifiers[] = {
DRM_FORMAT_MOD_LINEAR,
DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0),
DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1),
DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2),
DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3),
DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4),
DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5),
DRM_FORMAT_MOD_INVALID
};
static int tegra_plane_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
unsigned int rotation = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_Y;
struct tegra_bo_tiling *tiling = &plane_state->tiling;
struct tegra_plane *tegra = to_tegra_plane(plane);
struct tegra_dc *dc = to_tegra_dc(state->crtc);
int err;
/* no need for further checks if the plane is being disabled */
if (!state->crtc)
return 0;
err = tegra_plane_format(state->fb->format->format,
&plane_state->format,
&plane_state->swap);
if (err < 0)
return err;
/*
* Tegra20 and Tegra30 are special cases here because they support
* only variants of specific formats with an alpha component, but not
* the corresponding opaque formats. However, the opaque formats can
* be emulated by disabling alpha blending for the plane.
*/
if (dc->soc->has_legacy_blending) {
err = tegra_plane_setup_legacy_state(tegra, plane_state);
if (err < 0)
return err;
}
err = tegra_fb_get_tiling(state->fb, tiling);
if (err < 0)
return err;
if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
!dc->soc->supports_block_linear) {
DRM_ERROR("hardware doesn't support block linear mode\n");
return -EINVAL;
}
rotation = drm_rotation_simplify(state->rotation, rotation);
if (rotation & DRM_MODE_REFLECT_Y)
plane_state->bottom_up = true;
else
plane_state->bottom_up = false;
/*
* Tegra doesn't support different strides for U and V planes so we
* error out if the user tries to display a framebuffer with such a
* configuration.
*/
if (state->fb->format->num_planes > 2) {
if (state->fb->pitches[2] != state->fb->pitches[1]) {
DRM_ERROR("unsupported UV-plane configuration\n");
return -EINVAL;
}
}
err = tegra_plane_state_add(tegra, state);
if (err < 0)
return err;
return 0;
}
static void tegra_plane_atomic_disable(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct tegra_plane *p = to_tegra_plane(plane);
u32 value;
/* rien ne va plus */
if (!old_state || !old_state->crtc)
return;
value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
value &= ~WIN_ENABLE;
tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
}
static void tegra_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
struct drm_framebuffer *fb = plane->state->fb;
struct tegra_plane *p = to_tegra_plane(plane);
struct tegra_dc_window window;
unsigned int i;
/* rien ne va plus */
if (!plane->state->crtc || !plane->state->fb)
return;
if (!plane->state->visible)
return tegra_plane_atomic_disable(plane, old_state);
memset(&window, 0, sizeof(window));
window.src.x = plane->state->src.x1 >> 16;
window.src.y = plane->state->src.y1 >> 16;
window.src.w = drm_rect_width(&plane->state->src) >> 16;
window.src.h = drm_rect_height(&plane->state->src) >> 16;
window.dst.x = plane->state->dst.x1;
window.dst.y = plane->state->dst.y1;
window.dst.w = drm_rect_width(&plane->state->dst);
window.dst.h = drm_rect_height(&plane->state->dst);
window.bits_per_pixel = fb->format->cpp[0] * 8;
window.bottom_up = tegra_fb_is_bottom_up(fb) || state->bottom_up;
/* copy from state */
window.zpos = plane->state->normalized_zpos;
window.tiling = state->tiling;
window.format = state->format;
window.swap = state->swap;
for (i = 0; i < fb->format->num_planes; i++) {
window.base[i] = state->iova[i] + fb->offsets[i];
/*
* Tegra uses a shared stride for UV planes. Framebuffers are
* already checked for this in the tegra_plane_atomic_check()
* function, so it's safe to ignore the V-plane pitch here.
*/
if (i < 2)
window.stride[i] = fb->pitches[i];
}
tegra_dc_setup_window(p, &window);
}
static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
.prepare_fb = tegra_plane_prepare_fb,
.cleanup_fb = tegra_plane_cleanup_fb,
.atomic_check = tegra_plane_atomic_check,
.atomic_disable = tegra_plane_atomic_disable,
.atomic_update = tegra_plane_atomic_update,
};
static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm)
{
/*
* Ideally this would use drm_crtc_mask(), but that would require the
* CRTC to already be in the mode_config's list of CRTCs. However, it
* will only be added to that list in the drm_crtc_init_with_planes()
* (in tegra_dc_init()), which in turn requires registration of these
* planes. So we have ourselves a nice little chicken and egg problem
* here.
*
* We work around this by manually creating the mask from the number
* of CRTCs that have been registered, and should therefore always be
* the same as drm_crtc_index() after registration.
*/
return 1 << drm->mode_config.num_crtc;
}
static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
struct tegra_dc *dc)
{
unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
struct tegra_plane *plane;
unsigned int num_formats;
const u64 *modifiers;
const u32 *formats;
int err;
plane = kzalloc(sizeof(*plane), GFP_KERNEL);
if (!plane)
return ERR_PTR(-ENOMEM);
/* Always use window A as primary window */
plane->offset = 0xa00;
plane->index = 0;
plane->dc = dc;
num_formats = dc->soc->num_primary_formats;
formats = dc->soc->primary_formats;
modifiers = dc->soc->modifiers;
err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
&tegra_plane_funcs, formats,
num_formats, modifiers, type, NULL);
if (err < 0) {
kfree(plane);
return ERR_PTR(err);
}
drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255);
err = drm_plane_create_rotation_property(&plane->base,
DRM_MODE_ROTATE_0,
DRM_MODE_ROTATE_0 |
DRM_MODE_REFLECT_Y);
if (err < 0)
dev_err(dc->dev, "failed to create rotation property: %d\n",
err);
return &plane->base;
}
static const u32 tegra_cursor_plane_formats[] = {
DRM_FORMAT_RGBA8888,
};
static int tegra_cursor_atomic_check(struct drm_plane *plane,
struct drm_plane_state *state)
{
struct tegra_plane *tegra = to_tegra_plane(plane);
int err;
/* no need for further checks if the plane is being disabled */
if (!state->crtc)
return 0;
/* scaling not supported for cursor */
if ((state->src_w >> 16 != state->crtc_w) ||
(state->src_h >> 16 != state->crtc_h))
return -EINVAL;
/* only square cursors supported */
if (state->src_w != state->src_h)
return -EINVAL;
if (state->crtc_w != 32 && state->crtc_w != 64 &&
state->crtc_w != 128 && state->crtc_w != 256)
return -EINVAL;
err = tegra_plane_state_add(tegra, state);
if (err < 0)
return err;
return 0;
}
static void tegra_cursor_atomic_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
u32 value = CURSOR_CLIP_DISPLAY;
/* rien ne va plus */
if (!plane->state->crtc || !plane->state->fb)
return;
switch (plane->state->crtc_w) {
case 32:
value |= CURSOR_SIZE_32x32;
break;
case 64:
value |= CURSOR_SIZE_64x64;
break;
case 128:
value |= CURSOR_SIZE_128x128;
break;
case 256:
value |= CURSOR_SIZE_256x256;
break;
default:
WARN(1, "cursor size %ux%u not supported\n",
plane->state->crtc_w, plane->state->crtc_h);
return;
}
value |= (state->iova[0] >> 10) & 0x3fffff;
tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
value = (state->iova[0] >> 32) & 0x3;
tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
#endif
/* enable cursor and set blend mode */
value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
value |= CURSOR_ENABLE;
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
value &= ~CURSOR_DST_BLEND_MASK;
value &= ~CURSOR_SRC_BLEND_MASK;
value |= CURSOR_MODE_NORMAL;
value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
value |= CURSOR_ALPHA;
tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
/* position the cursor */
value = (plane->state->crtc_y & 0x3fff) << 16 |
(plane->state->crtc_x & 0x3fff);
tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
}
static void tegra_cursor_atomic_disable(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
struct tegra_dc *dc;
u32 value;
/* rien ne va plus */
if (!old_state || !old_state->crtc)
return;
dc = to_tegra_dc(old_state->crtc);
value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
value &= ~CURSOR_ENABLE;
tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
}
static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
.prepare_fb = tegra_plane_prepare_fb,
.cleanup_fb = tegra_plane_cleanup_fb,
.atomic_check = tegra_cursor_atomic_check,
.atomic_update = tegra_cursor_atomic_update,
.atomic_disable = tegra_cursor_atomic_disable,
};
static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
struct tegra_dc *dc)
{
unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm);
struct tegra_plane *plane;
unsigned int num_formats;
const u32 *formats;
int err;
plane = kzalloc(sizeof(*plane), GFP_KERNEL);
if (!plane)
return ERR_PTR(-ENOMEM);
/*
* This index is kind of fake. The cursor isn't a regular plane, but
* its update and activation request bits in DC_CMD_STATE_CONTROL do
* use the same programming. Setting this fake index here allows the
* code in tegra_add_plane_state() to do the right thing without the
* need to special-casing the cursor plane.
*/
plane->index = 6;
plane->dc = dc;
num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
formats = tegra_cursor_plane_formats;
err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
&tegra_plane_funcs, formats,
num_formats, NULL,
DRM_PLANE_TYPE_CURSOR, NULL);
if (err < 0) {
kfree(plane);
return ERR_PTR(err);
}
drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
drm_plane_create_zpos_immutable_property(&plane->base, 255);
return &plane->base;
}
static const u32 tegra20_overlay_formats[] = {
DRM_FORMAT_ARGB4444,
DRM_FORMAT_ARGB1555,
DRM_FORMAT_RGB565,
DRM_FORMAT_RGBA5551,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_ARGB8888,
/* non-native formats */
DRM_FORMAT_XRGB1555,
DRM_FORMAT_RGBX5551,
DRM_FORMAT_XBGR8888,
DRM_FORMAT_XRGB8888,
/* planar formats */
DRM_FORMAT_UYVY,
DRM_FORMAT_YUYV,
DRM_FORMAT_YUV420,
DRM_FORMAT_YUV422,
};
static const u32 tegra114_overlay_formats[] = {
DRM_FORMAT_ARGB4444,
DRM_FORMAT_ARGB1555,
DRM_FORMAT_RGB565,
DRM_FORMAT_RGBA5551,
DRM_FORMAT_ABGR8888,
DRM_FORMAT_ARGB8888,
/* new on Tegra114 */
DRM_FORMAT_ABGR4444,
DRM_FORMAT_ABGR1555,
DRM_FORMAT_BGRA5551,
DRM_FORMAT_XRGB1555,
DRM_FORMAT_RGBX5551,
DRM_FORMAT_XBGR1555,
DRM_FORMAT_BGRX5551,
DRM_FORMAT_BGR565,
DRM_FORMAT_BGRA8888,