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rockchip_drm_vop2.c
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rockchip_drm_vop2.c
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
* Author: Andy Yan <andy.yan@rock-chips.com>
*/
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/component.h>
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/swab.h>
#include <drm/drm.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_uapi.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_debugfs.h>
#include <drm/drm_flip_work.h>
#include <drm/drm_plane_helper.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_vblank.h>
#include <uapi/linux/videodev2.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rockchip_drm_drv.h"
#include "rockchip_drm_gem.h"
#include "rockchip_drm_fb.h"
#include "rockchip_drm_vop2.h"
/*
* VOP2 architecture
*
+----------+ +-------------+ +-----------+
| Cluster | | Sel 1 from 6| | 1 from 3 |
| window0 | | Layer0 | | RGB |
+----------+ +-------------+ +---------------+ +-------------+ +-----------+
+----------+ +-------------+ |N from 6 layers| | |
| Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+
| window1 | | Layer1 | | | | | | 1 from 3 |
+----------+ +-------------+ +---------------+ +-------------+ | LVDS |
+----------+ +-------------+ +-----------+
| Esmart | | Sel 1 from 6|
| window0 | | Layer2 | +---------------+ +-------------+ +-----------+
+----------+ +-------------+ |N from 6 Layers| | | +--> | 1 from 3 |
+----------+ +-------------+ --------> | Overlay1 +--->| Video Port1 | | MIPI |
| Esmart | | Sel 1 from 6| --------> | | | | +-----------+
| Window1 | | Layer3 | +---------------+ +-------------+
+----------+ +-------------+ +-----------+
+----------+ +-------------+ | 1 from 3 |
| Smart | | Sel 1 from 6| +---------------+ +-------------+ | HDMI |
| Window0 | | Layer4 | |N from 6 Layers| | | +-----------+
+----------+ +-------------+ | Overlay2 +--->| Video Port2 |
+----------+ +-------------+ | | | | +-----------+
| Smart | | Sel 1 from 6| +---------------+ +-------------+ | 1 from 3 |
| Window1 | | Layer5 | | eDP |
+----------+ +-------------+ +-----------+
*
*/
enum vop2_data_format {
VOP2_FMT_ARGB8888 = 0,
VOP2_FMT_RGB888,
VOP2_FMT_RGB565,
VOP2_FMT_XRGB101010,
VOP2_FMT_YUV420SP,
VOP2_FMT_YUV422SP,
VOP2_FMT_YUV444SP,
VOP2_FMT_YUYV422 = 8,
VOP2_FMT_YUYV420,
VOP2_FMT_VYUY422,
VOP2_FMT_VYUY420,
VOP2_FMT_YUV420SP_TILE_8x4 = 0x10,
VOP2_FMT_YUV420SP_TILE_16x2,
VOP2_FMT_YUV422SP_TILE_8x4,
VOP2_FMT_YUV422SP_TILE_16x2,
VOP2_FMT_YUV420SP_10,
VOP2_FMT_YUV422SP_10,
VOP2_FMT_YUV444SP_10,
};
enum vop2_afbc_format {
VOP2_AFBC_FMT_RGB565,
VOP2_AFBC_FMT_ARGB2101010 = 2,
VOP2_AFBC_FMT_YUV420_10BIT,
VOP2_AFBC_FMT_RGB888,
VOP2_AFBC_FMT_ARGB8888,
VOP2_AFBC_FMT_YUV420 = 9,
VOP2_AFBC_FMT_YUV422 = 0xb,
VOP2_AFBC_FMT_YUV422_10BIT = 0xe,
VOP2_AFBC_FMT_INVALID = -1,
};
union vop2_alpha_ctrl {
u32 val;
struct {
/* [0:1] */
u32 color_mode:1;
u32 alpha_mode:1;
/* [2:3] */
u32 blend_mode:2;
u32 alpha_cal_mode:1;
/* [5:7] */
u32 factor_mode:3;
/* [8:9] */
u32 alpha_en:1;
u32 src_dst_swap:1;
u32 reserved:6;
/* [16:23] */
u32 glb_alpha:8;
} bits;
};
struct vop2_alpha {
union vop2_alpha_ctrl src_color_ctrl;
union vop2_alpha_ctrl dst_color_ctrl;
union vop2_alpha_ctrl src_alpha_ctrl;
union vop2_alpha_ctrl dst_alpha_ctrl;
};
struct vop2_alpha_config {
bool src_premulti_en;
bool dst_premulti_en;
bool src_pixel_alpha_en;
bool dst_pixel_alpha_en;
u16 src_glb_alpha_value;
u16 dst_glb_alpha_value;
};
struct vop2_win {
struct vop2 *vop2;
struct drm_plane base;
const struct vop2_win_data *data;
struct regmap_field *reg[VOP2_WIN_MAX_REG];
/**
* @win_id: graphic window id, a cluster may be split into two
* graphics windows.
*/
u8 win_id;
u8 delay;
u32 offset;
enum drm_plane_type type;
};
struct vop2_video_port {
struct drm_crtc crtc;
struct vop2 *vop2;
struct clk *dclk;
unsigned int id;
const struct vop2_video_port_regs *regs;
const struct vop2_video_port_data *data;
struct completion dsp_hold_completion;
/**
* @win_mask: Bitmask of windows attached to the video port;
*/
u32 win_mask;
struct vop2_win *primary_plane;
struct drm_pending_vblank_event *event;
unsigned int nlayers;
};
struct vop2 {
struct device *dev;
struct drm_device *drm;
struct vop2_video_port vps[ROCKCHIP_MAX_CRTC];
const struct vop2_data *data;
/*
* Number of windows that are registered as plane, may be less than the
* total number of hardware windows.
*/
u32 registered_num_wins;
void __iomem *regs;
struct regmap *map;
struct regmap *grf;
/* physical map length of vop2 register */
u32 len;
void __iomem *lut_regs;
/* protects crtc enable/disable */
struct mutex vop2_lock;
int irq;
/*
* Some global resources are shared between all video ports(crtcs), so
* we need a ref counter here.
*/
unsigned int enable_count;
struct clk *hclk;
struct clk *aclk;
/* must be put at the end of the struct */
struct vop2_win win[];
};
static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc)
{
return container_of(crtc, struct vop2_video_port, crtc);
}
static struct vop2_win *to_vop2_win(struct drm_plane *p)
{
return container_of(p, struct vop2_win, base);
}
static void vop2_lock(struct vop2 *vop2)
{
mutex_lock(&vop2->vop2_lock);
}
static void vop2_unlock(struct vop2 *vop2)
{
mutex_unlock(&vop2->vop2_lock);
}
static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)
{
regmap_write(vop2->map, offset, v);
}
static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v)
{
regmap_write(vp->vop2->map, vp->data->offset + offset, v);
}
static u32 vop2_readl(struct vop2 *vop2, u32 offset)
{
u32 val;
regmap_read(vop2->map, offset, &val);
return val;
}
static void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v)
{
regmap_field_write(win->reg[reg], v);
}
static bool vop2_cluster_window(const struct vop2_win *win)
{
return win->data->feature & WIN_FEATURE_CLUSTER;
}
static void vop2_cfg_done(struct vop2_video_port *vp)
{
struct vop2 *vop2 = vp->vop2;
regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE,
BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
}
static void vop2_win_disable(struct vop2_win *win)
{
vop2_win_write(win, VOP2_WIN_ENABLE, 0);
if (vop2_cluster_window(win))
vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0);
}
static enum vop2_data_format vop2_convert_format(u32 format)
{
switch (format) {
case DRM_FORMAT_XRGB8888:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ABGR8888:
return VOP2_FMT_ARGB8888;
case DRM_FORMAT_RGB888:
case DRM_FORMAT_BGR888:
return VOP2_FMT_RGB888;
case DRM_FORMAT_RGB565:
case DRM_FORMAT_BGR565:
return VOP2_FMT_RGB565;
case DRM_FORMAT_NV12:
return VOP2_FMT_YUV420SP;
case DRM_FORMAT_NV16:
return VOP2_FMT_YUV422SP;
case DRM_FORMAT_NV24:
return VOP2_FMT_YUV444SP;
case DRM_FORMAT_YUYV:
case DRM_FORMAT_YVYU:
return VOP2_FMT_VYUY422;
case DRM_FORMAT_VYUY:
case DRM_FORMAT_UYVY:
return VOP2_FMT_YUYV422;
default:
DRM_ERROR("unsupported format[%08x]\n", format);
return -EINVAL;
}
}
static enum vop2_afbc_format vop2_convert_afbc_format(u32 format)
{
switch (format) {
case DRM_FORMAT_XRGB8888:
case DRM_FORMAT_ARGB8888:
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ABGR8888:
return VOP2_AFBC_FMT_ARGB8888;
case DRM_FORMAT_RGB888:
case DRM_FORMAT_BGR888:
return VOP2_AFBC_FMT_RGB888;
case DRM_FORMAT_RGB565:
case DRM_FORMAT_BGR565:
return VOP2_AFBC_FMT_RGB565;
case DRM_FORMAT_NV12:
return VOP2_AFBC_FMT_YUV420;
case DRM_FORMAT_NV16:
return VOP2_AFBC_FMT_YUV422;
default:
return VOP2_AFBC_FMT_INVALID;
}
return VOP2_AFBC_FMT_INVALID;
}
static bool vop2_win_rb_swap(u32 format)
{
switch (format) {
case DRM_FORMAT_XBGR8888:
case DRM_FORMAT_ABGR8888:
case DRM_FORMAT_BGR888:
case DRM_FORMAT_BGR565:
return true;
default:
return false;
}
}
static bool vop2_afbc_rb_swap(u32 format)
{
switch (format) {
case DRM_FORMAT_NV24:
return true;
default:
return false;
}
}
static bool vop2_afbc_uv_swap(u32 format)
{
switch (format) {
case DRM_FORMAT_NV12:
case DRM_FORMAT_NV16:
return true;
default:
return false;
}
}
static bool vop2_win_uv_swap(u32 format)
{
switch (format) {
case DRM_FORMAT_NV12:
case DRM_FORMAT_NV16:
case DRM_FORMAT_NV24:
return true;
default:
return false;
}
}
static bool vop2_win_dither_up(u32 format)
{
switch (format) {
case DRM_FORMAT_BGR565:
case DRM_FORMAT_RGB565:
return true;
default:
return false;
}
}
static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode)
{
/*
* FIXME:
*
* There is no media type for YUV444 output,
* so when out_mode is AAAA or P888, assume output is YUV444 on
* yuv format.
*
* From H/W testing, YUV444 mode need a rb swap.
*/
if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 ||
bus_format == MEDIA_BUS_FMT_VYUY8_1X16 ||
bus_format == MEDIA_BUS_FMT_YVYU8_2X8 ||
bus_format == MEDIA_BUS_FMT_VYUY8_2X8 ||
((bus_format == MEDIA_BUS_FMT_YUV8_1X24 ||
bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
(output_mode == ROCKCHIP_OUT_MODE_AAAA ||
output_mode == ROCKCHIP_OUT_MODE_P888)))
return true;
else
return false;
}
static bool is_yuv_output(u32 bus_format)
{
switch (bus_format) {
case MEDIA_BUS_FMT_YUV8_1X24:
case MEDIA_BUS_FMT_YUV10_1X30:
case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
case MEDIA_BUS_FMT_YUYV8_2X8:
case MEDIA_BUS_FMT_YVYU8_2X8:
case MEDIA_BUS_FMT_UYVY8_2X8:
case MEDIA_BUS_FMT_VYUY8_2X8:
case MEDIA_BUS_FMT_YUYV8_1X16:
case MEDIA_BUS_FMT_YVYU8_1X16:
case MEDIA_BUS_FMT_UYVY8_1X16:
case MEDIA_BUS_FMT_VYUY8_1X16:
return true;
default:
return false;
}
}
static bool rockchip_afbc(struct drm_plane *plane, u64 modifier)
{
int i;
if (modifier == DRM_FORMAT_MOD_LINEAR)
return false;
for (i = 0 ; i < plane->modifier_count; i++)
if (plane->modifiers[i] == modifier)
return true;
return false;
}
static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format,
u64 modifier)
{
struct vop2_win *win = to_vop2_win(plane);
struct vop2 *vop2 = win->vop2;
if (modifier == DRM_FORMAT_MOD_INVALID)
return false;
if (modifier == DRM_FORMAT_MOD_LINEAR)
return true;
if (!rockchip_afbc(plane, modifier)) {
drm_err(vop2->drm, "Unsupported format modifier 0x%llx\n",
modifier);
return false;
}
return vop2_convert_afbc_format(format) >= 0;
}
static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate,
bool afbc_half_block_en)
{
struct drm_rect *src = &pstate->src;
struct drm_framebuffer *fb = pstate->fb;
u32 bpp = fb->format->cpp[0] * 8;
u32 vir_width = (fb->pitches[0] << 3) / bpp;
u32 width = drm_rect_width(src) >> 16;
u32 height = drm_rect_height(src) >> 16;
u32 act_xoffset = src->x1 >> 16;
u32 act_yoffset = src->y1 >> 16;
u32 align16_crop = 0;
u32 align64_crop = 0;
u32 height_tmp;
u8 tx, ty;
u8 bottom_crop_line_num = 0;
/* 16 pixel align */
if (height & 0xf)
align16_crop = 16 - (height & 0xf);
height_tmp = height + align16_crop;
/* 64 pixel align */
if (height_tmp & 0x3f)
align64_crop = 64 - (height_tmp & 0x3f);
bottom_crop_line_num = align16_crop + align64_crop;
switch (pstate->rotation &
(DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y |
DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) {
case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y:
tx = 16 - ((act_xoffset + width) & 0xf);
ty = bottom_crop_line_num - act_yoffset;
break;
case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90:
tx = bottom_crop_line_num - act_yoffset;
ty = vir_width - width - act_xoffset;
break;
case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270:
tx = act_yoffset;
ty = act_xoffset;
break;
case DRM_MODE_REFLECT_X:
tx = 16 - ((act_xoffset + width) & 0xf);
ty = act_yoffset;
break;
case DRM_MODE_REFLECT_Y:
tx = act_xoffset;
ty = bottom_crop_line_num - act_yoffset;
break;
case DRM_MODE_ROTATE_90:
tx = bottom_crop_line_num - act_yoffset;
ty = act_xoffset;
break;
case DRM_MODE_ROTATE_270:
tx = act_yoffset;
ty = vir_width - width - act_xoffset;
break;
case 0:
tx = act_xoffset;
ty = act_yoffset;
break;
}
if (afbc_half_block_en)
ty &= 0x7f;
#define TRANSFORM_XOFFSET GENMASK(7, 0)
#define TRANSFORM_YOFFSET GENMASK(23, 16)
return FIELD_PREP(TRANSFORM_XOFFSET, tx) |
FIELD_PREP(TRANSFORM_YOFFSET, ty);
}
/*
* A Cluster window has 2048 x 16 line buffer, which can
* works at 2048 x 16(Full) or 4096 x 8 (Half) mode.
* for Cluster_lb_mode register:
* 0: half mode, for plane input width range 2048 ~ 4096
* 1: half mode, for cluster work at 2 * 2048 plane mode
* 2: half mode, for rotate_90/270 mode
*
*/
static int vop2_get_cluster_lb_mode(struct vop2_win *win,
struct drm_plane_state *pstate)
{
if ((pstate->rotation & DRM_MODE_ROTATE_270) ||
(pstate->rotation & DRM_MODE_ROTATE_90))
return 2;
else
return 0;
}
static u16 vop2_scale_factor(u32 src, u32 dst)
{
u32 fac;
int shift;
if (src == dst)
return 0;
if (dst < 2)
return U16_MAX;
if (src < 2)
return 0;
if (src > dst)
shift = 12;
else
shift = 16;
src--;
dst--;
fac = DIV_ROUND_UP(src << shift, dst) - 1;
if (fac > U16_MAX)
return U16_MAX;
return fac;
}
static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,
u32 src_w, u32 src_h, u32 dst_w,
u32 dst_h, u32 pixel_format)
{
const struct drm_format_info *info;
u16 hor_scl_mode, ver_scl_mode;
u16 hscl_filter_mode, vscl_filter_mode;
u8 gt2 = 0;
u8 gt4 = 0;
u32 val;
info = drm_format_info(pixel_format);
if (src_h >= (4 * dst_h)) {
gt4 = 1;
src_h >>= 2;
} else if (src_h >= (2 * dst_h)) {
gt2 = 1;
src_h >>= 1;
}
hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
if (hor_scl_mode == SCALE_UP)
hscl_filter_mode = VOP2_SCALE_UP_BIC;
else
hscl_filter_mode = VOP2_SCALE_DOWN_BIL;
if (ver_scl_mode == SCALE_UP)
vscl_filter_mode = VOP2_SCALE_UP_BIL;
else
vscl_filter_mode = VOP2_SCALE_DOWN_BIL;
/*
* RK3568 VOP Esmart/Smart dsp_w should be even pixel
* at scale down mode
*/
if (!(win->data->feature & WIN_FEATURE_AFBDC)) {
if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) {
drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n",
win->data->name, dst_w);
dst_w++;
}
}
val = vop2_scale_factor(src_w, dst_w);
vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val);
val = vop2_scale_factor(src_h, dst_h);
vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val);
vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4);
vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2);
vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode);
vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode);
if (vop2_cluster_window(win))
return;
vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode);
vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode);
if (info->is_yuv) {
src_w /= info->hsub;
src_h /= info->vsub;
gt4 = 0;
gt2 = 0;
if (src_h >= (4 * dst_h)) {
gt4 = 1;
src_h >>= 2;
} else if (src_h >= (2 * dst_h)) {
gt2 = 1;
src_h >>= 1;
}
hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
val = vop2_scale_factor(src_w, dst_w);
vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val);
val = vop2_scale_factor(src_h, dst_h);
vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val);
vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4);
vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2);
vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode);
vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode);
vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode);
vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode);
}
}
static int vop2_convert_csc_mode(int csc_mode)
{
switch (csc_mode) {
case V4L2_COLORSPACE_SMPTE170M:
case V4L2_COLORSPACE_470_SYSTEM_M:
case V4L2_COLORSPACE_470_SYSTEM_BG:
return CSC_BT601L;
case V4L2_COLORSPACE_REC709:
case V4L2_COLORSPACE_SMPTE240M:
case V4L2_COLORSPACE_DEFAULT:
return CSC_BT709L;
case V4L2_COLORSPACE_JPEG:
return CSC_BT601F;
case V4L2_COLORSPACE_BT2020:
return CSC_BT2020;
default:
return CSC_BT709L;
}
}
/*
* colorspace path:
* Input Win csc Output
* 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
* RGB --> R2Y __/
*
* 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020)
* RGB --> 709To2020->R2Y __/
*
* 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709)
* RGB --> R2Y __/
*
* 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
* RGB --> 709To2020->R2Y __/
*
* 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709)
* RGB --> R2Y __/
*
* 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601)
* RGB --> R2Y(601) __/
*
* 7. YUV --> Y2R(709) --> RGB_OUTPUT(709)
* RGB --> bypass __/
*
* 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020)
*
* 9. RGB --> R2Y(709) --> YUV_OUTPUT(709)
*
* 10. RGB --> R2Y(601) --> YUV_OUTPUT(601)
*
* 11. RGB --> bypass --> RGB_OUTPUT(709)
*/
static void vop2_setup_csc_mode(struct vop2_video_port *vp,
struct vop2_win *win,
struct drm_plane_state *pstate)
{
struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
int is_input_yuv = pstate->fb->format->is_yuv;
int is_output_yuv = is_yuv_output(vcstate->bus_format);
int input_csc = V4L2_COLORSPACE_DEFAULT;
int output_csc = vcstate->color_space;
bool r2y_en, y2r_en;
int csc_mode;
if (is_input_yuv && !is_output_yuv) {
y2r_en = true;
r2y_en = false;
csc_mode = vop2_convert_csc_mode(input_csc);
} else if (!is_input_yuv && is_output_yuv) {
y2r_en = false;
r2y_en = true;
csc_mode = vop2_convert_csc_mode(output_csc);
} else {
y2r_en = false;
r2y_en = false;
csc_mode = false;
}
vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en);
vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en);
vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode);
}
static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq)
{
struct vop2 *vop2 = vp->vop2;
vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq);
vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq);
}
static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq)
{
struct vop2 *vop2 = vp->vop2;
vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16);
}
static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
{
int ret;
ret = clk_prepare_enable(vop2->hclk);
if (ret < 0) {
drm_err(vop2->drm, "failed to enable hclk - %d\n", ret);
return ret;
}
ret = clk_prepare_enable(vop2->aclk);
if (ret < 0) {
drm_err(vop2->drm, "failed to enable aclk - %d\n", ret);
goto err;
}
return 0;
err:
clk_disable_unprepare(vop2->hclk);
return ret;
}
static void vop2_enable(struct vop2 *vop2)
{
int ret;
ret = pm_runtime_get_sync(vop2->dev);
if (ret < 0) {
drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret);
return;
}
ret = vop2_core_clks_prepare_enable(vop2);
if (ret) {
pm_runtime_put_sync(vop2->dev);
return;
}
ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev);
if (ret) {
drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret);
return;
}
if (vop2->data->soc_id == 3566)
vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);
vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
/*
* Disable auto gating, this is a workaround to
* avoid display image shift when a window enabled.
*/
regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL,
RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN);
vop2_writel(vop2, RK3568_SYS0_INT_CLR,
VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
vop2_writel(vop2, RK3568_SYS0_INT_EN,
VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
vop2_writel(vop2, RK3568_SYS1_INT_CLR,
VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
vop2_writel(vop2, RK3568_SYS1_INT_EN,
VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
}
static void vop2_disable(struct vop2 *vop2)
{
rockchip_drm_dma_detach_device(vop2->drm, vop2->dev);
pm_runtime_put_sync(vop2->dev);
clk_disable_unprepare(vop2->aclk);
clk_disable_unprepare(vop2->hclk);
}
static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
struct drm_atomic_state *state)
{
struct vop2_video_port *vp = to_vop2_video_port(crtc);
struct vop2 *vop2 = vp->vop2;
int ret;
vop2_lock(vop2);
drm_crtc_vblank_off(crtc);
/*
* Vop standby will take effect at end of current frame,
* if dsp hold valid irq happen, it means standby complete.
*
* we must wait standby complete when we want to disable aclk,
* if not, memory bus maybe dead.
*/
reinit_completion(&vp->dsp_hold_completion);
vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID);
vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY);
ret = wait_for_completion_timeout(&vp->dsp_hold_completion,
msecs_to_jiffies(50));
if (!ret)
drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id);
vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID);
clk_disable_unprepare(vp->dclk);
vop2->enable_count--;
if (!vop2->enable_count)
vop2_disable(vop2);
vop2_unlock(vop2);
if (crtc->state->event && !crtc->state->active) {
spin_lock_irq(&crtc->dev->event_lock);
drm_crtc_send_vblank_event(crtc, crtc->state->event);
spin_unlock_irq(&crtc->dev->event_lock);
crtc->state->event = NULL;
}
}
static int vop2_plane_atomic_check(struct drm_plane *plane,
struct drm_atomic_state *astate)
{
struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane);
struct drm_framebuffer *fb = pstate->fb;
struct drm_crtc *crtc = pstate->crtc;
struct drm_crtc_state *cstate;
struct vop2_video_port *vp;
struct vop2 *vop2;
const struct vop2_data *vop2_data;
struct drm_rect *dest = &pstate->dst;
struct drm_rect *src = &pstate->src;
int min_scale = FRAC_16_16(1, 8);
int max_scale = FRAC_16_16(8, 1);
int format;
int ret;
if (!crtc)
return 0;
vp = to_vop2_video_port(crtc);
vop2 = vp->vop2;
vop2_data = vop2->data;
cstate = drm_atomic_get_existing_crtc_state(pstate->state, crtc);
if (WARN_ON(!cstate))
return -EINVAL;
ret = drm_atomic_helper_check_plane_state(pstate, cstate,
min_scale, max_scale,
true, true);
if (ret)
return ret;
if (!pstate->visible)
return 0;
format = vop2_convert_format(fb->format->format);
if (format < 0)
return format;
if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 ||
drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) {
drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n",
drm_rect_width(src) >> 16, drm_rect_height(src) >> 16,
drm_rect_width(dest), drm_rect_height(dest));
pstate->visible = false;
return 0;
}
if (drm_rect_width(src) >> 16 > vop2_data->max_input.width ||
drm_rect_height(src) >> 16 > vop2_data->max_input.height) {
drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n",
drm_rect_width(src) >> 16,
drm_rect_height(src) >> 16,
vop2_data->max_input.width,
vop2_data->max_input.height);
return -EINVAL;
}
/*
* Src.x1 can be odd when do clip, but yuv plane start point
* need align with 2 pixel.
*/
if (fb->format->is_yuv && ((pstate->src.x1 >> 16) % 2)) {
drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n");
return -EINVAL;
}
return 0;
}
static void vop2_plane_atomic_disable(struct drm_plane *plane,
struct drm_atomic_state *state)
{
struct drm_plane_state *old_pstate = drm_atomic_get_old_plane_state(state, plane);
struct vop2_win *win = to_vop2_win(plane);
struct vop2 *vop2 = win->vop2;