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lan78xx.c
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lan78xx.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Microchip Technology
*/
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/usb.h>
#include <linux/crc32.h>
#include <linux/signal.h>
#include <linux/slab.h>
#include <linux/if_vlan.h>
#include <linux/uaccess.h>
#include <linux/linkmode.h>
#include <linux/list.h>
#include <linux/ip.h>
#include <linux/ipv6.h>
#include <linux/mdio.h>
#include <linux/phy.h>
#include <net/ip6_checksum.h>
#include <net/vxlan.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/microchipphy.h>
#include <linux/phy_fixed.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include "lan78xx.h"
#define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
#define DRIVER_DESC "LAN78XX USB 3.0 Gigabit Ethernet Devices"
#define DRIVER_NAME "lan78xx"
#define TX_TIMEOUT_JIFFIES (5 * HZ)
#define THROTTLE_JIFFIES (HZ / 8)
#define UNLINK_TIMEOUT_MS 3
#define RX_MAX_QUEUE_MEMORY (60 * 1518)
#define SS_USB_PKT_SIZE (1024)
#define HS_USB_PKT_SIZE (512)
#define FS_USB_PKT_SIZE (64)
#define MAX_RX_FIFO_SIZE (12 * 1024)
#define MAX_TX_FIFO_SIZE (12 * 1024)
#define FLOW_THRESHOLD(n) ((((n) + 511) / 512) & 0x7F)
#define FLOW_CTRL_THRESHOLD(on, off) ((FLOW_THRESHOLD(on) << 0) | \
(FLOW_THRESHOLD(off) << 8))
/* Flow control turned on when Rx FIFO level rises above this level (bytes) */
#define FLOW_ON_SS 9216
#define FLOW_ON_HS 8704
/* Flow control turned off when Rx FIFO level falls below this level (bytes) */
#define FLOW_OFF_SS 4096
#define FLOW_OFF_HS 1024
#define DEFAULT_BURST_CAP_SIZE (MAX_TX_FIFO_SIZE)
#define DEFAULT_BULK_IN_DELAY (0x0800)
#define MAX_SINGLE_PACKET_SIZE (9000)
#define DEFAULT_TX_CSUM_ENABLE (true)
#define DEFAULT_RX_CSUM_ENABLE (true)
#define DEFAULT_TSO_CSUM_ENABLE (true)
#define DEFAULT_VLAN_FILTER_ENABLE (true)
#define DEFAULT_VLAN_RX_OFFLOAD (true)
#define TX_OVERHEAD (8)
#define RXW_PADDING 2
#define LAN78XX_USB_VENDOR_ID (0x0424)
#define LAN7800_USB_PRODUCT_ID (0x7800)
#define LAN7850_USB_PRODUCT_ID (0x7850)
#define LAN7801_USB_PRODUCT_ID (0x7801)
#define LAN78XX_EEPROM_MAGIC (0x78A5)
#define LAN78XX_OTP_MAGIC (0x78F3)
#define AT29M2AF_USB_VENDOR_ID (0x07C9)
#define AT29M2AF_USB_PRODUCT_ID (0x0012)
#define MII_READ 1
#define MII_WRITE 0
#define EEPROM_INDICATOR (0xA5)
#define EEPROM_MAC_OFFSET (0x01)
#define MAX_EEPROM_SIZE 512
#define OTP_INDICATOR_1 (0xF3)
#define OTP_INDICATOR_2 (0xF7)
#define WAKE_ALL (WAKE_PHY | WAKE_UCAST | \
WAKE_MCAST | WAKE_BCAST | \
WAKE_ARP | WAKE_MAGIC)
/* USB related defines */
#define BULK_IN_PIPE 1
#define BULK_OUT_PIPE 2
/* default autosuspend delay (mSec)*/
#define DEFAULT_AUTOSUSPEND_DELAY (10 * 1000)
/* statistic update interval (mSec) */
#define STAT_UPDATE_TIMER (1 * 1000)
/* time to wait for MAC or FCT to stop (jiffies) */
#define HW_DISABLE_TIMEOUT (HZ / 10)
/* time to wait between polling MAC or FCT state (ms) */
#define HW_DISABLE_DELAY_MS 1
/* defines interrupts from interrupt EP */
#define MAX_INT_EP (32)
#define INT_EP_INTEP (31)
#define INT_EP_OTP_WR_DONE (28)
#define INT_EP_EEE_TX_LPI_START (26)
#define INT_EP_EEE_TX_LPI_STOP (25)
#define INT_EP_EEE_RX_LPI (24)
#define INT_EP_MAC_RESET_TIMEOUT (23)
#define INT_EP_RDFO (22)
#define INT_EP_TXE (21)
#define INT_EP_USB_STATUS (20)
#define INT_EP_TX_DIS (19)
#define INT_EP_RX_DIS (18)
#define INT_EP_PHY (17)
#define INT_EP_DP (16)
#define INT_EP_MAC_ERR (15)
#define INT_EP_TDFU (14)
#define INT_EP_TDFO (13)
#define INT_EP_UTX (12)
#define INT_EP_GPIO_11 (11)
#define INT_EP_GPIO_10 (10)
#define INT_EP_GPIO_9 (9)
#define INT_EP_GPIO_8 (8)
#define INT_EP_GPIO_7 (7)
#define INT_EP_GPIO_6 (6)
#define INT_EP_GPIO_5 (5)
#define INT_EP_GPIO_4 (4)
#define INT_EP_GPIO_3 (3)
#define INT_EP_GPIO_2 (2)
#define INT_EP_GPIO_1 (1)
#define INT_EP_GPIO_0 (0)
static const char lan78xx_gstrings[][ETH_GSTRING_LEN] = {
"RX FCS Errors",
"RX Alignment Errors",
"Rx Fragment Errors",
"RX Jabber Errors",
"RX Undersize Frame Errors",
"RX Oversize Frame Errors",
"RX Dropped Frames",
"RX Unicast Byte Count",
"RX Broadcast Byte Count",
"RX Multicast Byte Count",
"RX Unicast Frames",
"RX Broadcast Frames",
"RX Multicast Frames",
"RX Pause Frames",
"RX 64 Byte Frames",
"RX 65 - 127 Byte Frames",
"RX 128 - 255 Byte Frames",
"RX 256 - 511 Bytes Frames",
"RX 512 - 1023 Byte Frames",
"RX 1024 - 1518 Byte Frames",
"RX Greater 1518 Byte Frames",
"EEE RX LPI Transitions",
"EEE RX LPI Time",
"TX FCS Errors",
"TX Excess Deferral Errors",
"TX Carrier Errors",
"TX Bad Byte Count",
"TX Single Collisions",
"TX Multiple Collisions",
"TX Excessive Collision",
"TX Late Collisions",
"TX Unicast Byte Count",
"TX Broadcast Byte Count",
"TX Multicast Byte Count",
"TX Unicast Frames",
"TX Broadcast Frames",
"TX Multicast Frames",
"TX Pause Frames",
"TX 64 Byte Frames",
"TX 65 - 127 Byte Frames",
"TX 128 - 255 Byte Frames",
"TX 256 - 511 Bytes Frames",
"TX 512 - 1023 Byte Frames",
"TX 1024 - 1518 Byte Frames",
"TX Greater 1518 Byte Frames",
"EEE TX LPI Transitions",
"EEE TX LPI Time",
};
struct lan78xx_statstage {
u32 rx_fcs_errors;
u32 rx_alignment_errors;
u32 rx_fragment_errors;
u32 rx_jabber_errors;
u32 rx_undersize_frame_errors;
u32 rx_oversize_frame_errors;
u32 rx_dropped_frames;
u32 rx_unicast_byte_count;
u32 rx_broadcast_byte_count;
u32 rx_multicast_byte_count;
u32 rx_unicast_frames;
u32 rx_broadcast_frames;
u32 rx_multicast_frames;
u32 rx_pause_frames;
u32 rx_64_byte_frames;
u32 rx_65_127_byte_frames;
u32 rx_128_255_byte_frames;
u32 rx_256_511_bytes_frames;
u32 rx_512_1023_byte_frames;
u32 rx_1024_1518_byte_frames;
u32 rx_greater_1518_byte_frames;
u32 eee_rx_lpi_transitions;
u32 eee_rx_lpi_time;
u32 tx_fcs_errors;
u32 tx_excess_deferral_errors;
u32 tx_carrier_errors;
u32 tx_bad_byte_count;
u32 tx_single_collisions;
u32 tx_multiple_collisions;
u32 tx_excessive_collision;
u32 tx_late_collisions;
u32 tx_unicast_byte_count;
u32 tx_broadcast_byte_count;
u32 tx_multicast_byte_count;
u32 tx_unicast_frames;
u32 tx_broadcast_frames;
u32 tx_multicast_frames;
u32 tx_pause_frames;
u32 tx_64_byte_frames;
u32 tx_65_127_byte_frames;
u32 tx_128_255_byte_frames;
u32 tx_256_511_bytes_frames;
u32 tx_512_1023_byte_frames;
u32 tx_1024_1518_byte_frames;
u32 tx_greater_1518_byte_frames;
u32 eee_tx_lpi_transitions;
u32 eee_tx_lpi_time;
};
struct lan78xx_statstage64 {
u64 rx_fcs_errors;
u64 rx_alignment_errors;
u64 rx_fragment_errors;
u64 rx_jabber_errors;
u64 rx_undersize_frame_errors;
u64 rx_oversize_frame_errors;
u64 rx_dropped_frames;
u64 rx_unicast_byte_count;
u64 rx_broadcast_byte_count;
u64 rx_multicast_byte_count;
u64 rx_unicast_frames;
u64 rx_broadcast_frames;
u64 rx_multicast_frames;
u64 rx_pause_frames;
u64 rx_64_byte_frames;
u64 rx_65_127_byte_frames;
u64 rx_128_255_byte_frames;
u64 rx_256_511_bytes_frames;
u64 rx_512_1023_byte_frames;
u64 rx_1024_1518_byte_frames;
u64 rx_greater_1518_byte_frames;
u64 eee_rx_lpi_transitions;
u64 eee_rx_lpi_time;
u64 tx_fcs_errors;
u64 tx_excess_deferral_errors;
u64 tx_carrier_errors;
u64 tx_bad_byte_count;
u64 tx_single_collisions;
u64 tx_multiple_collisions;
u64 tx_excessive_collision;
u64 tx_late_collisions;
u64 tx_unicast_byte_count;
u64 tx_broadcast_byte_count;
u64 tx_multicast_byte_count;
u64 tx_unicast_frames;
u64 tx_broadcast_frames;
u64 tx_multicast_frames;
u64 tx_pause_frames;
u64 tx_64_byte_frames;
u64 tx_65_127_byte_frames;
u64 tx_128_255_byte_frames;
u64 tx_256_511_bytes_frames;
u64 tx_512_1023_byte_frames;
u64 tx_1024_1518_byte_frames;
u64 tx_greater_1518_byte_frames;
u64 eee_tx_lpi_transitions;
u64 eee_tx_lpi_time;
};
static u32 lan78xx_regs[] = {
ID_REV,
INT_STS,
HW_CFG,
PMT_CTL,
E2P_CMD,
E2P_DATA,
USB_STATUS,
VLAN_TYPE,
MAC_CR,
MAC_RX,
MAC_TX,
FLOW,
ERR_STS,
MII_ACC,
MII_DATA,
EEE_TX_LPI_REQ_DLY,
EEE_TW_TX_SYS,
EEE_TX_LPI_REM_DLY,
WUCSR
};
#define PHY_REG_SIZE (32 * sizeof(u32))
struct lan78xx_net;
struct lan78xx_priv {
struct lan78xx_net *dev;
u32 rfe_ctl;
u32 mchash_table[DP_SEL_VHF_HASH_LEN]; /* multicast hash table */
u32 pfilter_table[NUM_OF_MAF][2]; /* perfect filter table */
u32 vlan_table[DP_SEL_VHF_VLAN_LEN];
struct mutex dataport_mutex; /* for dataport access */
spinlock_t rfe_ctl_lock; /* for rfe register access */
struct work_struct set_multicast;
struct work_struct set_vlan;
u32 wol;
};
enum skb_state {
illegal = 0,
tx_start,
tx_done,
rx_start,
rx_done,
rx_cleanup,
unlink_start
};
struct skb_data { /* skb->cb is one of these */
struct urb *urb;
struct lan78xx_net *dev;
enum skb_state state;
size_t length;
int num_of_packet;
};
struct usb_context {
struct usb_ctrlrequest req;
struct lan78xx_net *dev;
};
#define EVENT_TX_HALT 0
#define EVENT_RX_HALT 1
#define EVENT_RX_MEMORY 2
#define EVENT_STS_SPLIT 3
#define EVENT_LINK_RESET 4
#define EVENT_RX_PAUSED 5
#define EVENT_DEV_WAKING 6
#define EVENT_DEV_ASLEEP 7
#define EVENT_DEV_OPEN 8
#define EVENT_STAT_UPDATE 9
#define EVENT_DEV_DISCONNECT 10
struct statstage {
struct mutex access_lock; /* for stats access */
struct lan78xx_statstage saved;
struct lan78xx_statstage rollover_count;
struct lan78xx_statstage rollover_max;
struct lan78xx_statstage64 curr_stat;
};
struct irq_domain_data {
struct irq_domain *irqdomain;
unsigned int phyirq;
struct irq_chip *irqchip;
irq_flow_handler_t irq_handler;
u32 irqenable;
struct mutex irq_lock; /* for irq bus access */
};
struct lan78xx_net {
struct net_device *net;
struct usb_device *udev;
struct usb_interface *intf;
void *driver_priv;
int rx_qlen;
int tx_qlen;
struct sk_buff_head rxq;
struct sk_buff_head txq;
struct sk_buff_head done;
struct sk_buff_head txq_pend;
struct tasklet_struct bh;
struct delayed_work wq;
int msg_enable;
struct urb *urb_intr;
struct usb_anchor deferred;
struct mutex dev_mutex; /* serialise open/stop wrt suspend/resume */
struct mutex phy_mutex; /* for phy access */
unsigned int pipe_in, pipe_out, pipe_intr;
u32 hard_mtu; /* count any extra framing */
size_t rx_urb_size; /* size for rx urbs */
unsigned long flags;
wait_queue_head_t *wait;
unsigned char suspend_count;
unsigned int maxpacket;
struct timer_list stat_monitor;
unsigned long data[5];
int link_on;
u8 mdix_ctrl;
u32 chipid;
u32 chiprev;
struct mii_bus *mdiobus;
phy_interface_t interface;
int fc_autoneg;
u8 fc_request_control;
int delta;
struct statstage stats;
struct irq_domain_data domain_data;
};
/* define external phy id */
#define PHY_LAN8835 (0x0007C130)
#define PHY_KSZ9031RNX (0x00221620)
/* use ethtool to change the level for any given device */
static int msg_level = -1;
module_param(msg_level, int, 0);
MODULE_PARM_DESC(msg_level, "Override default message level");
static int lan78xx_read_reg(struct lan78xx_net *dev, u32 index, u32 *data)
{
u32 *buf;
int ret;
if (test_bit(EVENT_DEV_DISCONNECT, &dev->flags))
return -ENODEV;
buf = kmalloc(sizeof(u32), GFP_KERNEL);
if (!buf)
return -ENOMEM;
ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
USB_VENDOR_REQUEST_READ_REGISTER,
USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
0, index, buf, 4, USB_CTRL_GET_TIMEOUT);
if (likely(ret >= 0)) {
le32_to_cpus(buf);
*data = *buf;
} else if (net_ratelimit()) {
netdev_warn(dev->net,
"Failed to read register index 0x%08x. ret = %d",
index, ret);
}
kfree(buf);
return ret;
}
static int lan78xx_write_reg(struct lan78xx_net *dev, u32 index, u32 data)
{
u32 *buf;
int ret;
if (test_bit(EVENT_DEV_DISCONNECT, &dev->flags))
return -ENODEV;
buf = kmalloc(sizeof(u32), GFP_KERNEL);
if (!buf)
return -ENOMEM;
*buf = data;
cpu_to_le32s(buf);
ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
USB_VENDOR_REQUEST_WRITE_REGISTER,
USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
0, index, buf, 4, USB_CTRL_SET_TIMEOUT);
if (unlikely(ret < 0) &&
net_ratelimit()) {
netdev_warn(dev->net,
"Failed to write register index 0x%08x. ret = %d",
index, ret);
}
kfree(buf);
return ret;
}
static int lan78xx_update_reg(struct lan78xx_net *dev, u32 reg, u32 mask,
u32 data)
{
int ret;
u32 buf;
ret = lan78xx_read_reg(dev, reg, &buf);
if (ret < 0)
return ret;
buf &= ~mask;
buf |= (mask & data);
ret = lan78xx_write_reg(dev, reg, buf);
if (ret < 0)
return ret;
return 0;
}
static int lan78xx_read_stats(struct lan78xx_net *dev,
struct lan78xx_statstage *data)
{
int ret = 0;
int i;
struct lan78xx_statstage *stats;
u32 *src;
u32 *dst;
stats = kmalloc(sizeof(*stats), GFP_KERNEL);
if (!stats)
return -ENOMEM;
ret = usb_control_msg(dev->udev,
usb_rcvctrlpipe(dev->udev, 0),
USB_VENDOR_REQUEST_GET_STATS,
USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
0,
0,
(void *)stats,
sizeof(*stats),
USB_CTRL_SET_TIMEOUT);
if (likely(ret >= 0)) {
src = (u32 *)stats;
dst = (u32 *)data;
for (i = 0; i < sizeof(*stats) / sizeof(u32); i++) {
le32_to_cpus(&src[i]);
dst[i] = src[i];
}
} else {
netdev_warn(dev->net,
"Failed to read stat ret = %d", ret);
}
kfree(stats);
return ret;
}
#define check_counter_rollover(struct1, dev_stats, member) \
do { \
if ((struct1)->member < (dev_stats).saved.member) \
(dev_stats).rollover_count.member++; \
} while (0)
static void lan78xx_check_stat_rollover(struct lan78xx_net *dev,
struct lan78xx_statstage *stats)
{
check_counter_rollover(stats, dev->stats, rx_fcs_errors);
check_counter_rollover(stats, dev->stats, rx_alignment_errors);
check_counter_rollover(stats, dev->stats, rx_fragment_errors);
check_counter_rollover(stats, dev->stats, rx_jabber_errors);
check_counter_rollover(stats, dev->stats, rx_undersize_frame_errors);
check_counter_rollover(stats, dev->stats, rx_oversize_frame_errors);
check_counter_rollover(stats, dev->stats, rx_dropped_frames);
check_counter_rollover(stats, dev->stats, rx_unicast_byte_count);
check_counter_rollover(stats, dev->stats, rx_broadcast_byte_count);
check_counter_rollover(stats, dev->stats, rx_multicast_byte_count);
check_counter_rollover(stats, dev->stats, rx_unicast_frames);
check_counter_rollover(stats, dev->stats, rx_broadcast_frames);
check_counter_rollover(stats, dev->stats, rx_multicast_frames);
check_counter_rollover(stats, dev->stats, rx_pause_frames);
check_counter_rollover(stats, dev->stats, rx_64_byte_frames);
check_counter_rollover(stats, dev->stats, rx_65_127_byte_frames);
check_counter_rollover(stats, dev->stats, rx_128_255_byte_frames);
check_counter_rollover(stats, dev->stats, rx_256_511_bytes_frames);
check_counter_rollover(stats, dev->stats, rx_512_1023_byte_frames);
check_counter_rollover(stats, dev->stats, rx_1024_1518_byte_frames);
check_counter_rollover(stats, dev->stats, rx_greater_1518_byte_frames);
check_counter_rollover(stats, dev->stats, eee_rx_lpi_transitions);
check_counter_rollover(stats, dev->stats, eee_rx_lpi_time);
check_counter_rollover(stats, dev->stats, tx_fcs_errors);
check_counter_rollover(stats, dev->stats, tx_excess_deferral_errors);
check_counter_rollover(stats, dev->stats, tx_carrier_errors);
check_counter_rollover(stats, dev->stats, tx_bad_byte_count);
check_counter_rollover(stats, dev->stats, tx_single_collisions);
check_counter_rollover(stats, dev->stats, tx_multiple_collisions);
check_counter_rollover(stats, dev->stats, tx_excessive_collision);
check_counter_rollover(stats, dev->stats, tx_late_collisions);
check_counter_rollover(stats, dev->stats, tx_unicast_byte_count);
check_counter_rollover(stats, dev->stats, tx_broadcast_byte_count);
check_counter_rollover(stats, dev->stats, tx_multicast_byte_count);
check_counter_rollover(stats, dev->stats, tx_unicast_frames);
check_counter_rollover(stats, dev->stats, tx_broadcast_frames);
check_counter_rollover(stats, dev->stats, tx_multicast_frames);
check_counter_rollover(stats, dev->stats, tx_pause_frames);
check_counter_rollover(stats, dev->stats, tx_64_byte_frames);
check_counter_rollover(stats, dev->stats, tx_65_127_byte_frames);
check_counter_rollover(stats, dev->stats, tx_128_255_byte_frames);
check_counter_rollover(stats, dev->stats, tx_256_511_bytes_frames);
check_counter_rollover(stats, dev->stats, tx_512_1023_byte_frames);
check_counter_rollover(stats, dev->stats, tx_1024_1518_byte_frames);
check_counter_rollover(stats, dev->stats, tx_greater_1518_byte_frames);
check_counter_rollover(stats, dev->stats, eee_tx_lpi_transitions);
check_counter_rollover(stats, dev->stats, eee_tx_lpi_time);
memcpy(&dev->stats.saved, stats, sizeof(struct lan78xx_statstage));
}
static void lan78xx_update_stats(struct lan78xx_net *dev)
{
u32 *p, *count, *max;
u64 *data;
int i;
struct lan78xx_statstage lan78xx_stats;
if (usb_autopm_get_interface(dev->intf) < 0)
return;
p = (u32 *)&lan78xx_stats;
count = (u32 *)&dev->stats.rollover_count;
max = (u32 *)&dev->stats.rollover_max;
data = (u64 *)&dev->stats.curr_stat;
mutex_lock(&dev->stats.access_lock);
if (lan78xx_read_stats(dev, &lan78xx_stats) > 0)
lan78xx_check_stat_rollover(dev, &lan78xx_stats);
for (i = 0; i < (sizeof(lan78xx_stats) / (sizeof(u32))); i++)
data[i] = (u64)p[i] + ((u64)count[i] * ((u64)max[i] + 1));
mutex_unlock(&dev->stats.access_lock);
usb_autopm_put_interface(dev->intf);
}
/* Loop until the read is completed with timeout called with phy_mutex held */
static int lan78xx_phy_wait_not_busy(struct lan78xx_net *dev)
{
unsigned long start_time = jiffies;
u32 val;
int ret;
do {
ret = lan78xx_read_reg(dev, MII_ACC, &val);
if (unlikely(ret < 0))
return -EIO;
if (!(val & MII_ACC_MII_BUSY_))
return 0;
} while (!time_after(jiffies, start_time + HZ));
return -EIO;
}
static inline u32 mii_access(int id, int index, int read)
{
u32 ret;
ret = ((u32)id << MII_ACC_PHY_ADDR_SHIFT_) & MII_ACC_PHY_ADDR_MASK_;
ret |= ((u32)index << MII_ACC_MIIRINDA_SHIFT_) & MII_ACC_MIIRINDA_MASK_;
if (read)
ret |= MII_ACC_MII_READ_;
else
ret |= MII_ACC_MII_WRITE_;
ret |= MII_ACC_MII_BUSY_;
return ret;
}
static int lan78xx_wait_eeprom(struct lan78xx_net *dev)
{
unsigned long start_time = jiffies;
u32 val;
int ret;
do {
ret = lan78xx_read_reg(dev, E2P_CMD, &val);
if (unlikely(ret < 0))
return -EIO;
if (!(val & E2P_CMD_EPC_BUSY_) ||
(val & E2P_CMD_EPC_TIMEOUT_))
break;
usleep_range(40, 100);
} while (!time_after(jiffies, start_time + HZ));
if (val & (E2P_CMD_EPC_TIMEOUT_ | E2P_CMD_EPC_BUSY_)) {
netdev_warn(dev->net, "EEPROM read operation timeout");
return -EIO;
}
return 0;
}
static int lan78xx_eeprom_confirm_not_busy(struct lan78xx_net *dev)
{
unsigned long start_time = jiffies;
u32 val;
int ret;
do {
ret = lan78xx_read_reg(dev, E2P_CMD, &val);
if (unlikely(ret < 0))
return -EIO;
if (!(val & E2P_CMD_EPC_BUSY_))
return 0;
usleep_range(40, 100);
} while (!time_after(jiffies, start_time + HZ));
netdev_warn(dev->net, "EEPROM is busy");
return -EIO;
}
static int lan78xx_read_raw_eeprom(struct lan78xx_net *dev, u32 offset,
u32 length, u8 *data)
{
u32 val;
u32 saved;
int i, ret;
int retval;
/* depends on chip, some EEPROM pins are muxed with LED function.
* disable & restore LED function to access EEPROM.
*/
ret = lan78xx_read_reg(dev, HW_CFG, &val);
saved = val;
if (dev->chipid == ID_REV_CHIP_ID_7800_) {
val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_);
ret = lan78xx_write_reg(dev, HW_CFG, val);
}
retval = lan78xx_eeprom_confirm_not_busy(dev);
if (retval)
return retval;
for (i = 0; i < length; i++) {
val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_;
val |= (offset & E2P_CMD_EPC_ADDR_MASK_);
ret = lan78xx_write_reg(dev, E2P_CMD, val);
if (unlikely(ret < 0)) {
retval = -EIO;
goto exit;
}
retval = lan78xx_wait_eeprom(dev);
if (retval < 0)
goto exit;
ret = lan78xx_read_reg(dev, E2P_DATA, &val);
if (unlikely(ret < 0)) {
retval = -EIO;
goto exit;
}
data[i] = val & 0xFF;
offset++;
}
retval = 0;
exit:
if (dev->chipid == ID_REV_CHIP_ID_7800_)
ret = lan78xx_write_reg(dev, HW_CFG, saved);
return retval;
}
static int lan78xx_read_eeprom(struct lan78xx_net *dev, u32 offset,
u32 length, u8 *data)
{
u8 sig;
int ret;
ret = lan78xx_read_raw_eeprom(dev, 0, 1, &sig);
if ((ret == 0) && (sig == EEPROM_INDICATOR))
ret = lan78xx_read_raw_eeprom(dev, offset, length, data);
else
ret = -EINVAL;
return ret;
}
static int lan78xx_write_raw_eeprom(struct lan78xx_net *dev, u32 offset,
u32 length, u8 *data)
{
u32 val;
u32 saved;
int i, ret;
int retval;
/* depends on chip, some EEPROM pins are muxed with LED function.
* disable & restore LED function to access EEPROM.
*/
ret = lan78xx_read_reg(dev, HW_CFG, &val);
saved = val;
if (dev->chipid == ID_REV_CHIP_ID_7800_) {
val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_);
ret = lan78xx_write_reg(dev, HW_CFG, val);
}
retval = lan78xx_eeprom_confirm_not_busy(dev);
if (retval)
goto exit;
/* Issue write/erase enable command */
val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_;
ret = lan78xx_write_reg(dev, E2P_CMD, val);
if (unlikely(ret < 0)) {
retval = -EIO;
goto exit;
}
retval = lan78xx_wait_eeprom(dev);
if (retval < 0)
goto exit;
for (i = 0; i < length; i++) {
/* Fill data register */
val = data[i];
ret = lan78xx_write_reg(dev, E2P_DATA, val);
if (ret < 0) {
retval = -EIO;
goto exit;
}
/* Send "write" command */
val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_;
val |= (offset & E2P_CMD_EPC_ADDR_MASK_);
ret = lan78xx_write_reg(dev, E2P_CMD, val);
if (ret < 0) {
retval = -EIO;
goto exit;
}
retval = lan78xx_wait_eeprom(dev);
if (retval < 0)
goto exit;
offset++;
}
retval = 0;
exit:
if (dev->chipid == ID_REV_CHIP_ID_7800_)
ret = lan78xx_write_reg(dev, HW_CFG, saved);
return retval;
}
static int lan78xx_read_raw_otp(struct lan78xx_net *dev, u32 offset,
u32 length, u8 *data)
{
int i;
u32 buf;
unsigned long timeout;
lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
if (buf & OTP_PWR_DN_PWRDN_N_) {
/* clear it and wait to be cleared */
lan78xx_write_reg(dev, OTP_PWR_DN, 0);
timeout = jiffies + HZ;
do {
usleep_range(1, 10);
lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
if (time_after(jiffies, timeout)) {
netdev_warn(dev->net,
"timeout on OTP_PWR_DN");
return -EIO;
}
} while (buf & OTP_PWR_DN_PWRDN_N_);
}
for (i = 0; i < length; i++) {
lan78xx_write_reg(dev, OTP_ADDR1,
((offset + i) >> 8) & OTP_ADDR1_15_11);
lan78xx_write_reg(dev, OTP_ADDR2,
((offset + i) & OTP_ADDR2_10_3));
lan78xx_write_reg(dev, OTP_FUNC_CMD, OTP_FUNC_CMD_READ_);
lan78xx_write_reg(dev, OTP_CMD_GO, OTP_CMD_GO_GO_);
timeout = jiffies + HZ;
do {
udelay(1);
lan78xx_read_reg(dev, OTP_STATUS, &buf);
if (time_after(jiffies, timeout)) {
netdev_warn(dev->net,
"timeout on OTP_STATUS");
return -EIO;
}
} while (buf & OTP_STATUS_BUSY_);
lan78xx_read_reg(dev, OTP_RD_DATA, &buf);
data[i] = (u8)(buf & 0xFF);
}
return 0;
}
static int lan78xx_write_raw_otp(struct lan78xx_net *dev, u32 offset,
u32 length, u8 *data)
{
int i;
u32 buf;
unsigned long timeout;
lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
if (buf & OTP_PWR_DN_PWRDN_N_) {
/* clear it and wait to be cleared */
lan78xx_write_reg(dev, OTP_PWR_DN, 0);
timeout = jiffies + HZ;
do {
udelay(1);
lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
if (time_after(jiffies, timeout)) {
netdev_warn(dev->net,
"timeout on OTP_PWR_DN completion");
return -EIO;
}
} while (buf & OTP_PWR_DN_PWRDN_N_);
}
/* set to BYTE program mode */
lan78xx_write_reg(dev, OTP_PRGM_MODE, OTP_PRGM_MODE_BYTE_);
for (i = 0; i < length; i++) {
lan78xx_write_reg(dev, OTP_ADDR1,
((offset + i) >> 8) & OTP_ADDR1_15_11);
lan78xx_write_reg(dev, OTP_ADDR2,
((offset + i) & OTP_ADDR2_10_3));
lan78xx_write_reg(dev, OTP_PRGM_DATA, data[i]);
lan78xx_write_reg(dev, OTP_TST_CMD, OTP_TST_CMD_PRGVRFY_);
lan78xx_write_reg(dev, OTP_CMD_GO, OTP_CMD_GO_GO_);
timeout = jiffies + HZ;
do {
udelay(1);
lan78xx_read_reg(dev, OTP_STATUS, &buf);
if (time_after(jiffies, timeout)) {
netdev_warn(dev->net,
"Timeout on OTP_STATUS completion");
return -EIO;
}
} while (buf & OTP_STATUS_BUSY_);
}
return 0;
}
static int lan78xx_read_otp(struct lan78xx_net *dev, u32 offset,
u32 length, u8 *data)
{
u8 sig;
int ret;
ret = lan78xx_read_raw_otp(dev, 0, 1, &sig);
if (ret == 0) {
if (sig == OTP_INDICATOR_2)
offset += 0x100;
else if (sig != OTP_INDICATOR_1)
ret = -EINVAL;
if (!ret)
ret = lan78xx_read_raw_otp(dev, offset, length, data);
}
return ret;
}
static int lan78xx_dataport_wait_not_busy(struct lan78xx_net *dev)
{
int i, ret;
for (i = 0; i < 100; i++) {