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sstep.c
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sstep.c
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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Single-step support.
*
* Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
*/
#include <linux/kernel.h>
#include <linux/kprobes.h>
#include <linux/ptrace.h>
#include <linux/prefetch.h>
#include <asm/sstep.h>
#include <asm/processor.h>
#include <linux/uaccess.h>
#include <asm/cpu_has_feature.h>
#include <asm/cputable.h>
#include <asm/disassemble.h>
extern char system_call_common[];
extern char system_call_vectored_emulate[];
#ifdef CONFIG_PPC64
/* Bits in SRR1 that are copied from MSR */
#define MSR_MASK 0xffffffff87c0ffffUL
#else
#define MSR_MASK 0x87c0ffff
#endif
/* Bits in XER */
#define XER_SO 0x80000000U
#define XER_OV 0x40000000U
#define XER_CA 0x20000000U
#define XER_OV32 0x00080000U
#define XER_CA32 0x00040000U
#ifdef CONFIG_VSX
#define VSX_REGISTER_XTP(rd) ((((rd) & 1) << 5) | ((rd) & 0xfe))
#endif
#ifdef CONFIG_PPC_FPU
/*
* Functions in ldstfp.S
*/
extern void get_fpr(int rn, double *p);
extern void put_fpr(int rn, const double *p);
extern void get_vr(int rn, __vector128 *p);
extern void put_vr(int rn, __vector128 *p);
extern void load_vsrn(int vsr, const void *p);
extern void store_vsrn(int vsr, void *p);
extern void conv_sp_to_dp(const float *sp, double *dp);
extern void conv_dp_to_sp(const double *dp, float *sp);
#endif
#ifdef __powerpc64__
/*
* Functions in quad.S
*/
extern int do_lq(unsigned long ea, unsigned long *regs);
extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
extern int do_lqarx(unsigned long ea, unsigned long *regs);
extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
unsigned int *crp);
#endif
#ifdef __LITTLE_ENDIAN__
#define IS_LE 1
#define IS_BE 0
#else
#define IS_LE 0
#define IS_BE 1
#endif
/*
* Emulate the truncation of 64 bit values in 32-bit mode.
*/
static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
unsigned long val)
{
#ifdef __powerpc64__
if ((msr & MSR_64BIT) == 0)
val &= 0xffffffffUL;
#endif
return val;
}
/*
* Determine whether a conditional branch instruction would branch.
*/
static nokprobe_inline int branch_taken(unsigned int instr,
const struct pt_regs *regs,
struct instruction_op *op)
{
unsigned int bo = (instr >> 21) & 0x1f;
unsigned int bi;
if ((bo & 4) == 0) {
/* decrement counter */
op->type |= DECCTR;
if (((bo >> 1) & 1) ^ (regs->ctr == 1))
return 0;
}
if ((bo & 0x10) == 0) {
/* check bit from CR */
bi = (instr >> 16) & 0x1f;
if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
return 0;
}
return 1;
}
static nokprobe_inline long address_ok(struct pt_regs *regs,
unsigned long ea, int nb)
{
if (!user_mode(regs))
return 1;
if (__access_ok(ea, nb))
return 1;
if (__access_ok(ea, 1))
/* Access overlaps the end of the user region */
regs->dar = TASK_SIZE_MAX - 1;
else
regs->dar = ea;
return 0;
}
/*
* Calculate effective address for a D-form instruction
*/
static nokprobe_inline unsigned long dform_ea(unsigned int instr,
const struct pt_regs *regs)
{
int ra;
unsigned long ea;
ra = (instr >> 16) & 0x1f;
ea = (signed short) instr; /* sign-extend */
if (ra)
ea += regs->gpr[ra];
return ea;
}
#ifdef __powerpc64__
/*
* Calculate effective address for a DS-form instruction
*/
static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
const struct pt_regs *regs)
{
int ra;
unsigned long ea;
ra = (instr >> 16) & 0x1f;
ea = (signed short) (instr & ~3); /* sign-extend */
if (ra)
ea += regs->gpr[ra];
return ea;
}
/*
* Calculate effective address for a DQ-form instruction
*/
static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
const struct pt_regs *regs)
{
int ra;
unsigned long ea;
ra = (instr >> 16) & 0x1f;
ea = (signed short) (instr & ~0xf); /* sign-extend */
if (ra)
ea += regs->gpr[ra];
return ea;
}
#endif /* __powerpc64 */
/*
* Calculate effective address for an X-form instruction
*/
static nokprobe_inline unsigned long xform_ea(unsigned int instr,
const struct pt_regs *regs)
{
int ra, rb;
unsigned long ea;
ra = (instr >> 16) & 0x1f;
rb = (instr >> 11) & 0x1f;
ea = regs->gpr[rb];
if (ra)
ea += regs->gpr[ra];
return ea;
}
/*
* Calculate effective address for a MLS:D-form / 8LS:D-form
* prefixed instruction
*/
static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
unsigned int suffix,
const struct pt_regs *regs)
{
int ra, prefix_r;
unsigned int dd;
unsigned long ea, d0, d1, d;
prefix_r = GET_PREFIX_R(instr);
ra = GET_PREFIX_RA(suffix);
d0 = instr & 0x3ffff;
d1 = suffix & 0xffff;
d = (d0 << 16) | d1;
/*
* sign extend a 34 bit number
*/
dd = (unsigned int)(d >> 2);
ea = (signed int)dd;
ea = (ea << 2) | (d & 0x3);
if (!prefix_r && ra)
ea += regs->gpr[ra];
else if (!prefix_r && !ra)
; /* Leave ea as is */
else if (prefix_r)
ea += regs->nip;
/*
* (prefix_r && ra) is an invalid form. Should already be
* checked for by caller!
*/
return ea;
}
/*
* Return the largest power of 2, not greater than sizeof(unsigned long),
* such that x is a multiple of it.
*/
static nokprobe_inline unsigned long max_align(unsigned long x)
{
x |= sizeof(unsigned long);
return x & -x; /* isolates rightmost bit */
}
static nokprobe_inline unsigned long byterev_2(unsigned long x)
{
return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
}
static nokprobe_inline unsigned long byterev_4(unsigned long x)
{
return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
((x & 0xff00) << 8) | ((x & 0xff) << 24);
}
#ifdef __powerpc64__
static nokprobe_inline unsigned long byterev_8(unsigned long x)
{
return (byterev_4(x) << 32) | byterev_4(x >> 32);
}
#endif
static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
{
switch (nb) {
case 2:
*(u16 *)ptr = byterev_2(*(u16 *)ptr);
break;
case 4:
*(u32 *)ptr = byterev_4(*(u32 *)ptr);
break;
#ifdef __powerpc64__
case 8:
*(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
break;
case 16: {
unsigned long *up = (unsigned long *)ptr;
unsigned long tmp;
tmp = byterev_8(up[0]);
up[0] = byterev_8(up[1]);
up[1] = tmp;
break;
}
case 32: {
unsigned long *up = (unsigned long *)ptr;
unsigned long tmp;
tmp = byterev_8(up[0]);
up[0] = byterev_8(up[3]);
up[3] = tmp;
tmp = byterev_8(up[2]);
up[2] = byterev_8(up[1]);
up[1] = tmp;
break;
}
#endif
default:
WARN_ON_ONCE(1);
}
}
static nokprobe_inline int read_mem_aligned(unsigned long *dest,
unsigned long ea, int nb,
struct pt_regs *regs)
{
int err = 0;
unsigned long x = 0;
switch (nb) {
case 1:
err = __get_user(x, (unsigned char __user *) ea);
break;
case 2:
err = __get_user(x, (unsigned short __user *) ea);
break;
case 4:
err = __get_user(x, (unsigned int __user *) ea);
break;
#ifdef __powerpc64__
case 8:
err = __get_user(x, (unsigned long __user *) ea);
break;
#endif
}
if (!err)
*dest = x;
else
regs->dar = ea;
return err;
}
/*
* Copy from userspace to a buffer, using the largest possible
* aligned accesses, up to sizeof(long).
*/
static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb,
struct pt_regs *regs)
{
int err = 0;
int c;
for (; nb > 0; nb -= c) {
c = max_align(ea);
if (c > nb)
c = max_align(nb);
switch (c) {
case 1:
err = __get_user(*dest, (unsigned char __user *) ea);
break;
case 2:
err = __get_user(*(u16 *)dest,
(unsigned short __user *) ea);
break;
case 4:
err = __get_user(*(u32 *)dest,
(unsigned int __user *) ea);
break;
#ifdef __powerpc64__
case 8:
err = __get_user(*(unsigned long *)dest,
(unsigned long __user *) ea);
break;
#endif
}
if (err) {
regs->dar = ea;
return err;
}
dest += c;
ea += c;
}
return 0;
}
static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
unsigned long ea, int nb,
struct pt_regs *regs)
{
union {
unsigned long ul;
u8 b[sizeof(unsigned long)];
} u;
int i;
int err;
u.ul = 0;
i = IS_BE ? sizeof(unsigned long) - nb : 0;
err = copy_mem_in(&u.b[i], ea, nb, regs);
if (!err)
*dest = u.ul;
return err;
}
/*
* Read memory at address ea for nb bytes, return 0 for success
* or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
* If nb < sizeof(long), the result is right-justified on BE systems.
*/
static int read_mem(unsigned long *dest, unsigned long ea, int nb,
struct pt_regs *regs)
{
if (!address_ok(regs, ea, nb))
return -EFAULT;
if ((ea & (nb - 1)) == 0)
return read_mem_aligned(dest, ea, nb, regs);
return read_mem_unaligned(dest, ea, nb, regs);
}
NOKPROBE_SYMBOL(read_mem);
static nokprobe_inline int write_mem_aligned(unsigned long val,
unsigned long ea, int nb,
struct pt_regs *regs)
{
int err = 0;
switch (nb) {
case 1:
err = __put_user(val, (unsigned char __user *) ea);
break;
case 2:
err = __put_user(val, (unsigned short __user *) ea);
break;
case 4:
err = __put_user(val, (unsigned int __user *) ea);
break;
#ifdef __powerpc64__
case 8:
err = __put_user(val, (unsigned long __user *) ea);
break;
#endif
}
if (err)
regs->dar = ea;
return err;
}
/*
* Copy from a buffer to userspace, using the largest possible
* aligned accesses, up to sizeof(long).
*/
static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb,
struct pt_regs *regs)
{
int err = 0;
int c;
for (; nb > 0; nb -= c) {
c = max_align(ea);
if (c > nb)
c = max_align(nb);
switch (c) {
case 1:
err = __put_user(*dest, (unsigned char __user *) ea);
break;
case 2:
err = __put_user(*(u16 *)dest,
(unsigned short __user *) ea);
break;
case 4:
err = __put_user(*(u32 *)dest,
(unsigned int __user *) ea);
break;
#ifdef __powerpc64__
case 8:
err = __put_user(*(unsigned long *)dest,
(unsigned long __user *) ea);
break;
#endif
}
if (err) {
regs->dar = ea;
return err;
}
dest += c;
ea += c;
}
return 0;
}
static nokprobe_inline int write_mem_unaligned(unsigned long val,
unsigned long ea, int nb,
struct pt_regs *regs)
{
union {
unsigned long ul;
u8 b[sizeof(unsigned long)];
} u;
int i;
u.ul = val;
i = IS_BE ? sizeof(unsigned long) - nb : 0;
return copy_mem_out(&u.b[i], ea, nb, regs);
}
/*
* Write memory at address ea for nb bytes, return 0 for success
* or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
*/
static int write_mem(unsigned long val, unsigned long ea, int nb,
struct pt_regs *regs)
{
if (!address_ok(regs, ea, nb))
return -EFAULT;
if ((ea & (nb - 1)) == 0)
return write_mem_aligned(val, ea, nb, regs);
return write_mem_unaligned(val, ea, nb, regs);
}
NOKPROBE_SYMBOL(write_mem);
#ifdef CONFIG_PPC_FPU
/*
* These access either the real FP register or the image in the
* thread_struct, depending on regs->msr & MSR_FP.
*/
static int do_fp_load(struct instruction_op *op, unsigned long ea,
struct pt_regs *regs, bool cross_endian)
{
int err, rn, nb;
union {
int i;
unsigned int u;
float f;
double d[2];
unsigned long l[2];
u8 b[2 * sizeof(double)];
} u;
nb = GETSIZE(op->type);
if (!address_ok(regs, ea, nb))
return -EFAULT;
rn = op->reg;
err = copy_mem_in(u.b, ea, nb, regs);
if (err)
return err;
if (unlikely(cross_endian)) {
do_byte_reverse(u.b, min(nb, 8));
if (nb == 16)
do_byte_reverse(&u.b[8], 8);
}
preempt_disable();
if (nb == 4) {
if (op->type & FPCONV)
conv_sp_to_dp(&u.f, &u.d[0]);
else if (op->type & SIGNEXT)
u.l[0] = u.i;
else
u.l[0] = u.u;
}
if (regs->msr & MSR_FP)
put_fpr(rn, &u.d[0]);
else
current->thread.TS_FPR(rn) = u.l[0];
if (nb == 16) {
/* lfdp */
rn |= 1;
if (regs->msr & MSR_FP)
put_fpr(rn, &u.d[1]);
else
current->thread.TS_FPR(rn) = u.l[1];
}
preempt_enable();
return 0;
}
NOKPROBE_SYMBOL(do_fp_load);
static int do_fp_store(struct instruction_op *op, unsigned long ea,
struct pt_regs *regs, bool cross_endian)
{
int rn, nb;
union {
unsigned int u;
float f;
double d[2];
unsigned long l[2];
u8 b[2 * sizeof(double)];
} u;
nb = GETSIZE(op->type);
if (!address_ok(regs, ea, nb))
return -EFAULT;
rn = op->reg;
preempt_disable();
if (regs->msr & MSR_FP)
get_fpr(rn, &u.d[0]);
else
u.l[0] = current->thread.TS_FPR(rn);
if (nb == 4) {
if (op->type & FPCONV)
conv_dp_to_sp(&u.d[0], &u.f);
else
u.u = u.l[0];
}
if (nb == 16) {
rn |= 1;
if (regs->msr & MSR_FP)
get_fpr(rn, &u.d[1]);
else
u.l[1] = current->thread.TS_FPR(rn);
}
preempt_enable();
if (unlikely(cross_endian)) {
do_byte_reverse(u.b, min(nb, 8));
if (nb == 16)
do_byte_reverse(&u.b[8], 8);
}
return copy_mem_out(u.b, ea, nb, regs);
}
NOKPROBE_SYMBOL(do_fp_store);
#endif
#ifdef CONFIG_ALTIVEC
/* For Altivec/VMX, no need to worry about alignment */
static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
int size, struct pt_regs *regs,
bool cross_endian)
{
int err;
union {
__vector128 v;
u8 b[sizeof(__vector128)];
} u = {};
if (!address_ok(regs, ea & ~0xfUL, 16))
return -EFAULT;
/* align to multiple of size */
ea &= ~(size - 1);
err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
if (err)
return err;
if (unlikely(cross_endian))
do_byte_reverse(&u.b[ea & 0xf], size);
preempt_disable();
if (regs->msr & MSR_VEC)
put_vr(rn, &u.v);
else
current->thread.vr_state.vr[rn] = u.v;
preempt_enable();
return 0;
}
static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
int size, struct pt_regs *regs,
bool cross_endian)
{
union {
__vector128 v;
u8 b[sizeof(__vector128)];
} u;
if (!address_ok(regs, ea & ~0xfUL, 16))
return -EFAULT;
/* align to multiple of size */
ea &= ~(size - 1);
preempt_disable();
if (regs->msr & MSR_VEC)
get_vr(rn, &u.v);
else
u.v = current->thread.vr_state.vr[rn];
preempt_enable();
if (unlikely(cross_endian))
do_byte_reverse(&u.b[ea & 0xf], size);
return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
}
#endif /* CONFIG_ALTIVEC */
#ifdef __powerpc64__
static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
int reg, bool cross_endian)
{
int err;
if (!address_ok(regs, ea, 16))
return -EFAULT;
/* if aligned, should be atomic */
if ((ea & 0xf) == 0) {
err = do_lq(ea, ®s->gpr[reg]);
} else {
err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs);
if (!err)
err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs);
}
if (!err && unlikely(cross_endian))
do_byte_reverse(®s->gpr[reg], 16);
return err;
}
static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
int reg, bool cross_endian)
{
int err;
unsigned long vals[2];
if (!address_ok(regs, ea, 16))
return -EFAULT;
vals[0] = regs->gpr[reg];
vals[1] = regs->gpr[reg + 1];
if (unlikely(cross_endian))
do_byte_reverse(vals, 16);
/* if aligned, should be atomic */
if ((ea & 0xf) == 0)
return do_stq(ea, vals[0], vals[1]);
err = write_mem(vals[IS_LE], ea, 8, regs);
if (!err)
err = write_mem(vals[IS_BE], ea + 8, 8, regs);
return err;
}
#endif /* __powerpc64 */
#ifdef CONFIG_VSX
void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
const void *mem, bool rev)
{
int size, read_size;
int i, j;
const unsigned int *wp;
const unsigned short *hp;
const unsigned char *bp;
size = GETSIZE(op->type);
reg->d[0] = reg->d[1] = 0;
switch (op->element_size) {
case 32:
/* [p]lxvp[x] */
case 16:
/* whole vector; lxv[x] or lxvl[l] */
if (size == 0)
break;
memcpy(reg, mem, size);
if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
rev = !rev;
if (rev)
do_byte_reverse(reg, size);
break;
case 8:
/* scalar loads, lxvd2x, lxvdsx */
read_size = (size >= 8) ? 8 : size;
i = IS_LE ? 8 : 8 - read_size;
memcpy(®->b[i], mem, read_size);
if (rev)
do_byte_reverse(®->b[i], 8);
if (size < 8) {
if (op->type & SIGNEXT) {
/* size == 4 is the only case here */
reg->d[IS_LE] = (signed int) reg->d[IS_LE];
} else if (op->vsx_flags & VSX_FPCONV) {
preempt_disable();
conv_sp_to_dp(®->fp[1 + IS_LE],
®->dp[IS_LE]);
preempt_enable();
}
} else {
if (size == 16) {
unsigned long v = *(unsigned long *)(mem + 8);
reg->d[IS_BE] = !rev ? v : byterev_8(v);
} else if (op->vsx_flags & VSX_SPLAT)
reg->d[IS_BE] = reg->d[IS_LE];
}
break;
case 4:
/* lxvw4x, lxvwsx */
wp = mem;
for (j = 0; j < size / 4; ++j) {
i = IS_LE ? 3 - j : j;
reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
}
if (op->vsx_flags & VSX_SPLAT) {
u32 val = reg->w[IS_LE ? 3 : 0];
for (; j < 4; ++j) {
i = IS_LE ? 3 - j : j;
reg->w[i] = val;
}
}
break;
case 2:
/* lxvh8x */
hp = mem;
for (j = 0; j < size / 2; ++j) {
i = IS_LE ? 7 - j : j;
reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
}
break;
case 1:
/* lxvb16x */
bp = mem;
for (j = 0; j < size; ++j) {
i = IS_LE ? 15 - j : j;
reg->b[i] = *bp++;
}
break;
}
}
EXPORT_SYMBOL_GPL(emulate_vsx_load);
NOKPROBE_SYMBOL(emulate_vsx_load);
void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
void *mem, bool rev)
{
int size, write_size;
int i, j;
union vsx_reg buf;
unsigned int *wp;
unsigned short *hp;
unsigned char *bp;
size = GETSIZE(op->type);
switch (op->element_size) {
case 32:
/* [p]stxvp[x] */
if (size == 0)
break;
if (rev) {
/* reverse 32 bytes */
union vsx_reg buf32[2];
buf32[0].d[0] = byterev_8(reg[1].d[1]);
buf32[0].d[1] = byterev_8(reg[1].d[0]);
buf32[1].d[0] = byterev_8(reg[0].d[1]);
buf32[1].d[1] = byterev_8(reg[0].d[0]);
memcpy(mem, buf32, size);
} else {
memcpy(mem, reg, size);
}
break;
case 16:
/* stxv, stxvx, stxvl, stxvll */
if (size == 0)
break;
if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
rev = !rev;
if (rev) {
/* reverse 16 bytes */
buf.d[0] = byterev_8(reg->d[1]);
buf.d[1] = byterev_8(reg->d[0]);
reg = &buf;
}
memcpy(mem, reg, size);
break;
case 8:
/* scalar stores, stxvd2x */
write_size = (size >= 8) ? 8 : size;
i = IS_LE ? 8 : 8 - write_size;
if (size < 8 && op->vsx_flags & VSX_FPCONV) {
buf.d[0] = buf.d[1] = 0;
preempt_disable();
conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]);
preempt_enable();
reg = &buf;
}
memcpy(mem, ®->b[i], write_size);
if (size == 16)
memcpy(mem + 8, ®->d[IS_BE], 8);
if (unlikely(rev)) {
do_byte_reverse(mem, write_size);
if (size == 16)
do_byte_reverse(mem + 8, 8);
}
break;
case 4:
/* stxvw4x */
wp = mem;
for (j = 0; j < size / 4; ++j) {
i = IS_LE ? 3 - j : j;
*wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
}
break;
case 2:
/* stxvh8x */
hp = mem;
for (j = 0; j < size / 2; ++j) {
i = IS_LE ? 7 - j : j;
*hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
}
break;
case 1:
/* stvxb16x */
bp = mem;
for (j = 0; j < size; ++j) {
i = IS_LE ? 15 - j : j;
*bp++ = reg->b[i];
}
break;
}
}
EXPORT_SYMBOL_GPL(emulate_vsx_store);
NOKPROBE_SYMBOL(emulate_vsx_store);
static nokprobe_inline int do_vsx_load(struct instruction_op *op,
unsigned long ea, struct pt_regs *regs,
bool cross_endian)
{
int reg = op->reg;
int i, j, nr_vsx_regs;
u8 mem[32];
union vsx_reg buf[2];
int size = GETSIZE(op->type);
if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
return -EFAULT;
nr_vsx_regs = max(1ul, size / sizeof(__vector128));
emulate_vsx_load(op, buf, mem, cross_endian);
preempt_disable();
if (reg < 32) {
/* FP regs + extensions */
if (regs->msr & MSR_FP) {
for (i = 0; i < nr_vsx_regs; i++) {
j = IS_LE ? nr_vsx_regs - i - 1 : i;
load_vsrn(reg + i, &buf[j].v);
}
} else {
for (i = 0; i < nr_vsx_regs; i++) {
j = IS_LE ? nr_vsx_regs - i - 1 : i;
current->thread.fp_state.fpr[reg + i][0] = buf[j].d[0];
current->thread.fp_state.fpr[reg + i][1] = buf[j].d[1];
}
}
} else {
if (regs->msr & MSR_VEC) {
for (i = 0; i < nr_vsx_regs; i++) {
j = IS_LE ? nr_vsx_regs - i - 1 : i;
load_vsrn(reg + i, &buf[j].v);
}
} else {
for (i = 0; i < nr_vsx_regs; i++) {
j = IS_LE ? nr_vsx_regs - i - 1 : i;
current->thread.vr_state.vr[reg - 32 + i] = buf[j].v;
}
}
}
preempt_enable();
return 0;
}
static nokprobe_inline int do_vsx_store(struct instruction_op *op,
unsigned long ea, struct pt_regs *regs,
bool cross_endian)
{
int reg = op->reg;
int i, j, nr_vsx_regs;
u8 mem[32];
union vsx_reg buf[2];
int size = GETSIZE(op->type);
if (!address_ok(regs, ea, size))
return -EFAULT;
nr_vsx_regs = max(1ul, size / sizeof(__vector128));
preempt_disable();
if (reg < 32) {
/* FP regs + extensions */
if (regs->msr & MSR_FP) {
for (i = 0; i < nr_vsx_regs; i++) {
j = IS_LE ? nr_vsx_regs - i - 1 : i;
store_vsrn(reg + i, &buf[j].v);
}
} else {
for (i = 0; i < nr_vsx_regs; i++) {
j = IS_LE ? nr_vsx_regs - i - 1 : i;
buf[j].d[0] = current->thread.fp_state.fpr[reg + i][0];
buf[j].d[1] = current->thread.fp_state.fpr[reg + i][1];
}
}
} else {
if (regs->msr & MSR_VEC) {
for (i = 0; i < nr_vsx_regs; i++) {
j = IS_LE ? nr_vsx_regs - i - 1 : i;
store_vsrn(reg + i, &buf[j].v);
}
} else {
for (i = 0; i < nr_vsx_regs; i++) {
j = IS_LE ? nr_vsx_regs - i - 1 : i;
buf[j].v = current->thread.vr_state.vr[reg - 32 + i];
}
}
}
preempt_enable();
emulate_vsx_store(op, buf, mem, cross_endian);
return copy_mem_out(mem, ea, size, regs);
}
#endif /* CONFIG_VSX */
int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
{
int err;
unsigned long i, size;
#ifdef __powerpc64__
size = ppc64_caches.l1d.block_size;
if (!(regs->msr & MSR_64BIT))
ea &= 0xffffffffUL;
#else
size = L1_CACHE_BYTES;
#endif