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traps.c
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traps.c
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/*
* xen/arch/arm/traps.c
*
* ARM Trap handlers
*
* Copyright (c) 2011 Citrix Systems.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <xen/domain_page.h>
#include <xen/errno.h>
#include <xen/hypercall.h>
#include <xen/init.h>
#include <xen/iocap.h>
#include <xen/ioreq.h>
#include <xen/irq.h>
#include <xen/lib.h>
#include <xen/mem_access.h>
#include <xen/mm.h>
#include <xen/param.h>
#include <xen/perfc.h>
#include <xen/smp.h>
#include <xen/softirq.h>
#include <xen/string.h>
#include <xen/symbols.h>
#include <xen/version.h>
#include <xen/virtual_region.h>
#include <public/sched.h>
#include <public/xen.h>
#include <asm/acpi.h>
#include <asm/cpuerrata.h>
#include <asm/cpufeature.h>
#include <asm/debugger.h>
#include <asm/event.h>
#include <asm/hsr.h>
#include <asm/mmio.h>
#include <asm/regs.h>
#include <asm/smccc.h>
#include <asm/traps.h>
#include <asm/vgic.h>
#include <asm/vtimer.h>
/* The base of the stack must always be double-word aligned, which means
* that both the kernel half of struct cpu_user_regs (which is pushed in
* entry.S) and struct cpu_info (which lives at the bottom of a Xen
* stack) must be doubleword-aligned in size. */
static void __init __maybe_unused build_assertions(void)
{
#ifdef CONFIG_ARM_64
BUILD_BUG_ON((sizeof (struct cpu_user_regs)) & 0xf);
BUILD_BUG_ON((offsetof(struct cpu_user_regs, spsr_el1)) & 0xf);
BUILD_BUG_ON((offsetof(struct cpu_user_regs, lr)) & 0xf);
BUILD_BUG_ON((sizeof (struct cpu_info)) & 0xf);
#else
BUILD_BUG_ON((sizeof (struct cpu_user_regs)) & 0x7);
BUILD_BUG_ON((offsetof(struct cpu_user_regs, sp_usr)) & 0x7);
BUILD_BUG_ON((sizeof (struct cpu_info)) & 0x7);
#endif
}
#ifdef CONFIG_ARM_32
static int debug_stack_lines = 20;
#define stack_words_per_line 8
#else
static int debug_stack_lines = 40;
#define stack_words_per_line 4
#endif
integer_param("debug_stack_lines", debug_stack_lines);
static enum {
TRAP,
NATIVE,
} vwfi;
static int __init parse_vwfi(const char *s)
{
if ( !strcmp(s, "native") )
vwfi = NATIVE;
else
vwfi = TRAP;
return 0;
}
custom_param("vwfi", parse_vwfi);
register_t get_default_hcr_flags(void)
{
return (HCR_PTW|HCR_BSU_INNER|HCR_AMO|HCR_IMO|HCR_FMO|HCR_VM|
(vwfi != NATIVE ? (HCR_TWI|HCR_TWE) : 0) |
HCR_TID3|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB|HCR_TSW);
}
static enum {
SERRORS_DIVERSE,
SERRORS_PANIC,
} serrors_op = SERRORS_DIVERSE;
static int __init parse_serrors_behavior(const char *str)
{
if ( !strcmp(str, "panic") )
serrors_op = SERRORS_PANIC;
else if ( !strcmp(str, "diverse") )
serrors_op = SERRORS_DIVERSE;
else
return -EINVAL;
return 0;
}
custom_param("serrors", parse_serrors_behavior);
static int __init update_serrors_cpu_caps(void)
{
if ( serrors_op != SERRORS_DIVERSE )
cpus_set_cap(SKIP_SYNCHRONIZE_SERROR_ENTRY_EXIT);
return 0;
}
__initcall(update_serrors_cpu_caps);
void init_traps(void)
{
/*
* Setup Hyp vector base. Note they might get updated with the
* branch predictor hardening.
*/
WRITE_SYSREG((vaddr_t)hyp_traps_vector, VBAR_EL2);
/* Trap Debug and Performance Monitor accesses */
WRITE_SYSREG(HDCR_TDRA|HDCR_TDOSA|HDCR_TDA|HDCR_TPM|HDCR_TPMCR,
MDCR_EL2);
/* Trap CP15 c15 used for implementation defined registers */
WRITE_SYSREG(HSTR_T(15), HSTR_EL2);
/* Trap all coprocessor registers (0-13) except cp10 and
* cp11 for VFP.
*
* /!\ All coprocessors except cp10 and cp11 cannot be used in Xen.
*
* On ARM64 the TCPx bits which we set here (0..9,12,13) are all
* RES1, i.e. they would trap whether we did this write or not.
*/
WRITE_SYSREG((HCPTR_CP_MASK & ~(HCPTR_CP(10) | HCPTR_CP(11))) |
HCPTR_TTA | HCPTR_TAM,
CPTR_EL2);
/*
* Configure HCR_EL2 with the bare minimum to run Xen until a guest
* is scheduled. {A,I,F}MO bits are set to allow EL2 receiving
* interrupts.
*/
WRITE_SYSREG(HCR_AMO | HCR_FMO | HCR_IMO, HCR_EL2);
isb();
}
void __div0(void)
{
printk("Division by zero in hypervisor.\n");
BUG();
}
/* XXX could/should be common code */
static void print_xen_info(void)
{
char taint_str[TAINT_STRING_MAX_LEN];
printk("----[ Xen-%d.%d%s %s %s %s ]----\n",
xen_major_version(), xen_minor_version(), xen_extra_version(),
#ifdef CONFIG_ARM_32
"arm32",
#else
"arm64",
#endif
xen_build_info(), print_tainted(taint_str));
}
#ifdef CONFIG_ARM_32
static inline bool is_zero_register(int reg)
{
/* There is no zero register for ARM32 */
return false;
}
#else
static inline bool is_zero_register(int reg)
{
/*
* For store/load and sysreg instruction, the encoding 31 always
* corresponds to {w,x}zr which is the zero register.
*/
return (reg == 31);
}
#endif
/*
* Returns a pointer to the given register value in regs, taking the
* processor mode (CPSR) into account.
*
* Note that this function should not be used directly but via
* {get,set}_user_reg.
*/
static register_t *select_user_reg(struct cpu_user_regs *regs, int reg)
{
BUG_ON( !guest_mode(regs) );
#ifdef CONFIG_ARM_32
/*
* We rely heavily on the layout of cpu_user_regs to avoid having
* to handle all of the registers individually. Use BUILD_BUG_ON to
* ensure that things which expect are contiguous actually are.
*/
#define REGOFFS(R) offsetof(struct cpu_user_regs, R)
switch ( reg )
{
case 0 ... 7: /* Unbanked registers */
BUILD_BUG_ON(REGOFFS(r0) + 7*sizeof(register_t) != REGOFFS(r7));
return ®s->r0 + reg;
case 8 ... 12: /* Register banked in FIQ mode */
BUILD_BUG_ON(REGOFFS(r8_fiq) + 4*sizeof(register_t) != REGOFFS(r12_fiq));
if ( fiq_mode(regs) )
return ®s->r8_fiq + reg - 8;
else
return ®s->r8 + reg - 8;
case 13 ... 14: /* Banked SP + LR registers */
BUILD_BUG_ON(REGOFFS(sp_fiq) + 1*sizeof(register_t) != REGOFFS(lr_fiq));
BUILD_BUG_ON(REGOFFS(sp_irq) + 1*sizeof(register_t) != REGOFFS(lr_irq));
BUILD_BUG_ON(REGOFFS(sp_svc) + 1*sizeof(register_t) != REGOFFS(lr_svc));
BUILD_BUG_ON(REGOFFS(sp_abt) + 1*sizeof(register_t) != REGOFFS(lr_abt));
BUILD_BUG_ON(REGOFFS(sp_und) + 1*sizeof(register_t) != REGOFFS(lr_und));
switch ( regs->cpsr & PSR_MODE_MASK )
{
case PSR_MODE_USR:
case PSR_MODE_SYS: /* Sys regs are the usr regs */
if ( reg == 13 )
return ®s->sp_usr;
else /* lr_usr == lr in a user frame */
return ®s->lr;
case PSR_MODE_FIQ:
return ®s->sp_fiq + reg - 13;
case PSR_MODE_IRQ:
return ®s->sp_irq + reg - 13;
case PSR_MODE_SVC:
return ®s->sp_svc + reg - 13;
case PSR_MODE_ABT:
return ®s->sp_abt + reg - 13;
case PSR_MODE_UND:
return ®s->sp_und + reg - 13;
case PSR_MODE_MON:
case PSR_MODE_HYP:
default:
BUG();
}
case 15: /* PC */
return ®s->pc;
default:
BUG();
}
#undef REGOFFS
#else
/*
* On 64-bit the syndrome register contains the register index as
* viewed in AArch64 state even if the trap was from AArch32 mode.
*/
BUG_ON(is_zero_register(reg)); /* Cannot be {w,x}zr */
return ®s->x0 + reg;
#endif
}
register_t get_user_reg(struct cpu_user_regs *regs, int reg)
{
if ( is_zero_register(reg) )
return 0;
return *select_user_reg(regs, reg);
}
void set_user_reg(struct cpu_user_regs *regs, int reg, register_t value)
{
if ( is_zero_register(reg) )
return;
*select_user_reg(regs, reg) = value;
}
static const char *decode_fsc(uint32_t fsc, int *level)
{
const char *msg = NULL;
switch ( fsc & 0x3f )
{
case FSC_FLT_TRANS ... FSC_FLT_TRANS + 3:
msg = "Translation fault";
*level = fsc & FSC_LL_MASK;
break;
case FSC_FLT_ACCESS ... FSC_FLT_ACCESS + 3:
msg = "Access fault";
*level = fsc & FSC_LL_MASK;
break;
case FSC_FLT_PERM ... FSC_FLT_PERM + 3:
msg = "Permission fault";
*level = fsc & FSC_LL_MASK;
break;
case FSC_SEA:
msg = "Synchronous External Abort";
break;
case FSC_SPE:
msg = "Memory Access Synchronous Parity Error";
break;
case FSC_APE:
msg = "Memory Access Asynchronous Parity Error";
break;
case FSC_SEATT ... FSC_SEATT + 3:
msg = "Sync. Ext. Abort Translation Table";
*level = fsc & FSC_LL_MASK;
break;
case FSC_SPETT ... FSC_SPETT + 3:
msg = "Sync. Parity. Error Translation Table";
*level = fsc & FSC_LL_MASK;
break;
case FSC_AF:
msg = "Alignment Fault";
break;
case FSC_DE:
msg = "Debug Event";
break;
case FSC_LKD:
msg = "Implementation Fault: Lockdown Abort";
break;
case FSC_CPR:
msg = "Implementation Fault: Coprocossor Abort";
break;
default:
msg = "Unknown Failure";
break;
}
return msg;
}
static const char *fsc_level_str(int level)
{
switch ( level )
{
case -1: return "";
case 1: return " at level 1";
case 2: return " at level 2";
case 3: return " at level 3";
default: return " (level invalid)";
}
}
void panic_PAR(uint64_t par)
{
const char *msg;
int level = -1;
int stage = par & PAR_STAGE2 ? 2 : 1;
int second_in_first = !!(par & PAR_STAGE21);
msg = decode_fsc( (par&PAR_FSC_MASK) >> PAR_FSC_SHIFT, &level);
printk("PAR: %016"PRIx64": %s stage %d%s%s\n",
par, msg,
stage,
second_in_first ? " during second stage lookup" : "",
fsc_level_str(level));
panic("Error during Hypervisor-to-physical address translation\n");
}
static void cpsr_switch_mode(struct cpu_user_regs *regs, int mode)
{
register_t sctlr = READ_SYSREG(SCTLR_EL1);
regs->cpsr &= ~(PSR_MODE_MASK|PSR_IT_MASK|PSR_JAZELLE|PSR_BIG_ENDIAN|PSR_THUMB);
regs->cpsr |= mode;
regs->cpsr |= PSR_IRQ_MASK;
if ( mode == PSR_MODE_ABT )
regs->cpsr |= PSR_ABT_MASK;
if ( sctlr & SCTLR_A32_ELx_TE )
regs->cpsr |= PSR_THUMB;
if ( sctlr & SCTLR_Axx_ELx_EE )
regs->cpsr |= PSR_BIG_ENDIAN;
}
static vaddr_t exception_handler32(vaddr_t offset)
{
register_t sctlr = READ_SYSREG(SCTLR_EL1);
if ( sctlr & SCTLR_A32_EL1_V )
return 0xffff0000 + offset;
else /* always have security exceptions */
return READ_SYSREG(VBAR_EL1) + offset;
}
/* Injects an Undefined Instruction exception into the current vcpu,
* PC is the exact address of the faulting instruction (without
* pipeline adjustments). See TakeUndefInstrException pseudocode in
* ARM ARM.
*/
static void inject_undef32_exception(struct cpu_user_regs *regs)
{
uint32_t spsr = regs->cpsr;
int is_thumb = (regs->cpsr & PSR_THUMB);
/* Saved PC points to the instruction past the faulting instruction. */
uint32_t return_offset = is_thumb ? 2 : 4;
BUG_ON( !is_32bit_domain(current->domain) );
/* Update processor mode */
cpsr_switch_mode(regs, PSR_MODE_UND);
/* Update banked registers */
regs->spsr_und = spsr;
regs->lr_und = regs->pc32 + return_offset;
/* Branch to exception vector */
regs->pc32 = exception_handler32(VECTOR32_UND);
}
/* Injects an Abort exception into the current vcpu, PC is the exact
* address of the faulting instruction (without pipeline
* adjustments). See TakePrefetchAbortException and
* TakeDataAbortException pseudocode in ARM ARM.
*/
static void inject_abt32_exception(struct cpu_user_regs *regs,
int prefetch,
register_t addr)
{
uint32_t spsr = regs->cpsr;
int is_thumb = (regs->cpsr & PSR_THUMB);
/* Saved PC points to the instruction past the faulting instruction. */
uint32_t return_offset = is_thumb ? 4 : 0;
register_t fsr;
BUG_ON( !is_32bit_domain(current->domain) );
cpsr_switch_mode(regs, PSR_MODE_ABT);
/* Update banked registers */
regs->spsr_abt = spsr;
regs->lr_abt = regs->pc32 + return_offset;
regs->pc32 = exception_handler32(prefetch ? VECTOR32_PABT : VECTOR32_DABT);
/* Inject a debug fault, best we can do right now */
if ( READ_SYSREG(TCR_EL1) & TTBCR_EAE )
fsr = FSR_LPAE | FSRL_STATUS_DEBUG;
else
fsr = FSRS_FS_DEBUG;
if ( prefetch )
{
/* Set IFAR and IFSR */
#ifdef CONFIG_ARM_32
WRITE_SYSREG(addr, IFAR);
WRITE_SYSREG(fsr, IFSR);
#else
/* FAR_EL1[63:32] is AArch32 register IFAR */
register_t far = READ_SYSREG(FAR_EL1) & 0xffffffffUL;
far |= addr << 32;
WRITE_SYSREG(far, FAR_EL1);
WRITE_SYSREG(fsr, IFSR32_EL2);
#endif
}
else
{
#ifdef CONFIG_ARM_32
/* Set DFAR and DFSR */
WRITE_SYSREG(addr, DFAR);
WRITE_SYSREG(fsr, DFSR);
#else
/* FAR_EL1[31:0] is AArch32 register DFAR */
register_t far = READ_SYSREG(FAR_EL1) & ~0xffffffffUL;
far |= addr;
WRITE_SYSREG(far, FAR_EL1);
/* ESR_EL1 is AArch32 register DFSR */
WRITE_SYSREG(fsr, ESR_EL1);
#endif
}
}
static void inject_dabt32_exception(struct cpu_user_regs *regs,
register_t addr)
{
inject_abt32_exception(regs, 0, addr);
}
static void inject_pabt32_exception(struct cpu_user_regs *regs,
register_t addr)
{
inject_abt32_exception(regs, 1, addr);
}
#ifdef CONFIG_ARM_64
/*
* Take care to call this while regs contains the original faulting
* state and not the (partially constructed) exception state.
*/
static vaddr_t exception_handler64(struct cpu_user_regs *regs, vaddr_t offset)
{
vaddr_t base = READ_SYSREG(VBAR_EL1);
if ( usr_mode(regs) )
base += VECTOR64_LOWER32_BASE;
else if ( psr_mode(regs->cpsr,PSR_MODE_EL0t) )
base += VECTOR64_LOWER64_BASE;
else /* Otherwise must be from kernel mode */
base += VECTOR64_CURRENT_SPx_BASE;
return base + offset;
}
/* Inject an undefined exception into a 64 bit guest */
void inject_undef64_exception(struct cpu_user_regs *regs, int instr_len)
{
vaddr_t handler;
const union hsr esr = {
.iss = 0,
.len = instr_len,
.ec = HSR_EC_UNKNOWN,
};
BUG_ON( is_32bit_domain(current->domain) );
handler = exception_handler64(regs, VECTOR64_SYNC_OFFSET);
regs->spsr_el1 = regs->cpsr;
regs->elr_el1 = regs->pc;
regs->cpsr = PSR_MODE_EL1h | PSR_ABT_MASK | PSR_FIQ_MASK | \
PSR_IRQ_MASK | PSR_DBG_MASK;
regs->pc = handler;
WRITE_SYSREG32(esr.bits, ESR_EL1);
}
/* Inject an abort exception into a 64 bit guest */
static void inject_abt64_exception(struct cpu_user_regs *regs,
int prefetch,
register_t addr,
int instr_len)
{
vaddr_t handler;
union hsr esr = {
.iss = 0,
.len = instr_len,
};
if ( psr_mode_is_user(regs) )
esr.ec = prefetch
? HSR_EC_INSTR_ABORT_LOWER_EL : HSR_EC_DATA_ABORT_LOWER_EL;
else
esr.ec = prefetch
? HSR_EC_INSTR_ABORT_CURR_EL : HSR_EC_DATA_ABORT_CURR_EL;
BUG_ON( is_32bit_domain(current->domain) );
handler = exception_handler64(regs, VECTOR64_SYNC_OFFSET);
regs->spsr_el1 = regs->cpsr;
regs->elr_el1 = regs->pc;
regs->cpsr = PSR_MODE_EL1h | PSR_ABT_MASK | PSR_FIQ_MASK | \
PSR_IRQ_MASK | PSR_DBG_MASK;
regs->pc = handler;
WRITE_SYSREG(addr, FAR_EL1);
WRITE_SYSREG32(esr.bits, ESR_EL1);
}
static void inject_dabt64_exception(struct cpu_user_regs *regs,
register_t addr,
int instr_len)
{
inject_abt64_exception(regs, 0, addr, instr_len);
}
static void inject_iabt64_exception(struct cpu_user_regs *regs,
register_t addr,
int instr_len)
{
inject_abt64_exception(regs, 1, addr, instr_len);
}
#endif
void inject_undef_exception(struct cpu_user_regs *regs, const union hsr hsr)
{
if ( is_32bit_domain(current->domain) )
inject_undef32_exception(regs);
#ifdef CONFIG_ARM_64
else
inject_undef64_exception(regs, hsr.len);
#endif
}
static void inject_iabt_exception(struct cpu_user_regs *regs,
register_t addr,
int instr_len)
{
if ( is_32bit_domain(current->domain) )
inject_pabt32_exception(regs, addr);
#ifdef CONFIG_ARM_64
else
inject_iabt64_exception(regs, addr, instr_len);
#endif
}
static void inject_dabt_exception(struct cpu_user_regs *regs,
register_t addr,
int instr_len)
{
if ( is_32bit_domain(current->domain) )
inject_dabt32_exception(regs, addr);
#ifdef CONFIG_ARM_64
else
inject_dabt64_exception(regs, addr, instr_len);
#endif
}
/*
* Inject a virtual Abort/SError into the guest.
*
* This should only be called with 'current'.
*/
static void inject_vabt_exception(struct vcpu *v)
{
struct cpu_user_regs *regs = guest_cpu_user_regs();
const union hsr hsr = { .bits = regs->hsr };
ASSERT(v == current);
/*
* SVC/HVC/SMC already have an adjusted PC (See ARM ARM DDI 0487A.j
* D1.10.1 for more details), which we need to correct in order to
* return to after having injected the SError.
*/
switch ( hsr.ec )
{
case HSR_EC_SVC32:
case HSR_EC_HVC32:
case HSR_EC_SMC32:
#ifdef CONFIG_ARM_64
case HSR_EC_SVC64:
case HSR_EC_HVC64:
case HSR_EC_SMC64:
#endif
regs->pc -= hsr.len ? 4 : 2;
break;
default:
break;
}
vcpu_hcr_set_flags(v, HCR_VA);
}
/*
* SError exception handler.
*
* A true parameter "guest" means that the SError is type#1 or type#2.
*
* @guest indicates whether this is a SError generated by the guest.
*
* If true, the SError was generated by the guest, so it is safe to continue
* and forward to the guest (if requested).
*
* If false, the SError was likely generated by the hypervisor. As we cannot
* distinguish between precise and imprecise SErrors, it is not safe to
* continue.
*
* Note that Arm32 asynchronous external abort generated by the
* hypervisor will be handled in do_trap_data_abort().
*/
static void __do_trap_serror(struct cpu_user_regs *regs, bool guest)
{
/*
* When using "DIVERSE", the SErrors generated by the guest will be
* forwarded to the currently running vCPU.
*/
if ( serrors_op == SERRORS_DIVERSE && guest )
return inject_vabt_exception(current);
do_unexpected_trap("SError", regs);
}
struct reg_ctxt {
/* Guest-side state */
register_t sctlr_el1;
register_t tcr_el1;
uint64_t ttbr0_el1, ttbr1_el1;
#ifdef CONFIG_ARM_32
uint32_t dfsr, ifsr;
uint32_t dfar, ifar;
#else
uint32_t esr_el1;
uint64_t far;
uint32_t ifsr32_el2;
#endif
/* Hypervisor-side state */
uint64_t vttbr_el2;
};
static const char *mode_string(uint32_t cpsr)
{
uint32_t mode;
static const char *mode_strings[] = {
[PSR_MODE_USR] = "32-bit Guest USR",
[PSR_MODE_FIQ] = "32-bit Guest FIQ",
[PSR_MODE_IRQ] = "32-bit Guest IRQ",
[PSR_MODE_SVC] = "32-bit Guest SVC",
[PSR_MODE_MON] = "32-bit Monitor",
[PSR_MODE_ABT] = "32-bit Guest ABT",
[PSR_MODE_HYP] = "Hypervisor",
[PSR_MODE_UND] = "32-bit Guest UND",
[PSR_MODE_SYS] = "32-bit Guest SYS",
#ifdef CONFIG_ARM_64
[PSR_MODE_EL3h] = "64-bit EL3h (Monitor, handler)",
[PSR_MODE_EL3t] = "64-bit EL3t (Monitor, thread)",
[PSR_MODE_EL2h] = "64-bit EL2h (Hypervisor, handler)",
[PSR_MODE_EL2t] = "64-bit EL2t (Hypervisor, thread)",
[PSR_MODE_EL1h] = "64-bit EL1h (Guest Kernel, handler)",
[PSR_MODE_EL1t] = "64-bit EL1t (Guest Kernel, thread)",
[PSR_MODE_EL0t] = "64-bit EL0t (Guest User)",
#endif
};
mode = cpsr & PSR_MODE_MASK;
if ( mode >= ARRAY_SIZE(mode_strings) )
return "Unknown";
return mode_strings[mode] ? : "Unknown";
}
static void show_registers_32(const struct cpu_user_regs *regs,
const struct reg_ctxt *ctxt,
bool guest_mode,
const struct vcpu *v)
{
#ifdef CONFIG_ARM_64
BUG_ON( ! (regs->cpsr & PSR_MODE_BIT) );
printk("PC: %08"PRIx32"\n", regs->pc32);
#else
printk("PC: %08"PRIx32, regs->pc);
if ( !guest_mode )
printk(" %pS", _p(regs->pc));
printk("\n");
#endif
printk("CPSR: %08"PRIx32" MODE:%s\n", regs->cpsr,
mode_string(regs->cpsr));
printk(" R0: %08"PRIx32" R1: %08"PRIx32" R2: %08"PRIx32" R3: %08"PRIx32"\n",
regs->r0, regs->r1, regs->r2, regs->r3);
printk(" R4: %08"PRIx32" R5: %08"PRIx32" R6: %08"PRIx32" R7: %08"PRIx32"\n",
regs->r4, regs->r5, regs->r6, regs->r7);
printk(" R8: %08"PRIx32" R9: %08"PRIx32" R10:%08"PRIx32" R11:%08"PRIx32" R12:%08"PRIx32"\n",
regs->r8, regs->r9, regs->r10,
#ifdef CONFIG_ARM_64
regs->r11,
#else
regs->fp,
#endif
regs->r12);
if ( guest_mode )
{
printk("USR: SP: %08"PRIx32" LR: %"PRIregister"\n",
regs->sp_usr, regs->lr);
printk("SVC: SP: %08"PRIx32" LR: %08"PRIx32" SPSR:%08"PRIx32"\n",
regs->sp_svc, regs->lr_svc, regs->spsr_svc);
printk("ABT: SP: %08"PRIx32" LR: %08"PRIx32" SPSR:%08"PRIx32"\n",
regs->sp_abt, regs->lr_abt, regs->spsr_abt);
printk("UND: SP: %08"PRIx32" LR: %08"PRIx32" SPSR:%08"PRIx32"\n",
regs->sp_und, regs->lr_und, regs->spsr_und);
printk("IRQ: SP: %08"PRIx32" LR: %08"PRIx32" SPSR:%08"PRIx32"\n",
regs->sp_irq, regs->lr_irq, regs->spsr_irq);
printk("FIQ: SP: %08"PRIx32" LR: %08"PRIx32" SPSR:%08"PRIx32"\n",
regs->sp_fiq, regs->lr_fiq, regs->spsr_fiq);
printk("FIQ: R8: %08"PRIx32" R9: %08"PRIx32" R10:%08"PRIx32" R11:%08"PRIx32" R12:%08"PRIx32"\n",
regs->r8_fiq, regs->r9_fiq, regs->r10_fiq, regs->r11_fiq, regs->r11_fiq);
}
#ifndef CONFIG_ARM_64
else
{
printk("HYP: SP: %08"PRIx32" LR: %"PRIregister"\n", regs->sp, regs->lr);
}
#endif
printk("\n");
if ( guest_mode )
{
printk(" SCTLR: %"PRIregister"\n", ctxt->sctlr_el1);
printk(" TCR: %"PRIregister"\n", ctxt->tcr_el1);
printk(" TTBR0: %016"PRIx64"\n", ctxt->ttbr0_el1);
printk(" TTBR1: %016"PRIx64"\n", ctxt->ttbr1_el1);
printk(" IFAR: %08"PRIx32", IFSR: %08"PRIx32"\n"
" DFAR: %08"PRIx32", DFSR: %08"PRIx32"\n",
#ifdef CONFIG_ARM_64
(uint32_t)(ctxt->far >> 32),
ctxt->ifsr32_el2,
(uint32_t)(ctxt->far & 0xffffffff),
ctxt->esr_el1
#else
ctxt->ifar, ctxt->ifsr, ctxt->dfar, ctxt->dfsr
#endif
);
printk("\n");
}
}
#ifdef CONFIG_ARM_64
static void show_registers_64(const struct cpu_user_regs *regs,
const struct reg_ctxt *ctxt,
bool guest_mode,
const struct vcpu *v)
{
BUG_ON( (regs->cpsr & PSR_MODE_BIT) );
printk("PC: %016"PRIx64, regs->pc);
if ( !guest_mode )
printk(" %pS", _p(regs->pc));
printk("\n");
printk("LR: %016"PRIx64"\n", regs->lr);
if ( guest_mode )
{
printk("SP_EL0: %016"PRIx64"\n", regs->sp_el0);
printk("SP_EL1: %016"PRIx64"\n", regs->sp_el1);
}
else
{
printk("SP: %016"PRIx64"\n", regs->sp);
}
printk("CPSR: %08"PRIx32" MODE:%s\n", regs->cpsr,
mode_string(regs->cpsr));
printk(" X0: %016"PRIx64" X1: %016"PRIx64" X2: %016"PRIx64"\n",
regs->x0, regs->x1, regs->x2);
printk(" X3: %016"PRIx64" X4: %016"PRIx64" X5: %016"PRIx64"\n",
regs->x3, regs->x4, regs->x5);
printk(" X6: %016"PRIx64" X7: %016"PRIx64" X8: %016"PRIx64"\n",
regs->x6, regs->x7, regs->x8);
printk(" X9: %016"PRIx64" X10: %016"PRIx64" X11: %016"PRIx64"\n",
regs->x9, regs->x10, regs->x11);
printk(" X12: %016"PRIx64" X13: %016"PRIx64" X14: %016"PRIx64"\n",
regs->x12, regs->x13, regs->x14);
printk(" X15: %016"PRIx64" X16: %016"PRIx64" X17: %016"PRIx64"\n",
regs->x15, regs->x16, regs->x17);
printk(" X18: %016"PRIx64" X19: %016"PRIx64" X20: %016"PRIx64"\n",
regs->x18, regs->x19, regs->x20);
printk(" X21: %016"PRIx64" X22: %016"PRIx64" X23: %016"PRIx64"\n",
regs->x21, regs->x22, regs->x23);
printk(" X24: %016"PRIx64" X25: %016"PRIx64" X26: %016"PRIx64"\n",
regs->x24, regs->x25, regs->x26);
printk(" X27: %016"PRIx64" X28: %016"PRIx64" FP: %016"PRIx64"\n",
regs->x27, regs->x28, regs->fp);
printk("\n");
if ( guest_mode )
{
printk(" ELR_EL1: %016"PRIx64"\n", regs->elr_el1);
printk(" ESR_EL1: %08"PRIx32"\n", ctxt->esr_el1);
printk(" FAR_EL1: %016"PRIx64"\n", ctxt->far);
printk("\n");
printk(" SCTLR_EL1: %"PRIregister"\n", ctxt->sctlr_el1);
printk(" TCR_EL1: %"PRIregister"\n", ctxt->tcr_el1);
printk(" TTBR0_EL1: %016"PRIx64"\n", ctxt->ttbr0_el1);
printk(" TTBR1_EL1: %016"PRIx64"\n", ctxt->ttbr1_el1);
printk("\n");
}
}
#endif
static void _show_registers(const struct cpu_user_regs *regs,
const struct reg_ctxt *ctxt,
bool guest_mode,
const struct vcpu *v)
{
print_xen_info();
printk("CPU: %d\n", smp_processor_id());
if ( guest_mode )
{
if ( psr_mode_is_32bit(regs) )
show_registers_32(regs, ctxt, guest_mode, v);
#ifdef CONFIG_ARM_64
else
show_registers_64(regs, ctxt, guest_mode, v);
#endif
}
else
{
#ifdef CONFIG_ARM_64
show_registers_64(regs, ctxt, guest_mode, v);
#else
show_registers_32(regs, ctxt, guest_mode, v);
#endif
}
printk(" VTCR_EL2: %08"PRIx32"\n", READ_SYSREG32(VTCR_EL2));
printk(" VTTBR_EL2: %016"PRIx64"\n", ctxt->vttbr_el2);
printk("\n");
printk(" SCTLR_EL2: %08"PRIx32"\n", READ_SYSREG32(SCTLR_EL2));
printk(" HCR_EL2: %"PRIregister"\n", READ_SYSREG(HCR_EL2));
printk(" TTBR0_EL2: %016"PRIx64"\n", READ_SYSREG64(TTBR0_EL2));
printk("\n");
printk(" ESR_EL2: %08"PRIx32"\n", regs->hsr);
printk(" HPFAR_EL2: %"PRIregister"\n", READ_SYSREG(HPFAR_EL2));
#ifdef CONFIG_ARM_32
printk(" HDFAR: %08"PRIx32"\n", READ_CP32(HDFAR));
printk(" HIFAR: %08"PRIx32"\n", READ_CP32(HIFAR));
#else
printk(" FAR_EL2: %016"PRIx64"\n", READ_SYSREG64(FAR_EL2));
#endif
printk("\n");
}
void show_registers(const struct cpu_user_regs *regs)
{
struct reg_ctxt ctxt;
ctxt.sctlr_el1 = READ_SYSREG(SCTLR_EL1);
ctxt.tcr_el1 = READ_SYSREG(TCR_EL1);
ctxt.ttbr0_el1 = READ_SYSREG64(TTBR0_EL1);
ctxt.ttbr1_el1 = READ_SYSREG64(TTBR1_EL1);
#ifdef CONFIG_ARM_32
ctxt.dfar = READ_CP32(DFAR);
ctxt.ifar = READ_CP32(IFAR);
ctxt.dfsr = READ_CP32(DFSR);
ctxt.ifsr = READ_CP32(IFSR);
#else
ctxt.far = READ_SYSREG(FAR_EL1);
ctxt.esr_el1 = READ_SYSREG(ESR_EL1);
if ( guest_mode(regs) && is_32bit_domain(current->domain) )
ctxt.ifsr32_el2 = READ_SYSREG(IFSR32_EL2);
#endif
ctxt.vttbr_el2 = READ_SYSREG64(VTTBR_EL2);
_show_registers(regs, &ctxt, guest_mode(regs), current);
}
void vcpu_show_registers(const struct vcpu *v)
{
struct reg_ctxt ctxt;
ctxt.sctlr_el1 = v->arch.sctlr;
ctxt.tcr_el1 = v->arch.ttbcr;
ctxt.ttbr0_el1 = v->arch.ttbr0;
ctxt.ttbr1_el1 = v->arch.ttbr1;
#ifdef CONFIG_ARM_32
ctxt.dfar = v->arch.dfar;
ctxt.ifar = v->arch.ifar;
ctxt.dfsr = v->arch.dfsr;
ctxt.ifsr = v->arch.ifsr;
#else
ctxt.far = v->arch.far;
ctxt.esr_el1 = v->arch.esr;
ctxt.ifsr32_el2 = v->arch.ifsr;
#endif
ctxt.vttbr_el2 = v->domain->arch.p2m.vttbr;
_show_registers(&v->arch.cpu_info->guest_cpu_user_regs, &ctxt, 1, v);
}
static void show_guest_stack(struct vcpu *v, const struct cpu_user_regs *regs)
{
int i;
vaddr_t sp;
struct page_info *page;
void *mapped;
unsigned long *stack, addr;
if ( test_bit(_VPF_down, &v->pause_flags) )
{
printk("No stack trace, VCPU offline\n");
return;
}
switch ( regs->cpsr & PSR_MODE_MASK )
{
case PSR_MODE_USR:
case PSR_MODE_SYS:
#ifdef CONFIG_ARM_64
case PSR_MODE_EL0t:
#endif