/
radofin.dsn
366 lines (366 loc) · 13.8 KB
/
radofin.dsn
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(pcb C:\Users\antal\Desktop\radofin\radofin\radofin.dsn
(parser
(string_quote ")
(space_in_quoted_tokens on)
(host_cad "KiCad's Pcbnew")
(host_version "7.0.8")
)
(resolution um 10)
(unit um)
(structure
(layer F.Cu
(type signal)
(property
(index 0)
)
)
(layer B.Cu
(type signal)
(property
(index 1)
)
)
(boundary
(path pcb 0 152000 -119500 84000 -119500 84000 -51500 152000 -51500
152000 -119500)
)
(via "Via[0-1]_800:400_um")
(rule
(width 250)
(clearance 200.1)
(clearance 200.1 (type default_smd))
(clearance 50 (type smd_smd))
)
)
(placement
(component "Package_DIP:DIP-28_W15.24mm"
(place U1 134982.841000 -109376.378000 front 180.000000 (PN 27C128))
)
(component "Package_DIP:DIP-6_W7.62mm"
(place SW2 147452.721000 -65245.635000 front 180.000000 (PN SW_DIP_x03))
)
(component Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal
(place R3 130000.000000 -57282.005000 front 180.000000 (PN 10k))
)
(component Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal::1
(place R2 130000.000000 -62282.005000 front 180.000000 (PN 10k))
(place R1 130000.000000 -67282.005000 front 180.000000 (PN 10k))
)
(component radofin_footp:radofin
(place J1 88828.334000 -79548.638000 front 90.000000 (PN Conn_02x16_Counter_Clockwise))
)
)
(library
(image "Package_DIP:DIP-28_W15.24mm"
(outline (path signal 120 1160 1330 1160 -34350))
(outline (path signal 120 14080 1330 8620 1330))
(outline (path signal 120 1160 -34350 14080 -34350))
(outline (path signal 120 14080 -34350 14080 1330))
(outline (path signal 120 6620 1330 1160 1330))
(outline (path signal 0 7910.08 2349.53 8092.48 2278.87 8258.79 2175.9 8403.35 2044.12
8521.23 1888.02 8608.42 1712.92 8661.95 1524.77 8680 1330
8662.43 1287.57 8620 1270 8577.57 1287.57 8560 1330 8541.94 1513.38
8488.45 1689.72 8401.58 1852.24 8284.68 1994.68 8142.24 2111.58
7979.72 2198.45 7803.39 2251.94 7620 2270 7436.61 2251.94
7260.28 2198.45 7097.76 2111.58 6955.32 1994.68 6838.42 1852.24
6751.55 1689.72 6698.06 1513.38 6680 1330 6662.43 1287.57
6620 1270 6577.57 1287.57 6560 1330 6578.05 1524.77 6631.58 1712.92
6718.77 1888.02 6836.65 2044.12 6981.21 2175.9 7147.52 2278.87
7329.92 2349.53 7522.2 2385.48 7717.8 2385.48))
(outline (path signal 50 -1050 -34550 16300 -34550))
(outline (path signal 50 -1050 1550 -1050 -34550))
(outline (path signal 50 16300 -34550 16300 1550))
(outline (path signal 50 16300 1550 -1050 1550))
(outline (path signal 100 14985 1270 14985 -34290))
(outline (path signal 100 14985 -34290 255 -34290))
(outline (path signal 100 255 -34290 255 270))
(outline (path signal 100 255 270 1255 1270))
(outline (path signal 100 1255 1270 14985 1270))
(pin Rect[A]Pad_1600x1600_um 1 0 0)
(pin Oval[A]Pad_1600x1600_um 2 0 -2540)
(pin Oval[A]Pad_1600x1600_um 3 0 -5080)
(pin Oval[A]Pad_1600x1600_um 4 0 -7620)
(pin Oval[A]Pad_1600x1600_um 5 0 -10160)
(pin Oval[A]Pad_1600x1600_um 6 0 -12700)
(pin Oval[A]Pad_1600x1600_um 7 0 -15240)
(pin Oval[A]Pad_1600x1600_um 8 0 -17780)
(pin Oval[A]Pad_1600x1600_um 9 0 -20320)
(pin Oval[A]Pad_1600x1600_um 10 0 -22860)
(pin Oval[A]Pad_1600x1600_um 11 0 -25400)
(pin Oval[A]Pad_1600x1600_um 12 0 -27940)
(pin Oval[A]Pad_1600x1600_um 13 0 -30480)
(pin Oval[A]Pad_1600x1600_um 14 0 -33020)
(pin Oval[A]Pad_1600x1600_um 15 15240 -33020)
(pin Oval[A]Pad_1600x1600_um 16 15240 -30480)
(pin Oval[A]Pad_1600x1600_um 17 15240 -27940)
(pin Oval[A]Pad_1600x1600_um 18 15240 -25400)
(pin Oval[A]Pad_1600x1600_um 19 15240 -22860)
(pin Oval[A]Pad_1600x1600_um 20 15240 -20320)
(pin Oval[A]Pad_1600x1600_um 21 15240 -17780)
(pin Oval[A]Pad_1600x1600_um 22 15240 -15240)
(pin Oval[A]Pad_1600x1600_um 23 15240 -12700)
(pin Oval[A]Pad_1600x1600_um 24 15240 -10160)
(pin Oval[A]Pad_1600x1600_um 25 15240 -7620)
(pin Oval[A]Pad_1600x1600_um 26 15240 -5080)
(pin Oval[A]Pad_1600x1600_um 27 15240 -2540)
(pin Oval[A]Pad_1600x1600_um 28 15240 0)
)
(image "Package_DIP:DIP-6_W7.62mm"
(outline (path signal 100 635 270 1635 1270))
(outline (path signal 100 6985 1270 6985 -6350))
(outline (path signal 100 1635 1270 6985 1270))
(outline (path signal 100 635 -6350 635 270))
(outline (path signal 100 6985 -6350 635 -6350))
(outline (path signal 50 -1100 1550 -1100 -6600))
(outline (path signal 50 8700 1550 -1100 1550))
(outline (path signal 50 -1100 -6600 8700 -6600))
(outline (path signal 50 8700 -6600 8700 1550))
(outline (path signal 0 4100.08 2349.53 4282.48 2278.87 4448.79 2175.9 4593.35 2044.12
4711.23 1888.02 4798.42 1712.92 4851.95 1524.77 4870 1330
4852.43 1287.57 4810 1270 4767.57 1287.57 4750 1330 4731.94 1513.38
4678.45 1689.72 4591.58 1852.24 4474.68 1994.68 4332.24 2111.58
4169.72 2198.45 3993.39 2251.94 3810 2270 3626.61 2251.94
3450.28 2198.45 3287.76 2111.58 3145.32 1994.68 3028.42 1852.24
2941.55 1689.72 2888.06 1513.38 2870 1330 2852.43 1287.57
2810 1270 2767.57 1287.57 2750 1330 2768.05 1524.77 2821.58 1712.92
2908.77 1888.02 3026.65 2044.12 3171.21 2175.9 3337.52 2278.87
3519.92 2349.53 3712.2 2385.48 3907.8 2385.48))
(outline (path signal 120 2810 1330 1160 1330))
(outline (path signal 120 1160 -6410 6460 -6410))
(outline (path signal 120 1160 1330 1160 -6410))
(outline (path signal 120 6460 -6410 6460 1330))
(outline (path signal 120 6460 1330 4810 1330))
(pin Oval[A]Pad_1600x1600_um 6 7620 0)
(pin Oval[A]Pad_1600x1600_um 5 7620 -2540)
(pin Oval[A]Pad_1600x1600_um 4 7620 -5080)
(pin Oval[A]Pad_1600x1600_um 3 0 -5080)
(pin Oval[A]Pad_1600x1600_um 2 0 -2540)
(pin Rect[A]Pad_1600x1600_um 1 0 0)
)
(image Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal
(outline (path signal 100 10160 0 8230 0))
(outline (path signal 100 0 0 1930 0))
(outline (path signal 100 1930 1250 1930 -1250))
(outline (path signal 100 8230 -1250 8230 1250))
(outline (path signal 100 1930 -1250 8230 -1250))
(outline (path signal 100 8230 1250 1930 1250))
(outline (path signal 50 -1050 1500 -1050 -1500))
(outline (path signal 50 -1050 -1500 11210 -1500))
(outline (path signal 50 11210 1500 -1050 1500))
(outline (path signal 50 11210 -1500 11210 1500))
(outline (path signal 120 8350 1370 1810 1370))
(outline (path signal 120 1810 -1370 8350 -1370))
(outline (path signal 120 8350 -1370 8350 1370))
(outline (path signal 120 1810 1370 1810 -1370))
(outline (path signal 120 1040 0 1810 0))
(outline (path signal 120 9120 0 8350 0))
(pin Oval[A]Pad_1600x1600_um 2 10160 0)
(pin Round[A]Pad_1600_um 1 0 0)
)
(image Resistor_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal::1
(outline (path signal 120 9120 0 8350 0))
(outline (path signal 120 1040 0 1810 0))
(outline (path signal 120 1810 1370 1810 -1370))
(outline (path signal 120 8350 -1370 8350 1370))
(outline (path signal 120 1810 -1370 8350 -1370))
(outline (path signal 120 8350 1370 1810 1370))
(outline (path signal 50 11210 -1500 11210 1500))
(outline (path signal 50 11210 1500 -1050 1500))
(outline (path signal 50 -1050 -1500 11210 -1500))
(outline (path signal 50 -1050 1500 -1050 -1500))
(outline (path signal 100 8230 1250 1930 1250))
(outline (path signal 100 1930 -1250 8230 -1250))
(outline (path signal 100 8230 -1250 8230 1250))
(outline (path signal 100 1930 1250 1930 -1250))
(outline (path signal 100 0 0 1930 0))
(outline (path signal 100 10160 0 8230 0))
(pin Round[A]Pad_1600_um 1 0 0)
(pin Oval[A]Pad_1600x1600_um 2 10160 0)
)
(image radofin_footp:radofin
(pin Rect[T]Pad_2400x9000_um 1 -35640 0)
(pin Rect[T]Pad_2400x9000_um 2 -31680 0)
(pin Rect[T]Pad_2400x9000_um 3 -27720 0)
(pin Rect[T]Pad_2400x9000_um 4 -23760 0)
(pin Rect[T]Pad_2400x9000_um 5 -19800 0)
(pin Rect[T]Pad_2400x9000_um 6 -15840 0)
(pin Rect[T]Pad_2400x9000_um 7 -11880 0)
(pin Rect[T]Pad_2400x9000_um 8 -7920 0)
(pin Rect[T]Pad_2400x9000_um 9 -3960 0)
(pin Rect[T]Pad_2400x9000_um 10 0 0)
(pin Rect[T]Pad_2400x9000_um 11 3960 0)
(pin Rect[T]Pad_2400x9000_um 12 7920 0)
(pin Rect[T]Pad_2400x9000_um 13 11880 0)
(pin Rect[T]Pad_2400x9000_um 14 15840 0)
(pin Rect[T]Pad_2400x9000_um 15 19800 0)
(pin Rect[T]Pad_2400x9000_um 16 23760 0)
(pin Rect[B]Pad_2400x9000_um 17 23760 0)
(pin Rect[B]Pad_2400x9000_um 18 19800 0)
(pin Rect[B]Pad_2400x9000_um 19 15840 0)
(pin Rect[B]Pad_2400x9000_um 20 11880 0)
(pin Rect[B]Pad_2400x9000_um 21 7920 0)
(pin Rect[B]Pad_2400x9000_um 22 3960 0)
(pin Rect[B]Pad_2400x9000_um 23 0 0)
(pin Rect[B]Pad_2400x9000_um 24 -3960 0)
(pin Rect[B]Pad_2400x9000_um 25 -7920 0)
(pin Rect[B]Pad_2400x9000_um 26 -11880 0)
(pin Rect[B]Pad_2400x9000_um 27 -15840 0)
(pin Rect[B]Pad_2400x9000_um 28 -19800 0)
(pin Rect[B]Pad_2400x9000_um 29 -23760 0)
(pin Rect[B]Pad_2400x9000_um 30 -27720 0)
(pin Rect[B]Pad_2400x9000_um 31 -31680 0)
(pin Rect[B]Pad_2400x9000_um 32 -35640 0)
)
(padstack Round[A]Pad_1600_um
(shape (circle F.Cu 1600))
(shape (circle B.Cu 1600))
(attach off)
)
(padstack Oval[A]Pad_1600x1600_um
(shape (path F.Cu 1600 0 0 0 0))
(shape (path B.Cu 1600 0 0 0 0))
(attach off)
)
(padstack Rect[B]Pad_2400x9000_um
(shape (rect B.Cu -1200 -4500 1200 4500))
(attach off)
)
(padstack Rect[T]Pad_2400x9000_um
(shape (rect F.Cu -1200 -4500 1200 4500))
(attach off)
)
(padstack Rect[A]Pad_1600x1600_um
(shape (rect F.Cu -800 -800 800 800))
(shape (rect B.Cu -800 -800 800 800))
(attach off)
)
(padstack "Via[0-1]_800:400_um"
(shape (circle F.Cu 800))
(shape (circle B.Cu 800))
(attach off)
)
)
(network
(net "Net-(J1-Pin_6)"
(pins U1-23 SW2-6 R1-1 J1-6)
)
(net VCC
(pins U1-28 R3-2 R2-2 R1-2 J1-23)
)
(net "Net-(U1-A12)"
(pins U1-2 SW2-5 R2-1)
)
(net "Net-(U1-A13)"
(pins U1-26 SW2-4 R3-1)
)
(net GND
(pins U1-14 U1-20 U1-22 SW2-3 SW2-2 SW2-1 J1-17)
)
(net "Net-(J1-Pin_18)"
(pins U1-1 J1-18)
)
(net "Net-(J1-Pin_1)"
(pins U1-3 J1-1)
)
(net "Net-(J1-Pin_32)"
(pins U1-4 J1-32)
)
(net "Net-(J1-Pin_31)"
(pins U1-5 J1-31)
)
(net "Net-(J1-Pin_30)"
(pins U1-6 J1-30)
)
(net "Net-(J1-Pin_29)"
(pins U1-7 J1-29)
)
(net "Net-(J1-Pin_28)"
(pins U1-8 J1-28)
)
(net "Net-(J1-Pin_27)"
(pins U1-9 J1-27)
)
(net "Net-(J1-Pin_26)"
(pins U1-10 J1-26)
)
(net "Net-(J1-Pin_15)"
(pins U1-11 J1-15)
)
(net "Net-(J1-Pin_14)"
(pins U1-12 J1-14)
)
(net "Net-(J1-Pin_13)"
(pins U1-13 J1-13)
)
(net "Net-(J1-Pin_12)"
(pins U1-15 J1-12)
)
(net "Net-(J1-Pin_11)"
(pins U1-16 J1-11)
)
(net "Net-(J1-Pin_10)"
(pins U1-17 J1-10)
)
(net "Net-(J1-Pin_9)"
(pins U1-18 J1-9)
)
(net "Net-(J1-Pin_8)"
(pins U1-19 J1-8)
)
(net "Net-(J1-Pin_5)"
(pins U1-21 J1-5)
)
(net "Net-(J1-Pin_4)"
(pins U1-24 J1-4)
)
(net "Net-(J1-Pin_3)"
(pins U1-25 J1-3)
)
(net "Net-(J1-Pin_16)"
(pins U1-27 J1-16)
)
(net "unconnected-(J1-Pin_2-Pad2)"
(pins J1-2)
)
(net "unconnected-(J1-Pin_7-Pad7)"
(pins J1-7)
)
(net "unconnected-(J1-Pin_19-Pad19)"
(pins J1-19)
)
(net "unconnected-(J1-Pin_20-Pad20)"
(pins J1-20)
)
(net "unconnected-(J1-Pin_21-Pad21)"
(pins J1-21)
)
(net "unconnected-(J1-Pin_22-Pad22)"
(pins J1-22)
)
(net "unconnected-(J1-Pin_24-Pad24)"
(pins J1-24)
)
(net "unconnected-(J1-Pin_25-Pad25)"
(pins J1-25)
)
(class kicad_default "" GND "Net-(J1-Pin_1)" "Net-(J1-Pin_10)" "Net-(J1-Pin_11)"
"Net-(J1-Pin_12)" "Net-(J1-Pin_13)" "Net-(J1-Pin_14)" "Net-(J1-Pin_15)"
"Net-(J1-Pin_16)" "Net-(J1-Pin_18)" "Net-(J1-Pin_26)" "Net-(J1-Pin_27)"
"Net-(J1-Pin_28)" "Net-(J1-Pin_29)" "Net-(J1-Pin_3)" "Net-(J1-Pin_30)"
"Net-(J1-Pin_31)" "Net-(J1-Pin_32)" "Net-(J1-Pin_4)" "Net-(J1-Pin_5)"
"Net-(J1-Pin_6)" "Net-(J1-Pin_8)" "Net-(J1-Pin_9)" "Net-(U1-A12)" "Net-(U1-A13)"
VCC "unconnected-(J1-Pin_19-Pad19)" "unconnected-(J1-Pin_2-Pad2)" "unconnected-(J1-Pin_20-Pad20)"
"unconnected-(J1-Pin_21-Pad21)" "unconnected-(J1-Pin_22-Pad22)" "unconnected-(J1-Pin_24-Pad24)"
"unconnected-(J1-Pin_25-Pad25)" "unconnected-(J1-Pin_7-Pad7)"
(circuit
(use_via Via[0-1]_800:400_um)
)
(rule
(width 250)
(clearance 200.1)
)
)
)
(wiring
)
)