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nextpnr-ice40
is failing to route PLL clock
#71
Comments
@cr1901 Do you still have this issue ? I just tried a similar design (PLL with output manually connected to a SB_GB) and it works fine here. It's still not the "right" thing (wasing a buffer instead of using the one dedicated to the PLL), but that should still be working, at least for a led blink. |
Just for the record, issue was identified as next-pnr placing the PLL instance in the bottom PLL BEL ... which is not available in that package because it doesn't process the LOCKED attributes from the chipdb. I have a couple of commits to allow to workaround that and other fixes in my 'work' tree https://github.com/smunaut/nextpnr/tree/ice40_work I'll properly submit those once the PLL global stuff has been reviewed. |
I think this can be closed. Works fine on my tinyfpga BX now. |
Actual Behavior
The following Verilog module:
results in a design which passes timing according to
nextpnr
, but results in a nonfunctional bitstream (no LED blinking). Modifying the above Verilog module to remove the PLL and route the system clock directly to the logic creates a functional bitstream (LED blinking). I have reproduced it below:Expected behavior
As both the above modules are driven by a 16MHz clock- one from the PLL output, the other from a pin- I would expect the above two modules to behave identically.
Other information
MCVE
MVCE is here: pll-crash2.zip
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