Allwinner T113-s3 DSP static DRAM interleave fix proposal.

[ua1arn]

Then I fill data ram of embedded DSP, address translation discovered.
You can integrate these functions:

// HiFI4 DSP-viewed address offset translate to host cpu viewwed
static ptrdiff_t xlate_dsp2mpu(ptrdiff_t a)
{
	const ptrdiff_t BANKSIZE = 0x08000u;
	const ptrdiff_t CELLBASE = 0x10000u;
	const ptrdiff_t CELLSIZE = 16;
	const ptrdiff_t cellbank = (a - CELLBASE) / BANKSIZE;
	const ptrdiff_t cellrow = (a - CELLBASE) % BANKSIZE / CELLSIZE;	// 16 bytes granularity
	const unsigned cellpos = (a % CELLSIZE);	// 16 bytes granularity

	if (a < CELLBASE)
		return a;	/* translation not needed. */

	return CELLBASE +
			cellbank * BANKSIZE +
			CELLSIZE * ((cellrow % 2) ? (cellrow / 2) + (BANKSIZE / CELLSIZE / 2) : cellrow / 2) +
			cellpos;
}

static void copy2dsp(uint8_t * pdspmap, const uint8_t * pcpu, unsigned offs, unsigned size)
{
	for (; size --; ++ offs)
	{
		pdspmap [xlate_dsp2mpu(offs)] = pcpu [offs];
	}
}

static void zero2dsp(uint8_t * pdspmap, unsigned offs, unsigned size)
{
	for (; size --; ++ offs)
	{
		pdspmap [xlate_dsp2mpu(offs)] = 0x00;
	}
}

[YuzukiTsuru]

Currently, there is no mmu adapter driver available. All access to dram may result in errors. After consideration, provide these support soon

[ua1arn]

I tested on static ram at 0x20038000 at or 0x00038000 hifi4 view (0x00040000 from host view)