"RTL Design and Verification Engineer"
I am an RTL design and Verification engineer with a strong background in Computer Architecture and Digital Logic Design. I have deep knowledge of System on Chip components like bus protocols and peripheral communication with CPU. My research focus area is to improve computation speed and power optimization in hardware for Machine Learning applications.
- SystemVerilog, Verilog, CHISEL
- Universal Verification Methodology (UVM)
- RISC-V Assembly
- C / C++
- Python, Bash, tcl
- Xcelium, Questa Sim, Vivado (xsim), Verilator, iCarus Verilog, GTK wave
- Vivado (synthesis and implementation), AWS Cloud FPGA
- Genus, Yosys
Visit my portfolio @ zeeshanrafique.me 🛸