/
can_mcan.h
1735 lines (1558 loc) · 63.2 KB
/
can_mcan.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
* Copyright (c) 2023 Vestas Wind Systems A/S
* Copyright (c) 2020 Alexander Wachter
*
* SPDX-License-Identifier: Apache-2.0
*
*/
#ifndef ZEPHYR_INCLUDE_DRIVERS_CAN_CAN_MCAN_H_
#define ZEPHYR_INCLUDE_DRIVERS_CAN_CAN_MCAN_H_
#include <zephyr/cache.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/can.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/util.h>
/*
* The Bosch M_CAN register definitions correspond to those found in the Bosch M_CAN Controller Area
* Network User's Manual, Revision 3.3.0.
*/
/* Core Release register */
#define CAN_MCAN_CREL 0x000
#define CAN_MCAN_CREL_REL GENMASK(31, 28)
#define CAN_MCAN_CREL_STEP GENMASK(27, 24)
#define CAN_MCAN_CREL_SUBSTEP GENMASK(23, 20)
#define CAN_MCAN_CREL_YEAR GENMASK(19, 16)
#define CAN_MCAN_CREL_MON GENMASK(15, 8)
#define CAN_MCAN_CREL_DAY GENMASK(7, 0)
/* Endian register */
#define CAN_MCAN_ENDN 0x004
#define CAN_MCAN_ENDN_ETV GENMASK(31, 0)
/* Customer register */
#define CAN_MCAN_CUST 0x008
#define CAN_MCAN_CUST_CUST GENMASK(31, 0)
/* Data Bit Timing & Prescaler register */
#define CAN_MCAN_DBTP 0x00C
#define CAN_MCAN_DBTP_TDC BIT(23)
#define CAN_MCAN_DBTP_DBRP GENMASK(20, 16)
#define CAN_MCAN_DBTP_DTSEG1 GENMASK(12, 8)
#define CAN_MCAN_DBTP_DTSEG2 GENMASK(7, 4)
#define CAN_MCAN_DBTP_DSJW GENMASK(3, 0)
/* Test register */
#define CAN_MCAN_TEST 0x010
#define CAN_MCAN_TEST_SVAL BIT(21)
#define CAN_MCAN_TEST_TXBNS GENMASK(20, 16)
#define CAN_MCAN_TEST_PVAL BIT(13)
#define CAN_MCAN_TEST_TXBNP GENMASK(12, 8)
#define CAN_MCAN_TEST_RX BIT(7)
#define CAN_MCAN_TEST_TX GENMASK(6, 5)
#define CAN_MCAN_TEST_LBCK BIT(4)
/* RAM Watchdog register */
#define CAN_MCAN_RWD 0x014
#define CAN_MCAN_RWD_WDV GENMASK(15, 8)
#define CAN_MCAN_RWD_WDC GENMASK(7, 0)
/* CC Control register */
#define CAN_MCAN_CCCR 0x018
#define CAN_MCAN_CCCR_NISO BIT(15)
#define CAN_MCAN_CCCR_TXP BIT(14)
#define CAN_MCAN_CCCR_EFBI BIT(13)
#define CAN_MCAN_CCCR_PXHD BIT(12)
#define CAN_MCAN_CCCR_WMM BIT(11)
#define CAN_MCAN_CCCR_UTSU BIT(10)
#define CAN_MCAN_CCCR_BRSE BIT(9)
#define CAN_MCAN_CCCR_FDOE BIT(8)
#define CAN_MCAN_CCCR_TEST BIT(7)
#define CAN_MCAN_CCCR_DAR BIT(6)
#define CAN_MCAN_CCCR_MON BIT(5)
#define CAN_MCAN_CCCR_CSR BIT(4)
#define CAN_MCAN_CCCR_CSA BIT(3)
#define CAN_MCAN_CCCR_ASM BIT(2)
#define CAN_MCAN_CCCR_CCE BIT(1)
#define CAN_MCAN_CCCR_INIT BIT(0)
/* Nominal Bit Timing & Prescaler register */
#define CAN_MCAN_NBTP 0x01C
#define CAN_MCAN_NBTP_NSJW GENMASK(31, 25)
#define CAN_MCAN_NBTP_NBRP GENMASK(24, 16)
#define CAN_MCAN_NBTP_NTSEG1 GENMASK(15, 8)
#define CAN_MCAN_NBTP_NTSEG2 GENMASK(6, 0)
/* Timestamp Counter Configuration register */
#define CAN_MCAN_TSCC 0x020
#define CAN_MCAN_TSCC_TCP GENMASK(19, 16)
#define CAN_MCAN_TSCC_TSS GENMASK(1, 0)
/* Timestamp Counter Value register */
#define CAN_MCAN_TSCV 0x024
#define CAN_MCAN_TSCV_TSC GENMASK(15, 0)
/* Timeout Counter Configuration register */
#define CAN_MCAN_TOCC 0x028
#define CAN_MCAN_TOCC_TOP GENMASK(31, 16)
#define CAN_MCAN_TOCC_TOS GENMASK(2, 1)
#define CAN_MCAN_TOCC_ETOC BIT(1)
/* Timeout Counter Value register */
#define CAN_MCAN_TOCV 0x02C
#define CAN_MCAN_TOCV_TOC GENMASK(15, 0)
/* Error Counter register */
#define CAN_MCAN_ECR 0x040
#define CAN_MCAN_ECR_CEL GENMASK(23, 16)
#define CAN_MCAN_ECR_RP BIT(15)
#define CAN_MCAN_ECR_REC GENMASK(14, 8)
#define CAN_MCAN_ECR_TEC GENMASK(7, 0)
/* Protocol Status register */
#define CAN_MCAN_PSR 0x044
#define CAN_MCAN_PSR_TDCV GENMASK(22, 16)
#define CAN_MCAN_PSR_PXE BIT(14)
#define CAN_MCAN_PSR_RFDF BIT(13)
#define CAN_MCAN_PSR_RBRS BIT(12)
#define CAN_MCAN_PSR_RESI BIT(11)
#define CAN_MCAN_PSR_DLEC GENMASK(10, 8)
#define CAN_MCAN_PSR_BO BIT(7)
#define CAN_MCAN_PSR_EW BIT(6)
#define CAN_MCAN_PSR_EP BIT(5)
#define CAN_MCAN_PSR_ACT GENMASK(4, 3)
#define CAN_MCAN_PSR_LEC GENMASK(2, 0)
#define CAN_MCAN_PSR_LEC_NO_ERROR 0
#define CAN_MCAN_PSR_LEC_STUFF_ERROR 1
#define CAN_MCAN_PSR_LEC_FORM_ERROR 2
#define CAN_MCAN_PSR_LEC_ACK_ERROR 3
#define CAN_MCAN_PSR_LEC_BIT1_ERROR 4
#define CAN_MCAN_PSR_LEC_BIT0_ERROR 5
#define CAN_MCAN_PSR_LEC_CRC_ERROR 6
#define CAN_MCAN_PSR_LEC_NO_CHANGE 7
/* Transmitter Delay Compensation register */
#define CAN_MCAN_TDCR 0x048
#define CAN_MCAN_TDCR_TDCO GENMASK(14, 8)
#define CAN_MCAN_TDCR_TDCF GENMASK(6, 0)
/* Interrupt register */
#define CAN_MCAN_IR 0x050
#define CAN_MCAN_IR_ARA BIT(29)
#define CAN_MCAN_IR_PED BIT(28)
#define CAN_MCAN_IR_PEA BIT(27)
#define CAN_MCAN_IR_WDI BIT(26)
#define CAN_MCAN_IR_BO BIT(25)
#define CAN_MCAN_IR_EW BIT(24)
#define CAN_MCAN_IR_EP BIT(23)
#define CAN_MCAN_IR_ELO BIT(22)
#define CAN_MCAN_IR_BEU BIT(21)
#define CAN_MCAN_IR_BEC BIT(20)
#define CAN_MCAN_IR_DRX BIT(19)
#define CAN_MCAN_IR_TOO BIT(18)
#define CAN_MCAN_IR_MRAF BIT(17)
#define CAN_MCAN_IR_TSW BIT(16)
#define CAN_MCAN_IR_TEFL BIT(15)
#define CAN_MCAN_IR_TEFF BIT(14)
#define CAN_MCAN_IR_TEFW BIT(13)
#define CAN_MCAN_IR_TEFN BIT(12)
#define CAN_MCAN_IR_TFE BIT(11)
#define CAN_MCAN_IR_TCF BIT(10)
#define CAN_MCAN_IR_TC BIT(9)
#define CAN_MCAN_IR_HPM BIT(8)
#define CAN_MCAN_IR_RF1L BIT(7)
#define CAN_MCAN_IR_RF1F BIT(6)
#define CAN_MCAN_IR_RF1W BIT(5)
#define CAN_MCAN_IR_RF1N BIT(4)
#define CAN_MCAN_IR_RF0L BIT(3)
#define CAN_MCAN_IR_RF0F BIT(2)
#define CAN_MCAN_IR_RF0W BIT(1)
#define CAN_MCAN_IR_RF0N BIT(0)
/* Interrupt Enable register */
#define CAN_MCAN_IE 0x054
#define CAN_MCAN_IE_ARAE BIT(29)
#define CAN_MCAN_IE_PEDE BIT(28)
#define CAN_MCAN_IE_PEAE BIT(27)
#define CAN_MCAN_IE_WDIE BIT(26)
#define CAN_MCAN_IE_BOE BIT(25)
#define CAN_MCAN_IE_EWE BIT(24)
#define CAN_MCAN_IE_EPE BIT(23)
#define CAN_MCAN_IE_ELOE BIT(22)
#define CAN_MCAN_IE_BEUE BIT(21)
#define CAN_MCAN_IE_BECE BIT(20)
#define CAN_MCAN_IE_DRXE BIT(19)
#define CAN_MCAN_IE_TOOE BIT(18)
#define CAN_MCAN_IE_MRAFE BIT(17)
#define CAN_MCAN_IE_TSWE BIT(16)
#define CAN_MCAN_IE_TEFLE BIT(15)
#define CAN_MCAN_IE_TEFFE BIT(14)
#define CAN_MCAN_IE_TEFWE BIT(13)
#define CAN_MCAN_IE_TEFNE BIT(12)
#define CAN_MCAN_IE_TFEE BIT(11)
#define CAN_MCAN_IE_TCFE BIT(10)
#define CAN_MCAN_IE_TCE BIT(9)
#define CAN_MCAN_IE_HPME BIT(8)
#define CAN_MCAN_IE_RF1LE BIT(7)
#define CAN_MCAN_IE_RF1FE BIT(6)
#define CAN_MCAN_IE_RF1WE BIT(5)
#define CAN_MCAN_IE_RF1NE BIT(4)
#define CAN_MCAN_IE_RF0LE BIT(3)
#define CAN_MCAN_IE_RF0FE BIT(2)
#define CAN_MCAN_IE_RF0WE BIT(1)
#define CAN_MCAN_IE_RF0NE BIT(0)
/* Interrupt Line Select register */
#define CAN_MCAN_ILS 0x058
#define CAN_MCAN_ILS_ARAL BIT(29)
#define CAN_MCAN_ILS_PEDL BIT(28)
#define CAN_MCAN_ILS_PEAL BIT(27)
#define CAN_MCAN_ILS_WDIL BIT(26)
#define CAN_MCAN_ILS_BOL BIT(25)
#define CAN_MCAN_ILS_EWL BIT(24)
#define CAN_MCAN_ILS_EPL BIT(23)
#define CAN_MCAN_ILS_ELOL BIT(22)
#define CAN_MCAN_ILS_BEUL BIT(21)
#define CAN_MCAN_ILS_BECL BIT(20)
#define CAN_MCAN_ILS_DRXL BIT(19)
#define CAN_MCAN_ILS_TOOL BIT(18)
#define CAN_MCAN_ILS_MRAFL BIT(17)
#define CAN_MCAN_ILS_TSWL BIT(16)
#define CAN_MCAN_ILS_TEFLL BIT(15)
#define CAN_MCAN_ILS_TEFFL BIT(14)
#define CAN_MCAN_ILS_TEFWL BIT(13)
#define CAN_MCAN_ILS_TEFNL BIT(12)
#define CAN_MCAN_ILS_TFEL BIT(11)
#define CAN_MCAN_ILS_TCFL BIT(10)
#define CAN_MCAN_ILS_TCL BIT(9)
#define CAN_MCAN_ILS_HPML BIT(8)
#define CAN_MCAN_ILS_RF1LL BIT(7)
#define CAN_MCAN_ILS_RF1FL BIT(6)
#define CAN_MCAN_ILS_RF1WL BIT(5)
#define CAN_MCAN_ILS_RF1NL BIT(4)
#define CAN_MCAN_ILS_RF0LL BIT(3)
#define CAN_MCAN_ILS_RF0FL BIT(2)
#define CAN_MCAN_ILS_RF0WL BIT(1)
#define CAN_MCAN_ILS_RF0NL BIT(0)
/* Interrupt Line Enable register */
#define CAN_MCAN_ILE 0x05C
#define CAN_MCAN_ILE_EINT1 BIT(1)
#define CAN_MCAN_ILE_EINT0 BIT(0)
/* Global filter configuration register */
#define CAN_MCAN_GFC 0x080
#define CAN_MCAN_GFC_ANFS GENMASK(5, 4)
#define CAN_MCAN_GFC_ANFE GENMASK(3, 2)
#define CAN_MCAN_GFC_RRFS BIT(1)
#define CAN_MCAN_GFC_RRFE BIT(0)
/* Standard ID Filter Configuration register */
#define CAN_MCAN_SIDFC 0x084
#define CAN_MCAN_SIDFC_LSS GENMASK(23, 16)
#define CAN_MCAN_SIDFC_FLSSA GENMASK(15, 2)
/* Extended ID Filter Configuration register */
#define CAN_MCAN_XIDFC 0x088
#define CAN_MCAN_XIDFC_LSS GENMASK(22, 16)
#define CAN_MCAN_XIDFC_FLESA GENMASK(15, 2)
/* Extended ID AND Mask register */
#define CAN_MCAN_XIDAM 0x090
#define CAN_MCAN_XIDAM_EIDM GENMASK(28, 0)
/* High Priority Message Status register */
#define CAN_MCAN_HPMS 0x094
#define CAN_MCAN_HPMS_FLST BIT(15)
#define CAN_MCAN_HPMS_FIDX GENMASK(14, 8)
#define CAN_MCAN_HPMS_MSI GENMASK(7, 6)
#define CAN_MCAN_HPMS_BIDX GENMASK(5, 0)
/* New Data 1 register */
#define CAN_MCAN_NDAT1 0x098
#define CAN_MCAN_NDAT1_ND GENMASK(31, 0)
/* New Data 2 register */
#define CAN_MCAN_NDAT2 0x09C
#define CAN_MCAN_NDAT2_ND GENMASK(31, 0)
/* Rx FIFO 0 Configuration register */
#define CAN_MCAN_RXF0C 0x0A0
#define CAN_MCAN_RXF0C_F0OM BIT(31)
#define CAN_MCAN_RXF0C_F0WM GENMASK(30, 24)
#define CAN_MCAN_RXF0C_F0S GENMASK(22, 16)
#define CAN_MCAN_RXF0C_F0SA GENMASK(15, 2)
/* Rx FIFO 0 Status register */
#define CAN_MCAN_RXF0S 0x0A4
#define CAN_MCAN_RXF0S_RF0L BIT(25)
#define CAN_MCAN_RXF0S_F0F BIT(24)
#define CAN_MCAN_RXF0S_F0PI GENMASK(21, 16)
#define CAN_MCAN_RXF0S_F0GI GENMASK(13, 8)
#define CAN_MCAN_RXF0S_F0FL GENMASK(6, 0)
/* Rx FIFO 0 Acknowledge register */
#define CAN_MCAN_RXF0A 0x0A8
#define CAN_MCAN_RXF0A_F0AI GENMASK(5, 0)
/* Rx Buffer Configuration register */
#define CAN_MCAN_RXBC 0x0AC
#define CAN_MCAN_RXBC_RBSA GENMASK(15, 2)
/* Rx FIFO 1 Configuration register */
#define CAN_MCAN_RXF1C 0x0B0
#define CAN_MCAN_RXF1C_F1OM BIT(31)
#define CAN_MCAN_RXF1C_F1WM GENMASK(30, 24)
#define CAN_MCAN_RXF1C_F1S GENMASK(22, 16)
#define CAN_MCAN_RXF1C_F1SA GENMASK(15, 2)
/* Rx FIFO 1 Status register */
#define CAN_MCAN_RXF1S 0x0B4
#define CAN_MCAN_RXF1S_RF1L BIT(25)
#define CAN_MCAN_RXF1S_F1F BIT(24)
#define CAN_MCAN_RXF1S_F1PI GENMASK(21, 16)
#define CAN_MCAN_RXF1S_F1GI GENMASK(13, 8)
#define CAN_MCAN_RXF1S_F1FL GENMASK(6, 0)
/* Rx FIFO 1 Acknowledge register */
#define CAN_MCAN_RXF1A 0x0B8
#define CAN_MCAN_RXF1A_F1AI GENMASK(5, 0)
/* Rx Buffer/FIFO Element Size Configuration register */
#define CAN_MCAN_RXESC 0x0BC
#define CAN_MCAN_RXESC_RBDS GENMASK(10, 8)
#define CAN_MCAN_RXESC_F1DS GENMASK(6, 4)
#define CAN_MCAN_RXESC_F0DS GENMASK(2, 0)
/* Tx Buffer Configuration register */
#define CAN_MCAN_TXBC 0x0C0
#define CAN_MCAN_TXBC_TFQM BIT(30)
#define CAN_MCAN_TXBC_TFQS GENMASK(29, 24)
#define CAN_MCAN_TXBC_NDTB GENMASK(21, 16)
#define CAN_MCAN_TXBC_TBSA GENMASK(15, 2)
/* Tx FIFO/Queue Status register */
#define CAN_MCAN_TXFQS 0x0C4
#define CAN_MCAN_TXFQS_TFQF BIT(21)
#define CAN_MCAN_TXFQS_TFQPI GENMASK(20, 16)
#define CAN_MCAN_TXFQS_TFGI GENMASK(12, 8)
#define CAN_MCAN_TXFQS_TFFL GENMASK(5, 0)
/* Tx Buffer Element Size Configuration register */
#define CAN_MCAN_TXESC 0x0C8
#define CAN_MCAN_TXESC_TBDS GENMASK(2, 0)
/* Tx Buffer Request Pending register */
#define CAN_MCAN_TXBRP 0x0CC
#define CAN_MCAN_TXBRP_TRP GENMASK(31, 0)
/* Tx Buffer Add Request register */
#define CAN_MCAN_TXBAR 0x0D0
#define CAN_MCAN_TXBAR_AR GENMASK(31, 0)
/* Tx Buffer Cancellation Request register */
#define CAN_MCAN_TXBCR 0x0D4
#define CAN_MCAN_TXBCR_CR GENMASK(31, 0)
/* Tx Buffer Transmission Occurred register */
#define CAN_MCAN_TXBTO 0x0D8
#define CAN_MCAN_TXBTO_TO GENMASK(31, 0)
/* Tx Buffer Cancellation Finished register */
#define CAN_MCAN_TXBCF 0x0DC
#define CAN_MCAN_TXBCF_CF GENMASK(31, 0)
/* Tx Buffer Transmission Interrupt Enable register */
#define CAN_MCAN_TXBTIE 0x0E0
#define CAN_MCAN_TXBTIE_TIE GENMASK(31, 0)
/* Tx Buffer Cancellation Finished Interrupt Enable register */
#define CAN_MCAN_TXBCIE 0x0E4
#define CAN_MCAN_TXBCIE_CFIE GENMASK(31, 0)
/* Tx Event FIFO Configuration register */
#define CAN_MCAN_TXEFC 0x0F0
#define CAN_MCAN_TXEFC_EFWM GENMASK(29, 24)
#define CAN_MCAN_TXEFC_EFS GENMASK(21, 16)
#define CAN_MCAN_TXEFC_EFSA GENMASK(15, 2)
/* Tx Event FIFO Status register */
#define CAN_MCAN_TXEFS 0x0F4
#define CAN_MCAN_TXEFS_TEFL BIT(25)
#define CAN_MCAN_TXEFS_EFF BIT(24)
#define CAN_MCAN_TXEFS_EFPI GENMASK(20, 16)
#define CAN_MCAN_TXEFS_EFGI GENMASK(12, 8)
#define CAN_MCAN_TXEFS_EFFL GENMASK(5, 0)
/* Tx Event FIFO Acknowledge register */
#define CAN_MCAN_TXEFA 0x0F8
#define CAN_MCAN_TXEFA_EFAI GENMASK(4, 0)
/**
* @name Indexes for the cells in the devicetree bosch,mram-cfg property
* @anchor CAN_MCAN_MRAM_CFG
* These match the description of the cells in the bosch,m_can-base devicetree binding.
*
* @{
*/
/** offset cell index */
#define CAN_MCAN_MRAM_CFG_OFFSET 0
/** std-filter-elements cell index */
#define CAN_MCAN_MRAM_CFG_STD_FILTER 1
/** ext-filter-elements cell index */
#define CAN_MCAN_MRAM_CFG_EXT_FILTER 2
/** rx-fifo0-elements cell index */
#define CAN_MCAN_MRAM_CFG_RX_FIFO0 3
/** rx-fifo1-elements cell index */
#define CAN_MCAN_MRAM_CFG_RX_FIFO1 4
/** rx-buffer-elements cell index */
#define CAN_MCAN_MRAM_CFG_RX_BUFFER 5
/** tx-event-fifo-elements cell index */
#define CAN_MCAN_MRAM_CFG_TX_EVENT_FIFO 6
/** tx-buffer-elements cell index */
#define CAN_MCAN_MRAM_CFG_TX_BUFFER 7
/** Total number of cells in bosch,mram-cfg property */
#define CAN_MCAN_MRAM_CFG_NUM_CELLS 8
/** @} */
/**
* @brief Get the Bosch M_CAN Message RAM offset
*
* @param node_id node identifier
* @return the Message RAM offset in bytes
*/
#define CAN_MCAN_DT_MRAM_OFFSET(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_OFFSET)
/**
* @brief Get the number of standard (11-bit) filter elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the number of standard (11-bit) filter elements
*/
#define CAN_MCAN_DT_MRAM_STD_FILTER_ELEMENTS(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_STD_FILTER)
/**
* @brief Get the number of extended (29-bit) filter elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the number of extended (29-bit) filter elements
*/
#define CAN_MCAN_DT_MRAM_EXT_FILTER_ELEMENTS(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_EXT_FILTER)
/**
* @brief Get the number of Rx FIFO 0 elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the number of Rx FIFO 0 elements
*/
#define CAN_MCAN_DT_MRAM_RX_FIFO0_ELEMENTS(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_RX_FIFO0)
/**
* @brief Get the number of Rx FIFO 1 elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the number of Rx FIFO 1 elements
*/
#define CAN_MCAN_DT_MRAM_RX_FIFO1_ELEMENTS(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_RX_FIFO1)
/**
* @brief Get the number of Rx Buffer elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the number of Rx Buffer elements
*/
#define CAN_MCAN_DT_MRAM_RX_BUFFER_ELEMENTS(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_RX_BUFFER)
/**
* @brief Get the number of Tx Event FIFO elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the number of Tx Event FIFO elements
*/
#define CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_ELEMENTS(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_TX_EVENT_FIFO)
/**
* @brief Get the number of Tx Buffer elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the number of Tx Buffer elements
*/
#define CAN_MCAN_DT_MRAM_TX_BUFFER_ELEMENTS(node_id) \
DT_PROP_BY_IDX(node_id, bosch_mram_cfg, CAN_MCAN_MRAM_CFG_TX_BUFFER)
/**
* @brief Get the base offset of standard (11-bit) filter elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the base offset of standard (11-bit) filter elements in bytes
*/
#define CAN_MCAN_DT_MRAM_STD_FILTER_OFFSET(node_id) (0U)
/**
* @brief Get the base offset of extended (29-bit) filter elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the base offset of extended (29-bit) filter elements in bytes
*/
#define CAN_MCAN_DT_MRAM_EXT_FILTER_OFFSET(node_id) \
(CAN_MCAN_DT_MRAM_STD_FILTER_OFFSET(node_id) + \
CAN_MCAN_DT_MRAM_STD_FILTER_ELEMENTS(node_id) * sizeof(struct can_mcan_std_filter))
/**
* @brief Get the base offset of Rx FIFO 0 elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the base offset of Rx FIFO 0 elements in bytes
*/
#define CAN_MCAN_DT_MRAM_RX_FIFO0_OFFSET(node_id) \
(CAN_MCAN_DT_MRAM_EXT_FILTER_OFFSET(node_id) + \
CAN_MCAN_DT_MRAM_EXT_FILTER_ELEMENTS(node_id) * sizeof(struct can_mcan_ext_filter))
/**
* @brief Get the base offset of Rx FIFO 1 elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the base offset of Rx FIFO 1 elements in bytes
*/
#define CAN_MCAN_DT_MRAM_RX_FIFO1_OFFSET(node_id) \
(CAN_MCAN_DT_MRAM_RX_FIFO0_OFFSET(node_id) + \
CAN_MCAN_DT_MRAM_RX_FIFO0_ELEMENTS(node_id) * sizeof(struct can_mcan_rx_fifo))
/**
* @brief Get the base offset of Rx Buffer elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the base offset of Rx Buffer elements in bytes
*/
#define CAN_MCAN_DT_MRAM_RX_BUFFER_OFFSET(node_id) \
(CAN_MCAN_DT_MRAM_RX_FIFO1_OFFSET(node_id) + \
CAN_MCAN_DT_MRAM_RX_FIFO1_ELEMENTS(node_id) * sizeof(struct can_mcan_rx_fifo))
/**
* @brief Get the base offset of Tx Event FIFO elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the base offset of Tx Event FIFO elements in bytes
*/
#define CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_OFFSET(node_id) \
(CAN_MCAN_DT_MRAM_RX_BUFFER_OFFSET(node_id) + \
CAN_MCAN_DT_MRAM_RX_BUFFER_ELEMENTS(node_id) * sizeof(struct can_mcan_rx_fifo))
/**
* @brief Get the base offset of Tx Buffer elements in Bosch M_CAN Message RAM
*
* @param node_id node identifier
* @return the base offset of Tx Buffer elements in bytes
*/
#define CAN_MCAN_DT_MRAM_TX_BUFFER_OFFSET(node_id) \
(CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_OFFSET(node_id) + \
CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_ELEMENTS(node_id) * sizeof(struct can_mcan_tx_event_fifo))
/**
* @brief Get the Bosch M_CAN register base address
*
* For devicetree nodes with just one register block, this macro returns the base address of that
* register block.
*
* If a devicetree node has more than one register block, this macros returns the base address of
* the register block named "m_can".
*
* @param node_id node identifier
* @return the Bosch M_CAN register base address
*/
#define CAN_MCAN_DT_MCAN_ADDR(node_id) \
COND_CODE_1(DT_NUM_REGS(node_id), ((mm_reg_t)DT_REG_ADDR(node_id)), \
((mm_reg_t)DT_REG_ADDR_BY_NAME(node_id, m_can)))
/**
* @brief Get the Bosch M_CAN Message RAM base address
*
* For devicetree nodes with dedicated Message RAM area defined via devicetree, this macro returns
* the base address of the Message RAM.
*
* @param node_id node identifier
* @return the Bosch M_CAN Message RAM base address (MRBA)
*/
#define CAN_MCAN_DT_MRBA(node_id) \
(mem_addr_t)DT_REG_ADDR_BY_NAME(node_id, message_ram)
/**
* @brief Get the Bosch M_CAN Message RAM address
*
* For devicetree nodes with dedicated Message RAM area defined via devicetree, this macro returns
* the address of the Message RAM, taking in the Message RAM offset into account.
*
* @param node_id node identifier
* @return the Bosch M_CAN Message RAM address
*/
#define CAN_MCAN_DT_MRAM_ADDR(node_id) \
(mem_addr_t)(CAN_MCAN_DT_MRBA(node_id) + CAN_MCAN_DT_MRAM_OFFSET(node_id))
/**
* @brief Get the Bosch M_CAN Message RAM size
*
* For devicetree nodes with dedicated Message RAM area defined via devicetree, this macro returns
* the size of the Message RAM, taking in the Message RAM offset into account.
*
* @param node_id node identifier
* @return the Bosch M_CAN Message RAM base address
* @see CAN_MCAN_DT_MRAM_ELEMENTS_SIZE()
*/
#define CAN_MCAN_DT_MRAM_SIZE(node_id) \
(mem_addr_t)(DT_REG_SIZE_BY_NAME(node_id, message_ram) - CAN_MCAN_DT_MRAM_OFFSET(node_id))
/**
* @brief Get the total size of all Bosch M_CAN Message RAM elements
*
* @param node_id node identifier
* @return the total size of all Message RAM elements in bytes
* @see CAN_MCAN_DT_MRAM_SIZE()
*/
#define CAN_MCAN_DT_MRAM_ELEMENTS_SIZE(node_id) \
(CAN_MCAN_DT_MRAM_TX_BUFFER_OFFSET(node_id) + \
CAN_MCAN_DT_MRAM_TX_BUFFER_ELEMENTS(node_id) * sizeof(struct can_mcan_tx_buffer))
/**
* @brief Define a RAM buffer for Bosch M_CAN Message RAM
*
* For devicetree nodes without dedicated Message RAM area, this macro defines a suitable RAM buffer
* to hold the Message RAM elements. Since this buffer cannot be shared between multiple Bosch M_CAN
* instances, the Message RAM offset must be set to 0x0.
*
* @param node_id node identifier
* @param _name buffer variable name
*/
#define CAN_MCAN_DT_MRAM_DEFINE(node_id, _name) \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_OFFSET(node_id) == 0, "offset must be 0"); \
static char __noinit __nocache __aligned(4) _name[CAN_MCAN_DT_MRAM_ELEMENTS_SIZE(node_id)];
/**
* @brief Assert that the Message RAM configuration meets the Bosch M_CAN IP core restrictions
*
* @param node_id node identifier
*/
#define CAN_MCAN_DT_BUILD_ASSERT_MRAM_CFG(node_id) \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_STD_FILTER_ELEMENTS(node_id) <= 128, \
"Maximum Standard filter elements exceeded"); \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_EXT_FILTER_ELEMENTS(node_id) <= 64, \
"Maximum Extended filter elements exceeded"); \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_RX_FIFO0_ELEMENTS(node_id) <= 64, \
"Maximum Rx FIFO 0 elements exceeded"); \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_RX_FIFO1_ELEMENTS(node_id) <= 64, \
"Maximum Rx FIFO 1 elements exceeded"); \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_RX_BUFFER_ELEMENTS(node_id) <= 64, \
"Maximum Rx Buffer elements exceeded"); \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_ELEMENTS(node_id) <= 32, \
"Maximum Tx Buffer elements exceeded"); \
BUILD_ASSERT(CAN_MCAN_DT_MRAM_TX_BUFFER_ELEMENTS(node_id) <= 32, \
"Maximum Tx Buffer elements exceeded");
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the Message RAM offset in bytes
* @see CAN_MCAN_DT_MRAM_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_OFFSET(inst) CAN_MCAN_DT_MRAM_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_STD_FILTER_ELEMENTS(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the number of standard (11-bit) elements
* @see CAN_MCAN_DT_MRAM_STD_FILTER_ELEMENTS()
*/
#define CAN_MCAN_DT_INST_MRAM_STD_FILTER_ELEMENTS(inst) \
CAN_MCAN_DT_MRAM_STD_FILTER_ELEMENTS(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_EXT_FILTER_ELEMENTS(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the number of extended (29-bit) elements
* @see CAN_MCAN_DT_MRAM_EXT_FILTER_ELEMENTS()
*/
#define CAN_MCAN_DT_INST_MRAM_EXT_FILTER_ELEMENTS(inst) \
CAN_MCAN_DT_MRAM_EXT_FILTER_ELEMENTS(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_RX_FIFO0_ELEMENTS(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the number of Rx FIFO 0 elements
* @see CAN_MCAN_DT_MRAM_RX_FIFO0_ELEMENTS()
*/
#define CAN_MCAN_DT_INST_MRAM_RX_FIFO0_ELEMENTS(inst) \
CAN_MCAN_DT_MRAM_RX_FIFO0_ELEMENTS(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_RX_FIFO1_ELEMENTS(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the number of Rx FIFO 1 elements
* @see CAN_MCAN_DT_MRAM_RX_FIFO1_ELEMENTS()
*/
#define CAN_MCAN_DT_INST_MRAM_RX_FIFO1_ELEMENTS(inst) \
CAN_MCAN_DT_MRAM_RX_FIFO1_ELEMENTS(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_RX_BUFFER_ELEMENTS(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the number of Rx Buffer elements
* @see CAN_MCAN_DT_MRAM_RX_BUFFER_ELEMENTS()
*/
#define CAN_MCAN_DT_INST_MRAM_RX_BUFFER_ELEMENTS(inst) \
CAN_MCAN_DT_MRAM_RX_BUFFER_ELEMENTS(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_ELEMENTS(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the number of Tx Event FIFO elements
* @see CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_ELEMENTS()
*/
#define CAN_MCAN_DT_INST_MRAM_TX_EVENT_FIFO_ELEMENTS(inst) \
CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_ELEMENTS(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_TX_BUFFER_ELEMENTS(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the number of Tx Buffer elements
* @see CAN_MCAN_DT_MRAM_TX_BUFFER_ELEMENTS()
*/
#define CAN_MCAN_DT_INST_MRAM_TX_BUFFER_ELEMENTS(inst) \
CAN_MCAN_DT_MRAM_TX_BUFFER_ELEMENTS(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_STD_FILTER_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the base offset of standard (11-bit) filter elements in bytes
* @see CAN_MCAN_DT_MRAM_STD_FILTER_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_STD_FILTER_OFFSET(inst) \
CAN_MCAN_DT_MRAM_STD_FILTER_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_EXT_FILTER_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the base offset of extended (29-bit) filter elements in bytes
* @see CAN_MCAN_DT_MRAM_EXT_FILTER_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_EXT_FILTER_OFFSET(inst) \
CAN_MCAN_DT_MRAM_EXT_FILTER_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_RX_FIFO0_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the base offset of Rx FIFO 0 elements in bytes
* @see CAN_MCAN_DT_MRAM_RX_FIFO0_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_RX_FIFO0_OFFSET(inst) \
CAN_MCAN_DT_MRAM_RX_FIFO0_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_RX_FIFO1_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the base offset of Rx FIFO 1 elements in bytes
* @see CAN_MCAN_DT_MRAM_RX_FIFO1_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_RX_FIFO1_OFFSET(inst) \
CAN_MCAN_DT_MRAM_RX_FIFO1_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_RX_BUFFER_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the base offset of Rx Buffer elements in bytes
* @see CAN_MCAN_DT_MRAM_RX_BUFFER_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_RX_BUFFER_OFFSET(inst) \
CAN_MCAN_DT_MRAM_RX_BUFFER_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the base offset of Tx Event FIFO elements in bytes
* @see CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_TX_EVENT_FIFO_OFFSET(inst) \
CAN_MCAN_DT_MRAM_TX_EVENT_FIFO_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_TX_BUFFER_OFFSET(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the base offset of Tx Buffer elements in bytes
* @see CAN_MCAN_DT_MRAM_TX_BUFFER_OFFSET()
*/
#define CAN_MCAN_DT_INST_MRAM_TX_BUFFER_OFFSET(inst) \
CAN_MCAN_DT_MRAM_TX_BUFFER_OFFSET(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MCAN_ADDR(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the Bosch M_CAN register base address
* @see CAN_MCAN_DT_MRAM_ADDR()
*/
#define CAN_MCAN_DT_INST_MCAN_ADDR(inst) CAN_MCAN_DT_MCAN_ADDR(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRBA(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the Bosch M_CAN Message RAM Base Address (MRBA)
* @see CAN_MCAN_DT_MRBA()
*/
#define CAN_MCAN_DT_INST_MRBA(inst) CAN_MCAN_DT_MRBA(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_ADDR(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the Bosch M_CAN Message RAM address
* @see CAN_MCAN_DT_MRAM_ADDR()
*/
#define CAN_MCAN_DT_INST_MRAM_ADDR(inst) CAN_MCAN_DT_MRAM_ADDR(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_SIZE(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the Bosch M_CAN Message RAM size in bytes
* @see CAN_MCAN_DT_MRAM_SIZE()
*/
#define CAN_MCAN_DT_INST_MRAM_SIZE(inst) CAN_MCAN_DT_MRAM_SIZE(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_ELEMENTS_SIZE(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @return the total size of all Message RAM elements in bytes
* @see CAN_MCAN_DT_MRAM_ELEMENTS_SIZE()
*/
#define CAN_MCAN_DT_INST_MRAM_ELEMENTS_SIZE(inst) CAN_MCAN_DT_MRAM_ELEMENTS_SIZE(DT_DRV_INST(inst))
/**
* @brief Equivalent to CAN_MCAN_DT_MRAM_DEFINE(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @param _name buffer variable name
* @see CAN_MCAN_DT_MRAM_DEFINE()
*/
#define CAN_MCAN_DT_INST_MRAM_DEFINE(inst, _name) CAN_MCAN_DT_MRAM_DEFINE(DT_DRV_INST(inst), _name)
/**
* @brief Bosch M_CAN specific static initializer for a minimum nominal @p can_timing struct
*/
#define CAN_MCAN_TIMING_MIN_INITIALIZER \
{ \
.sjw = 1, \
.prop_seg = 0, \
.phase_seg1 = 2, \
.phase_seg2 = 2, \
.prescaler = 1 \
}
/**
* @brief Bosch M_CAN specific static initializer for a maximum nominal @p can_timing struct
*/
#define CAN_MCAN_TIMING_MAX_INITIALIZER \
{ \
.sjw = 128, \
.prop_seg = 0, \
.phase_seg1 = 256, \
.phase_seg2 = 128, \
.prescaler = 512 \
}
/**
* @brief Bosch M_CAN specific static initializer for a minimum data phase @p can_timing struct
*/
#define CAN_MCAN_TIMING_DATA_MIN_INITIALIZER \
{ \
.sjw = 1, \
.prop_seg = 0, \
.phase_seg1 = 1, \
.phase_seg2 = 1, \
.prescaler = 1 \
}
/**
* @brief Bosch M_CAN specific static initializer for a maximum data phase @p can_timing struct
*/
#define CAN_MCAN_TIMING_DATA_MAX_INITIALIZER \
{ \
.sjw = 16, \
.prop_seg = 0, \
.phase_seg1 = 32, \
.phase_seg2 = 16, \
.prescaler = 32 \
}
/**
* @brief Equivalent to CAN_MCAN_DT_BUILD_ASSERT_MRAM_CFG(DT_DRV_INST(inst))
* @param inst DT_DRV_COMPAT instance number
* @see CAN_MCAN_DT_BUILD_ASSERT_MRAM_CFG()
*/
#define CAN_MCAN_DT_INST_BUILD_ASSERT_MRAM_CFG(inst) \
CAN_MCAN_DT_BUILD_ASSERT_MRAM_CFG(DT_DRV_INST(inst))
/**
* @brief Bosch M_CAN Rx Buffer and FIFO Element header
*
* See Bosch M_CAN Users Manual section 2.4.2 for details.
*/
struct can_mcan_rx_fifo_hdr {
union {
struct {
uint32_t ext_id: 29;
uint32_t rtr: 1;
uint32_t xtd: 1;
uint32_t esi: 1;
};
struct {
uint32_t pad1: 18;
uint32_t std_id: 11;
uint32_t pad2: 3;
};
};
uint32_t rxts: 16;
uint32_t dlc: 4;
uint32_t brs: 1;
uint32_t fdf: 1;
uint32_t res: 2;
uint32_t fidx: 7;
uint32_t anmf: 1;
} __packed __aligned(4);
/**
* @brief Bosch M_CAN Rx Buffer and FIFO Element
*
* See Bosch M_CAN Users Manual section 2.4.2 for details.
*/
struct can_mcan_rx_fifo {
struct can_mcan_rx_fifo_hdr hdr;
union {
uint8_t data[64];
uint32_t data_32[16];
};
} __packed __aligned(4);
/**
* @brief Bosch M_CAN Tx Buffer Element header
*
* See Bosch M_CAN Users Manual section 2.4.3 for details.
*/
struct can_mcan_tx_buffer_hdr {
union {
struct {
uint32_t ext_id: 29;
uint32_t rtr: 1;
uint32_t xtd: 1;
uint32_t esi: 1;
};
struct {
uint32_t pad1: 18;
uint32_t std_id: 11;
uint32_t pad2: 3;
};
};
uint16_t res1;
uint8_t dlc: 4;
uint8_t brs: 1;
uint8_t fdf: 1;
uint8_t tsce: 1;
uint8_t efc: 1;
uint8_t mm;
} __packed __aligned(4);
/**
* @brief Bosch M_CAN Tx Buffer Element
*
* See Bosch M_CAN Users Manual section 2.4.3 for details.
*/
struct can_mcan_tx_buffer {
struct can_mcan_tx_buffer_hdr hdr;
union {
uint8_t data[64];
uint32_t data_32[16];
};
} __packed __aligned(4);
/**
* @brief Bosch M_CAN Tx Event FIFO Element
*
* See Bosch M_CAN Users Manual section 2.4.4 for details.
*/
struct can_mcan_tx_event_fifo {
union {
struct {
uint32_t ext_id: 29;
uint32_t rtr: 1;
uint32_t xtd: 1;
uint32_t esi: 1;
};
struct {
uint32_t pad1: 18;
uint32_t std_id: 11;
uint32_t pad2: 3;