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bluetooth-ctlr-arch.rst

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LE Controller

Overview

img/ctlr_overview.png

  1. HCI
    • Host Controller Interface, Bluetooth standard
    • Provides Zephyr Bluetooth HCI Driver
  2. HAL
    • Hardware Abstraction Layer
    • Vendor Specific, and Zephyr Driver usage
  3. Ticker
    • Soft real time radio/resource scheduling
  4. LL_SW
    • Software-based Link Layer implementation
    • States and roles, control procedures, packet controller
  5. Util
    • Bare metal memory pool management
    • Queues of variable count, lockless usage
    • FIFO of fixed count, lockless usage
    • Mayfly concept based deferred ISR executions

Architecture

Execution Overview

img/ctlr_exec_overview.png

Architecture Overview

img/ctlr_arch_overview.png

Scheduling

img/ctlr_sched.png

Ticker

img/ctlr_sched_ticker.png

Upper Link Layer and Lower Link Layer

img/ctlr_sched_ull_lll.png

Scheduling Variants

img/ctlr_sched_variant.png

ULL and LLL Timing

img/ctlr_sched_ull_lll_timing.png

Event Handling

img/ctlr_sched_event_handling.png

Scheduling Closely Spaced Events

img/ctlr_sched_msc_close_events.png

Aborting Active Event

img/ctlr_sched_msc_event_abort.png

Cancelling Pending Event

img/ctlr_sched_msc_event_cancel.png

Pre-emption of Active Event

img/ctlr_sched_msc_event_preempt.png

Data Flow

Transmit Data Flow

img/ctlr_dataflow_tx.png

Receive Data Flow

img/ctlr_dataflow_rx.png

Execution Priorities

img/ctlr_exec_prio.png

  • Event handle (0, 1) < Event preparation (2, 3) < Event/Rx done (4) < Tx request (5) < Role management (6) < Host (7).
  • LLL is vendor ISR, ULL is Mayfly ISR concept, Host is kernel thread.

Lower Link Layer

LLL Execution

img/ctlr_exec_lll.png

LLL Resume

img/ctlr_exec_lll_resume_top.png

img/ctlr_exec_lll_resume_bottom.png

Bare metal utilities

Memory FIFO and Memory Queue

img/ctlr_mfifo_memq.png

Mayfly

img/ctlr_mayfly.png

  • Mayfly are multi-instance scalable ISR execution contexts
  • What a Work is to a Thread, Mayfly is to an ISR
  • List of functions executing in ISRs
  • Execution priorities map to IRQ priorities
  • Facilitate cross execution context scheduling
  • Race-to-idle execution
  • Lock-less, bare metal

Legacy Controller

img/ctlr_legacy.png

Bluetooth Low Energy Controller - Vendor Specific Details

Hardware Requirements

Nordic Semiconductor

The Nordic Semiconductor Bluetooth Low Energy Controller implementation requires the following hardware peripherals.

SoC Peripheral Use
Resource nRF Peripheral # instances Zephyr Driver Accessible Description
Clock NRF_CLOCK 1 Yes
  • A Low Frequency Clock (LFCLOCK) or sleep clock, for low power consumption between Bluetooth radio events
  • A High Frequency Clock (HFCLOCK) or active clock, for high precision packet timing and software based transceiver state switching with inter-frame space (tIFS) timing inside Bluetooth radio events
RTC [a] NRF_RTC0 1 No
  • Uses 2 capture/compare registers
Timer NRF_TIMER0 or NRF_TIMER4 [1], and NRF_TIMER1 [0] 2 or 1 [1] No
  • 2 instances, one each for packet timing and tIFS software switching, respectively
  • 7 capture/compare registers (3 mandatory, 1 optional for ISR profiling, 4 for single timer tIFS switching) on first instance
  • 4 capture/compare registers for second instance, if single tIFS timer is not used.
PPI [b] NRF_PPI 21 channels (20 [2]), and 2 channel groups [3] Yes [4]
  • Used for radio mode switching to achieve tIFS timings, for PA/LNA control
DPPI [c] NRF_DPPI 20 channels, and 2 channel groups [3] Yes [4]
  • Used for radio mode switching to achieve tIFS timings, for PA/LNA control
SWI [d] NRF_SWI4 and NRF_SWI5, or NRF_SWI2 and NRF_SWI3 [5] 2 No
  • 2 instances, for Lower Link Layer and Upper Link Layer Low priority execution context
Radio NRF_RADIO 1 No
  • 2.4 GHz radio transceiver with multiple radio standards such as 1 Mbps, 2 Mbps and Coded PHY S2/S8 Long Range Bluetooth Low Energy technology
RNG [e] NRF_RNG 1 Yes  
ECB [f] NRF_ECB 1 No  
CBC-CCM [g] NRF_CCM 1 No  
AAR [h] NRF_AAR 1 No  
GPIO [i] NRF_GPIO 2 GPIO pins for PA and LNA, 1 each Yes
  • Additionally, 10 Debug GPIO pins (optional)
GPIOTE [j] NRF_GPIOTE 1 Yes
  • Used for PA/LNA
TEMP [k] NRF_TEMP 1 Yes
  • For RC sourced LFCLOCK calibration
UART [l] NRF_UART0 1 Yes
  • For HCI interface in Controller only builds
IPC [m] NRF_IPC [5] 1 Yes
  • For HCI interface in Controller only builds
[a]Real Time Counter (RTC)
[b]Programmable Peripheral Interconnect (PPI)
[c]Distributed Programmable Peripheral Interconnect (DPPI)
[d]Software Interrupt (SWI)
[e]Random Number Generator (RNG)
[f]AES Electronic Codebook Mode Encryption (ECB)
[g]Cipher Block Chaining (CBC) - Message Authentication Code with Counter Mode encryption (CCM)
[h]Accelerated Address Resolver (AAR)
[i]General Purpose Input Output (GPIO)
[j]GPIO tasks and events (GPIOTE)
[k]Temperature sensor (TEMP)
[l]Universal Asynchronous Receiver Transmitter (UART)
[m]Interprocess Communication peripheral (IPC)
[0]:kconfig:option:`CONFIG_BT_CTLR_TIFS_HW` =n
[1](1, 2) :kconfig:option:`CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER` =y
[2]When not using pre-defined PPI channels
[3](1, 2) For software-based tIFS switching
[4](1, 2) Drivers that use nRFx interfaces
[5](1, 2) For nRF53x Series