dts : arm : Add Microchip MEC1501 SoC device tree

Initial support for Microchip MEC1501 series is added to the tree.
Additional support for UART is also included. This SoC supports
two operational modes for interrupts (Direct and Aggregated). For
this commit, the direct capable interrupts are configured in
direct mode.

Signed-off-by: Scott Worley <scott.worley@microchip.com>

CODEOWNERS

@@ -153,6 +153,7 @@
 /dts/arm/st/                              @erwango
 /dts/arm/nordic/                          @ioannisg @carlescufi
 /dts/arm/nxp/                             @MaureenHelm
+/dts/arm/microchip/                       @franciscomunoz @albertofloyd @scottwcpg
 /dts/bindings/                            @galak
 /dts/bindings/can/                        @alexanderwachter
 /dts/bindings/serial/ns16550.yaml         @gnuless

dts/arm/microchip/mec1501hsz.dtsi

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4";
+			reg = <0>;
+		};
+	};
+
+	flash0: flash@e0000 {
+		reg = <0x000E0000 0x38000>;
+	};
+
+	sram0: memory@118000 {
+		compatible = "mmio-sram";
+		reg = <0x00118000 0x8000>;
+	};
+
+	soc {
+		uart0: uart@400f2400 {
+			compatible = "ns16550";
+			reg = <0x400f2400 0x400>;
+			interrupts = <40 0>;
+			current-speed = <38400>;
+			label = "UART_0";
+			reg-shift = <0>;
+		};
+		uart1: uart@400f2800 {
+			compatible = "ns16550";
+			reg = <0x400f2800 0x400>;
+			interrupts = <41 0>;
+			current-speed = <38400>;
+			label = "UART_1";
+			reg-shift = <0>;
+		};
+		uart2: uart@400f2c00 {
+			compatible = "ns16550";
+			reg = <0x400f2c00 0x400>;
+			interrupts = <44 0>;
+			current-speed = <38400>;
+			label = "UART_2";
+			reg-shift = <0>;
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};