can we increase qemu_riscv32/64 RAM sizes

[andrewboie]

Both qemu_riscv32 and qemu_riscv64 inherit from the riscv32-fe10.dtsi which provides only 16KB of RAM.

This prevents a lot of larger test cases from running on RISCV under emulation in QEMU.

Can we change this? I'd suggest a couple megabytes which would allow the largest tests to run. But anything is better than 16KB.

I tried overriding &dtim in the board-level DTS to increase RAM size but this just caused QEMU to crash.

[andrewboie]

@nategraff-sifive FYI

[nategraff-sifive]

All this needs to work is a patch to QEMU to increase the amount of emulated DTIM.

[0xAl3xH]

All this needs to work is a patch to QEMU to increase the amount of emulated DTIM.

How does one do this? Is there a config setting somewhere?

[nategraff-sifive]

It just needs a patch in the Zephyr SDK sources which alters the size of the DTIM in hw/riscv/sifive_e.c in the QEMU source tree.

You'd want to edit this struct:

static const struct MemmapEntry {
    hwaddr base;
    hwaddr size;
} sifive_e_memmap[] = {
    ...
    [SIFIVE_E_DTIM] =     { 0x80000000,     0x4000 }
};

Just increase the second number to something like 0x400000

[andrewboie]

There's no other way to do this other than patching the QEMU source code?

[nategraff-sifive]

QEMU hard-codes the size of the DTIM 🤷‍♂ There might be a more elegant way but I'm not familiar enough with QEMU to know.