drivers: ethernet: enc28j60: ESTAT TXABRT bit should be cleared on error

[zkrx]

We have a custom board using Zephyr 2.7 and an SPI ethernet chip enc28j60. The custom board is connected to my laptop using ethernet. I encountered a bug where the driver would continuously spam the serial console with the following message:

[00:19:37.315,000] <err> eth_enc28j60: TX failed!
[00:19:37.524,000] <err> eth_enc28j60: TX failed!
[00:19:37.532,000] <err> eth_enc28j60: TX failed!
[00:19:37.541,000] <err> eth_enc28j60: TX failed!
[00:19:37.550,000] <err> eth_enc28j60: TX failed!
[00:19:37.703,000] <err> eth_enc28j60: TX failed!

Our board sends packets every second. On each sent packet, the "TX failed!" message would be shown. I could see all packets on my laptop with Wireshark, so they were all correctly sent.

In the enc28j60 datasheet, the following is written under 12.1.3 TRANSMIT ERROR INTERRUPT FLAG (TXERIF):

After determining the problem and solution, the
host controller should clear the LATECOL (if set) and
TXABRT bits so that future aborts can be detected
accurately.

Therefore, I conclude that if the TXABRT is ever detected on the following line:

zephyr/drivers/ethernet/eth_enc28j60.c

Line 528 in 35429de

if (tx_end & ENC28J60_BIT_ESTAT_TXABRT) {

it should be manually cleared.

The problem is hard to reproduce (I don't know why I had a TX error in the first place, it seems to happen very rarely). In order to confirm without resetting the device, I used gdb and put a breakpoint in eth_enc28j60_clear_eth_reg(). I landed in eth_enc28j60_rx_thread() here:

zephyr/drivers/ethernet/eth_enc28j60.c

Line 692 in a1cdf27

eth_enc28j60_clear_eth_reg(dev, ENC28J60_REG_EIR,

zephyr/drivers/ethernet/eth_enc28j60.c

Line 181 in a1cdf27

spi_write_dt(&config->spi, &tx);

And changed buf[0] from 0xbc to 0xbd and buf[1] from 0x41 to 0x2, which would be equivalent to doing the following call:

eth_enc28j60_clear_eth_reg(dev, ENC28J60_REG_ESTAT, ENC28J60_BIT_ESTAT_TXABRT);

Hit Continue and TX error messages disappeared, the device continued working normally.

I will create a PR soon.