forked from riscv-collab/riscv-openjdk
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macroAssembler_riscv64.cpp
3680 lines (3194 loc) · 127 KB
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macroAssembler_riscv64.cpp
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/*
* Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* Copyright (c) 2020, 2021, Huawei Technologies Co., Ltd. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 only, as
* published by the Free Software Foundation.
*
* This code is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* version 2 for more details (a copy is included in the LICENSE file that
* accompanied this code).
*
* You should have received a copy of the GNU General Public License version
* 2 along with this work; if not, write to the Free Software Foundation,
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
* or visit www.oracle.com if you need additional information or have any
* questions.
*
*/
#include "precompiled.hpp"
#include "asm/assembler.hpp"
#include "asm/assembler.inline.hpp"
#include "compiler/disassembler.hpp"
#include "gc/shared/barrierSet.hpp"
#include "gc/shared/barrierSetAssembler.hpp"
#include "gc/shared/cardTable.hpp"
#include "gc/shared/cardTableBarrierSet.hpp"
#include "interpreter/bytecodeHistogram.hpp"
#include "interpreter/interpreter.hpp"
#include "memory/resourceArea.hpp"
#include "memory/universe.hpp"
#include "nativeInst_riscv64.hpp"
#include "oops/accessDecorators.hpp"
#include "oops/compressedOops.inline.hpp"
#include "oops/klass.inline.hpp"
#include "oops/oop.hpp"
#include "runtime/biasedLocking.hpp"
#include "runtime/interfaceSupport.inline.hpp"
#include "runtime/jniHandles.inline.hpp"
#include "runtime/sharedRuntime.hpp"
#include "runtime/stubRoutines.hpp"
#include "runtime/thread.hpp"
#include "utilities/powerOfTwo.hpp"
#ifdef COMPILER2
#include "opto/compile.hpp"
#include "opto/node.hpp"
#include "opto/output.hpp"
#endif
#ifdef PRODUCT
#define BLOCK_COMMENT(str) /* nothing */
#else
#define BLOCK_COMMENT(str) block_comment(str)
#endif
#define BIND(label) bind(label); __ BLOCK_COMMENT(#label ":")
static void pass_arg0(MacroAssembler* masm, Register arg) {
if (c_rarg0 != arg) {
assert_cond(masm != NULL);
masm->mv(c_rarg0, arg);
}
}
static void pass_arg1(MacroAssembler* masm, Register arg) {
if (c_rarg1 != arg) {
assert_cond(masm != NULL);
masm->mv(c_rarg1, arg);
}
}
static void pass_arg2(MacroAssembler* masm, Register arg) {
if (c_rarg2 != arg) {
assert_cond(masm != NULL);
masm->mv(c_rarg2, arg);
}
}
static void pass_arg3(MacroAssembler* masm, Register arg) {
if (c_rarg3 != arg) {
assert_cond(masm != NULL);
masm->mv(c_rarg3, arg);
}
}
void MacroAssembler::align(int modulus) {
while (offset() % modulus != 0) { nop(); }
}
void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
}
// Implementation of call_VM versions
void MacroAssembler::call_VM(Register oop_result,
address entry_point,
bool check_exceptions) {
call_VM_helper(oop_result, entry_point, 0, check_exceptions);
}
void MacroAssembler::call_VM(Register oop_result,
address entry_point,
Register arg_1,
bool check_exceptions) {
pass_arg1(this, arg_1);
call_VM_helper(oop_result, entry_point, 1, check_exceptions);
}
void MacroAssembler::call_VM(Register oop_result,
address entry_point,
Register arg_1,
Register arg_2,
bool check_exceptions) {
assert(arg_1 != c_rarg2, "smashed arg");
pass_arg2(this, arg_2);
pass_arg1(this, arg_1);
call_VM_helper(oop_result, entry_point, 2, check_exceptions);
}
void MacroAssembler::call_VM(Register oop_result,
address entry_point,
Register arg_1,
Register arg_2,
Register arg_3,
bool check_exceptions) {
assert(arg_1 != c_rarg3, "smashed arg");
assert(arg_2 != c_rarg3, "smashed arg");
pass_arg3(this, arg_3);
assert(arg_1 != c_rarg2, "smashed arg");
pass_arg2(this, arg_2);
pass_arg1(this, arg_1);
call_VM_helper(oop_result, entry_point, 3, check_exceptions);
}
void MacroAssembler::call_VM(Register oop_result,
Register last_java_sp,
address entry_point,
int number_of_arguments,
bool check_exceptions) {
call_VM_base(oop_result, xthread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
}
void MacroAssembler::call_VM(Register oop_result,
Register last_java_sp,
address entry_point,
Register arg_1,
bool check_exceptions) {
pass_arg1(this, arg_1);
call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
}
void MacroAssembler::call_VM(Register oop_result,
Register last_java_sp,
address entry_point,
Register arg_1,
Register arg_2,
bool check_exceptions) {
assert(arg_1 != c_rarg2, "smashed arg");
pass_arg2(this, arg_2);
pass_arg1(this, arg_1);
call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
}
void MacroAssembler::call_VM(Register oop_result,
Register last_java_sp,
address entry_point,
Register arg_1,
Register arg_2,
Register arg_3,
bool check_exceptions) {
assert(arg_1 != c_rarg3, "smashed arg");
assert(arg_2 != c_rarg3, "smashed arg");
pass_arg3(this, arg_3);
assert(arg_1 != c_rarg2, "smashed arg");
pass_arg2(this, arg_2);
pass_arg1(this, arg_1);
call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
}
// these are no-ops overridden by InterpreterMacroAssembler
void MacroAssembler::check_and_handle_earlyret(Register java_thread) {}
void MacroAssembler::check_and_handle_popframe(Register java_thread) {}
// Calls to C land
//
// When entering C land, the fp, & esp of the last Java frame have to be recorded
// in the (thread-local) JavaThread object. When leaving C land, the last Java fp
// has to be reset to 0. This is required to allow proper stack traversal.
void MacroAssembler::set_last_Java_frame(Register last_java_sp,
Register last_java_fp,
Register last_java_pc,
Register temp) {
if (last_java_pc->is_valid()) {
sd(last_java_pc, Address(xthread,
JavaThread::frame_anchor_offset() +
JavaFrameAnchor::last_Java_pc_offset()));
}
// determine last_java_sp register
if (last_java_sp == sp) {
mv(temp, sp);
last_java_sp = temp;
} else if (!last_java_sp->is_valid()) {
last_java_sp = esp;
}
sd(last_java_sp, Address(xthread, JavaThread::last_Java_sp_offset()));
// last_java_fp is optional
if (last_java_fp->is_valid()) {
sd(last_java_fp, Address(xthread, JavaThread::last_Java_fp_offset()));
}
}
void MacroAssembler::set_last_Java_frame(Register last_java_sp,
Register last_java_fp,
address last_java_pc,
Register temp) {
assert(last_java_pc != NULL, "must provide a valid PC");
la(temp, last_java_pc);
sd(temp, Address(xthread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()));
set_last_Java_frame(last_java_sp, last_java_fp, noreg, temp);
}
void MacroAssembler::set_last_Java_frame(Register last_java_sp,
Register last_java_fp,
Label &L,
Register temp) {
if (L.is_bound()) {
set_last_Java_frame(last_java_sp, last_java_fp, target(L), temp);
} else {
InstructionMark im(this);
L.add_patch_at(code(), locator());
set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, temp);
}
}
void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
// we must set sp to zero to clear frame
sd(zr, Address(xthread, JavaThread::last_Java_sp_offset()));
// must clear fp, so that compiled frames are not confused; it is
// possible that we need it only for debugging
if (clear_fp) {
sd(zr, Address(xthread, JavaThread::last_Java_fp_offset()));
}
// Always clear the pc because it could have been set by make_walkable()
sd(zr, Address(xthread, JavaThread::last_Java_pc_offset()));
}
void MacroAssembler::call_VM_base(Register oop_result,
Register java_thread,
Register last_java_sp,
address entry_point,
int number_of_arguments,
bool check_exceptions) {
// determine java_thread register
if (!java_thread->is_valid()) {
java_thread = xthread;
}
// determine last_java_sp register
if (!last_java_sp->is_valid()) {
last_java_sp = esp;
}
// debugging support
assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
assert(java_thread == xthread, "unexpected register");
assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
// push java thread (becomes first argument of C function)
mv(c_rarg0, java_thread);
// set last Java frame before call
assert(last_java_sp != fp, "can't use fp");
Label l;
set_last_Java_frame(last_java_sp, fp, l, t0);
// do the call, remove parameters
MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
// reset last Java frame
// Only interpreter should have to clear fp
reset_last_Java_frame(true);
// C++ interp handles this in the interpreter
check_and_handle_popframe(java_thread);
check_and_handle_earlyret(java_thread);
if (check_exceptions) {
// check for pending exceptions (java_thread is set upon return)
ld(t0, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
Label ok;
beqz(t0, ok);
int32_t offset = 0;
la_patchable(t0, RuntimeAddress(StubRoutines::forward_exception_entry()), offset);
jalr(x0, t0, offset);
bind(ok);
}
// get oop result if there is one and reset the value in the thread
if (oop_result->is_valid()) {
get_vm_result(oop_result, java_thread);
}
}
void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
ld(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
sd(zr, Address(java_thread, JavaThread::vm_result_offset()));
verify_oop(oop_result, "broken oop in call_VM_base");
}
void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
ld(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
sd(zr, Address(java_thread, JavaThread::vm_result_2_offset()));
}
void MacroAssembler::clinit_barrier(Register klass, Register tmp, Label* L_fast_path, Label* L_slow_path) {
assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required");
assert_different_registers(klass, xthread, tmp);
Label L_fallthrough, L_tmp;
if (L_fast_path == NULL) {
L_fast_path = &L_fallthrough;
} else if (L_slow_path == NULL) {
L_slow_path = &L_fallthrough;
}
// Fast path check: class is fully initialized
lbu(tmp, Address(klass, InstanceKlass::init_state_offset()));
sub(tmp, tmp, InstanceKlass::fully_initialized);
beqz(tmp, *L_fast_path);
// Fast path check: current thread is initializer thread
ld(tmp, Address(klass, InstanceKlass::init_thread_offset()));
if (L_slow_path == &L_fallthrough) {
beq(xthread, tmp, *L_fast_path);
bind(*L_slow_path);
} else if (L_fast_path == &L_fallthrough) {
bne(xthread, tmp, *L_slow_path);
bind(*L_fast_path);
} else {
Unimplemented();
}
}
void MacroAssembler::verify_oop(Register reg, const char* s) {
if (!VerifyOops) { return; }
// Pass register number to verify_oop_subroutine
const char* b = NULL;
{
ResourceMark rm;
stringStream ss;
ss.print("verify_oop: %s: %s", reg->name(), s);
b = code_string(ss.as_string());
}
BLOCK_COMMENT("verify_oop {");
push_reg(RegSet::of(lr, t0, t1, c_rarg0), sp);
mv(c_rarg0, reg); // c_rarg0 : x10
if(b != NULL) {
li(t0, (uintptr_t)(address)b);
} else {
ShouldNotReachHere();
}
// call indirectly to solve generation ordering problem
int32_t offset = 0;
la_patchable(t1, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()), offset);
ld(t1, Address(t1, offset));
jalr(t1);
pop_reg(RegSet::of(lr, t0, t1, c_rarg0), sp);
BLOCK_COMMENT("} verify_oop");
}
void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
if (!VerifyOops) {
return;
}
const char* b = NULL;
{
ResourceMark rm;
stringStream ss;
ss.print("verify_oop_addr: %s", s);
b = code_string(ss.as_string());
}
BLOCK_COMMENT("verify_oop_addr {");
push_reg(RegSet::of(lr, t0, t1, c_rarg0), sp);
if (addr.uses(sp)) {
la(x10, addr);
ld(x10, Address(x10, 4 * wordSize));
} else {
ld(x10, addr);
}
if(b != NULL) {
li(t0, (uintptr_t)(address)b);
} else {
ShouldNotReachHere();
}
// call indirectly to solve generation ordering problem
int32_t offset = 0;
la_patchable(t1, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()), offset);
ld(t1, Address(t1, offset));
jalr(t1);
pop_reg(RegSet::of(lr, t0, t1, c_rarg0), sp);
BLOCK_COMMENT("} verify_oop_addr");
}
Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
int extra_slot_offset) {
// cf. TemplateTable::prepare_invoke(), if (load_receiver).
int stackElementSize = Interpreter::stackElementSize;
int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
#ifdef ASSERT
int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
assert(offset1 - offset == stackElementSize, "correct arithmetic");
#endif
if (arg_slot.is_constant()) {
return Address(esp, arg_slot.as_constant() * stackElementSize + offset);
} else {
assert_different_registers(t0, arg_slot.as_register());
slli(t0, arg_slot.as_register(), log2i_exact(stackElementSize));
add(t0, esp, t0);
return Address(t0, offset);
}
}
#ifndef PRODUCT
extern "C" void findpc(intptr_t x);
#endif
void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
{
// In order to get locks to work, we need to fake a in_VM state
if (ShowMessageBoxOnError) {
JavaThread* thread = JavaThread::current();
JavaThreadState saved_state = thread->thread_state();
thread->set_thread_state(_thread_in_vm);
#ifndef PRODUCT
if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
ttyLocker ttyl;
BytecodeCounter::print();
}
#endif
if (os::message_box(msg, "Execution stopped, print registers?")) {
ttyLocker ttyl;
tty->print_cr(" pc = 0x%016lx", pc);
#ifndef PRODUCT
tty->cr();
findpc(pc);
tty->cr();
#endif
tty->print_cr(" x0 = 0x%016lx", regs[0]);
tty->print_cr(" x1 = 0x%016lx", regs[1]);
tty->print_cr(" x2 = 0x%016lx", regs[2]);
tty->print_cr(" x3 = 0x%016lx", regs[3]);
tty->print_cr(" x4 = 0x%016lx", regs[4]);
tty->print_cr(" x5 = 0x%016lx", regs[5]);
tty->print_cr(" x6 = 0x%016lx", regs[6]);
tty->print_cr(" x7 = 0x%016lx", regs[7]);
tty->print_cr(" x8 = 0x%016lx", regs[8]);
tty->print_cr(" x9 = 0x%016lx", regs[9]);
tty->print_cr("x10 = 0x%016lx", regs[10]);
tty->print_cr("x11 = 0x%016lx", regs[11]);
tty->print_cr("x12 = 0x%016lx", regs[12]);
tty->print_cr("x13 = 0x%016lx", regs[13]);
tty->print_cr("x14 = 0x%016lx", regs[14]);
tty->print_cr("x15 = 0x%016lx", regs[15]);
tty->print_cr("x16 = 0x%016lx", regs[16]);
tty->print_cr("x17 = 0x%016lx", regs[17]);
tty->print_cr("x18 = 0x%016lx", regs[18]);
tty->print_cr("x19 = 0x%016lx", regs[19]);
tty->print_cr("x20 = 0x%016lx", regs[20]);
tty->print_cr("x21 = 0x%016lx", regs[21]);
tty->print_cr("x22 = 0x%016lx", regs[22]);
tty->print_cr("x23 = 0x%016lx", regs[23]);
tty->print_cr("x24 = 0x%016lx", regs[24]);
tty->print_cr("x25 = 0x%016lx", regs[25]);
tty->print_cr("x26 = 0x%016lx", regs[26]);
tty->print_cr("x27 = 0x%016lx", regs[27]);
tty->print_cr("x28 = 0x%016lx", regs[28]);
tty->print_cr("x30 = 0x%016lx", regs[30]);
tty->print_cr("x31 = 0x%016lx", regs[31]);
BREAKPOINT;
}
ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
} else {
ttyLocker ttyl;
::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
assert(false, "DEBUG MESSAGE: %s", msg);
}
}
void MacroAssembler::resolve_jobject(Register value, Register thread, Register tmp) {
Label done, not_weak;
beqz(value, done); // Use NULL as-is.
// Test for jweak tag.
andi(t0, value, JNIHandles::weak_tag_mask);
beqz(t0, not_weak);
// Resolve jweak.
access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, value,
Address(value, -JNIHandles::weak_tag_value), tmp, thread);
verify_oop(value);
j(done);
bind(not_weak);
// Resolve (untagged) jobject.
access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
verify_oop(value);
bind(done);
}
void MacroAssembler::stop(const char* msg) {
address ip = pc();
pusha();
if(msg != NULL && ip != NULL) {
li(c_rarg0, (uintptr_t)(address)msg);
li(c_rarg1, (uintptr_t)(address)ip);
} else {
ShouldNotReachHere();
}
mv(c_rarg2, sp);
mv(c_rarg3, CAST_FROM_FN_PTR(address, MacroAssembler::debug64));
jalr(c_rarg3);
ebreak();
}
void MacroAssembler::unimplemented(const char* what) {
const char* buf = NULL;
{
ResourceMark rm;
stringStream ss;
ss.print("unimplemented: %s", what);
buf = code_string(ss.as_string());
}
stop(buf);
}
void MacroAssembler::emit_static_call_stub() {
// CompiledDirectStaticCall::set_to_interpreted knows the
// exact layout of this stub.
ifence();
mov_metadata(xmethod, (Metadata*)NULL);
// Jump to the entry point of the i2c stub.
int32_t offset = 0;
movptr_with_offset(t0, 0, offset);
jalr(x0, t0, offset);
}
void MacroAssembler::call_VM_leaf_base(address entry_point,
int number_of_arguments,
Label *retaddr) {
call_native_base(entry_point, retaddr);
}
void MacroAssembler::call_native(address entry_point, Register arg_0) {
pass_arg0(this, arg_0);
call_native_base(entry_point);
}
void MacroAssembler::call_native_base(address entry_point, Label *retaddr) {
Label E, L;
int32_t offset = 0;
push_reg(0x80000040, sp); // push << t0 & xmethod >> to sp
movptr_with_offset(t0, entry_point, offset);
jalr(x1, t0, offset);
if (retaddr != NULL) {
bind(*retaddr);
}
pop_reg(0x80000040, sp); // pop << t0 & xmethod >> from sp
}
void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
call_VM_leaf_base(entry_point, number_of_arguments);
}
void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
pass_arg0(this, arg_0);
call_VM_leaf_base(entry_point, 1);
}
void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
pass_arg0(this, arg_0);
pass_arg1(this, arg_1);
call_VM_leaf_base(entry_point, 2);
}
void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
Register arg_1, Register arg_2) {
pass_arg0(this, arg_0);
pass_arg1(this, arg_1);
pass_arg2(this, arg_2);
call_VM_leaf_base(entry_point, 3);
}
void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
pass_arg0(this, arg_0);
MacroAssembler::call_VM_leaf_base(entry_point, 1);
}
void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
assert(arg_0 != c_rarg1, "smashed arg");
pass_arg1(this, arg_1);
pass_arg0(this, arg_0);
MacroAssembler::call_VM_leaf_base(entry_point, 2);
}
void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
assert(arg_0 != c_rarg2, "smashed arg");
assert(arg_1 != c_rarg2, "smashed arg");
pass_arg2(this, arg_2);
assert(arg_0 != c_rarg1, "smashed arg");
pass_arg1(this, arg_1);
pass_arg0(this, arg_0);
MacroAssembler::call_VM_leaf_base(entry_point, 3);
}
void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
assert(arg_0 != c_rarg3, "smashed arg");
assert(arg_1 != c_rarg3, "smashed arg");
assert(arg_2 != c_rarg3, "smashed arg");
pass_arg3(this, arg_3);
assert(arg_0 != c_rarg2, "smashed arg");
assert(arg_1 != c_rarg2, "smashed arg");
pass_arg2(this, arg_2);
assert(arg_0 != c_rarg1, "smashed arg");
pass_arg1(this, arg_1);
pass_arg0(this, arg_0);
MacroAssembler::call_VM_leaf_base(entry_point, 4);
}
void MacroAssembler::nop() {
addi(x0, x0, 0);
}
void MacroAssembler::mv(Register Rd, Register Rs) {
if (Rd != Rs) {
addi(Rd, Rs, 0);
}
}
void MacroAssembler::notr(Register Rd, Register Rs) {
xori(Rd, Rs, -1);
}
void MacroAssembler::neg(Register Rd, Register Rs) {
sub(Rd, x0, Rs);
}
void MacroAssembler::negw(Register Rd, Register Rs) {
subw(Rd, x0, Rs);
}
void MacroAssembler::sext_w(Register Rd, Register Rs) {
addiw(Rd, Rs, 0);
}
void MacroAssembler::seqz(Register Rd, Register Rs) {
sltiu(Rd, Rs, 1);
}
void MacroAssembler::snez(Register Rd, Register Rs) {
sltu(Rd, x0, Rs);
}
void MacroAssembler::sltz(Register Rd, Register Rs) {
slt(Rd, Rs, x0);
}
void MacroAssembler::sgtz(Register Rd, Register Rs) {
slt(Rd, x0, Rs);
}
void MacroAssembler::fmv_s(FloatRegister Rd, FloatRegister Rs) {
if (Rd != Rs) {
fsgnj_s(Rd, Rs, Rs);
}
}
void MacroAssembler::fabs_s(FloatRegister Rd, FloatRegister Rs) {
fsgnjx_s(Rd, Rs, Rs);
}
void MacroAssembler::fneg_s(FloatRegister Rd, FloatRegister Rs) {
fsgnjn_s(Rd, Rs, Rs);
}
void MacroAssembler::fmv_d(FloatRegister Rd, FloatRegister Rs) {
if (Rd != Rs) {
fsgnj_d(Rd, Rs, Rs);
}
}
void MacroAssembler::fabs_d(FloatRegister Rd, FloatRegister Rs) {
fsgnjx_d(Rd, Rs, Rs);
}
void MacroAssembler::fneg_d(FloatRegister Rd, FloatRegister Rs) {
fsgnjn_d(Rd, Rs, Rs);
}
void MacroAssembler::vmnot_m(VectorRegister vd, VectorRegister vs) {
vmnand_mm(vd, vs, vs);
}
void MacroAssembler::vncvt_x_x_w(VectorRegister vd, VectorRegister vs, VectorMask vm) {
vnsrl_wx(vd, vs, x0, vm);
}
void MacroAssembler::vfneg_v(VectorRegister vd, VectorRegister vs) {
vfsgnjn_vv(vd, vs, vs);
}
void MacroAssembler::la(Register Rd, const address &dest) {
int64_t offset = dest - pc();
if (is_offset_in_range(offset, 32)) {
auipc(Rd, (int32_t)offset + 0x800); //0x800, Note:the 11th sign bit
addi(Rd, Rd, ((int64_t)offset << 52) >> 52);
} else {
movptr(Rd, dest);
}
}
void MacroAssembler::la(Register Rd, const Address &adr) {
InstructionMark im(this);
code_section()->relocate(inst_mark(), adr.rspec());
relocInfo::relocType rtype = adr.rspec().reloc()->type();
switch(adr.getMode()) {
case Address::literal: {
if (rtype == relocInfo::none) {
li(Rd, (intptr_t)(adr.target()));
} else {
movptr(Rd, adr.target());
}
break;
}
case Address::base_plus_offset:{
int32_t offset = 0;
baseOffset(Rd, adr, offset);
addi(Rd, Rd, offset);
break;
}
default:
ShouldNotReachHere();
}
}
void MacroAssembler::la(Register Rd, Label &label) {
la(Rd, target(label));
}
#define INSN(NAME) \
void MacroAssembler::NAME##z(Register Rs, const address &dest) { \
NAME(Rs, zr, dest); \
} \
void MacroAssembler::NAME##z(Register Rs, Label &l, bool is_far) { \
NAME(Rs, zr, l, is_far); \
} \
INSN(beq);
INSN(bne);
INSN(blt);
INSN(ble);
INSN(bge);
INSN(bgt);
#undef INSN
// Float compare branch instructions
#define INSN(NAME, FLOATCMP, BRANCH) \
void MacroAssembler::float_##NAME(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far, bool is_unordered) { \
FLOATCMP##_s(t0, Rs1, Rs2); \
BRANCH(t0, l, is_far); \
} \
void MacroAssembler::double_##NAME(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far, bool is_unordered) { \
FLOATCMP##_d(t0, Rs1, Rs2); \
BRANCH(t0, l, is_far); \
}
INSN(beq, feq, bnez);
INSN(bne, feq, beqz);
#undef INSN
#define INSN(NAME, FLOATCMP1, FLOATCMP2) \
void MacroAssembler::float_##NAME(FloatRegister Rs1, FloatRegister Rs2, Label &l, \
bool is_far, bool is_unordered) { \
if(is_unordered) { \
/* jump if either source is NaN or condition is expected */ \
FLOATCMP2##_s(t0, Rs2, Rs1); \
beqz(t0, l, is_far); \
} else { \
/* jump if no NaN in source and condition is expected */ \
FLOATCMP1##_s(t0, Rs1, Rs2); \
bnez(t0, l, is_far); \
} \
} \
void MacroAssembler::double_##NAME(FloatRegister Rs1, FloatRegister Rs2, Label &l, \
bool is_far, bool is_unordered) { \
if(is_unordered) { \
/* jump if either source is NaN or condition is expected */ \
FLOATCMP2##_d(t0, Rs2, Rs1); \
beqz(t0, l, is_far); \
} else { \
/* jump if no NaN in source and condition is expected */ \
FLOATCMP1##_d(t0, Rs1, Rs2); \
bnez(t0, l, is_far); \
} \
}
INSN(ble, fle, flt);
INSN(blt, flt, fle);
#undef INSN
#define INSN(NAME, CMP) \
void MacroAssembler::float_##NAME(FloatRegister Rs1, FloatRegister Rs2, Label &l, \
bool is_far, bool is_unordered) { \
float_##CMP(Rs2, Rs1, l, is_far, is_unordered); \
} \
void MacroAssembler::double_##NAME(FloatRegister Rs1, FloatRegister Rs2, Label &l, \
bool is_far, bool is_unordered) { \
double_##CMP(Rs2, Rs1, l, is_far, is_unordered); \
}
INSN(bgt, blt);
INSN(bge, ble);
#undef INSN
#define INSN(NAME, CSR) \
void MacroAssembler::NAME(Register Rd) { \
csrr(Rd, CSR); \
}
INSN(rdinstret, CSR_INSTERT);
INSN(rdcycle, CSR_CYCLE);
INSN(rdtime, CSR_TIME);
INSN(frcsr, CSR_FCSR);
INSN(frrm, CSR_FRM);
INSN(frflags, CSR_FFLAGS);
#undef INSN
void MacroAssembler::csrr(Register Rd, unsigned csr) {
csrrs(Rd, csr, x0);
}
#define INSN(NAME, OPFUN) \
void MacroAssembler::NAME(unsigned csr, Register Rs) { \
OPFUN(x0, csr, Rs); \
}
INSN(csrw, csrrw);
INSN(csrs, csrrs);
INSN(csrc, csrrc);
#undef INSN
#define INSN(NAME, OPFUN) \
void MacroAssembler::NAME(unsigned csr, unsigned imm) { \
OPFUN(x0, csr, imm); \
}
INSN(csrwi, csrrwi);
INSN(csrsi, csrrsi);
INSN(csrci, csrrci);
#undef INSN
#define INSN(NAME, CSR) \
void MacroAssembler::NAME(Register Rd, Register Rs) { \
csrrw(Rd, CSR, Rs); \
}
INSN(fscsr, CSR_FCSR);
INSN(fsrm, CSR_FRM);
INSN(fsflags, CSR_FFLAGS);
#undef INSN
#define INSN(NAME) \
void MacroAssembler::NAME(Register Rs) { \
NAME(x0, Rs); \
}
INSN(fscsr);
INSN(fsrm);
INSN(fsflags);
#undef INSN
void MacroAssembler::fsrmi(Register Rd, unsigned imm) {
guarantee(imm < 5, "Rounding Mode is invalid in Rounding Mode register");
csrrwi(Rd, CSR_FRM, imm);
}
void MacroAssembler::fsflagsi(Register Rd, unsigned imm) {
csrrwi(Rd, CSR_FFLAGS, imm);
}
#define INSN(NAME) \
void MacroAssembler::NAME(unsigned imm) { \
NAME(x0, imm); \
}
INSN(fsrmi);
INSN(fsflagsi);
#undef INSN
void MacroAssembler::push_reg(Register Rs)
{
addi(esp, esp, 0 - wordSize);
sd(Rs, Address(esp, 0));
}
void MacroAssembler::pop_reg(Register Rd)
{
ld(Rd, esp, 0);
addi(esp, esp, wordSize);
}
int MacroAssembler::bitset_to_regs(unsigned int bitset, unsigned char* regs) {
DEBUG_ONLY(int words_pushed = 0;)
int count = 0;
// Sp is x2, and zr is x0, which should not be pushed.
// If the number of registers is odd, zr is used for stack alignment.Otherwise, it will be ignored.
bitset &= ~ (1U << 2);
bitset |= 0x1;
// Scan bitset to accumulate register pairs
for (int reg = 31; reg >= 0; reg --) {
if ((1U << 31) & bitset) {
regs[count++] = reg;
}
bitset <<= 1;
}
count &= ~1; // Only push an even number of regs
return count;
}
// Push lots of registers in the bit set supplied. Don't push sp.
// Return the number of words pushed
int MacroAssembler::push_reg(unsigned int bitset, Register stack) {
DEBUG_ONLY(int words_pushed = 0;)
unsigned char regs[32];
int count = bitset_to_regs(bitset, regs);
if (count) {
addi(stack, stack, - count * wordSize);
}
for (int i = count - 1; i >= 0; i--) {
sd(as_Register(regs[i]), Address(stack, (count -1 - i) * wordSize));
DEBUG_ONLY(words_pushed ++;)
}
assert(words_pushed == count, "oops, pushed != count");
return count;
}