Skip to content
/ DLD-final-project Public

This is the final project for course Digital logic design which is a combination of encryptor, state machines and implementation on Atlys.

0 stars 0 forks Branches Tags Activity
Star
Notifications You must be signed in to change notification settings

SiluPanda/DLD-final-project

BranchesTags

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

2 Commits

README.md

README.md

 
 

bit_converter.vhd

bit_converter.vhd

 
 

clockconverter.vhd

clockconverter.vhd

 
 

encryptor.vhd

encryptor.vhd

 
 

main_module.vhd

main_module.vhd

 
 

test1.vhd

test1.vhd

 
 

test2.vhd

test2.vhd

 
 

test_clock.vhd

test_clock.vhd

 
 

test_clock_converter.vhd

test_clock_converter.vhd

 
 

test_encryptor.vhd

test_encryptor.vhd

 
 

test_main.vhd

test_main.vhd

 
 

test_top.vhd

test_top.vhd

 
 

top_module.bit

top_module.bit

 
 

top_module.vhd

top_module.vhd

 
 

Repository files navigation

DLD-final-project

About

This is the final project for course Digital logic design which is a combination of encryptor, state machines and implementation on Atlys.

Topics

vhdl digital-logic-design

Resources

Readme
Activity

Stars

0 stars

Watchers

2 watching

Forks

0 forks
Report repository

Releases

No releases published

Packages

No packages published

Languages