Add ethernet udp tx/rx module

[jjyy-Huang]

Context, Motivation & Description

The udp project is here.

• The goal of this PR is to create a UDP/IP Tx/Rx module with SpinalHDL for Xilinx 100GbE Ethernet-Subsystem (MRMAC/CMAC).

• the module support following features:

  • UDP Tx/Rx without checksum
  • IP Tx/Rx
  • Ethernet Frame Layer2 (pre-add MAC adn EtherType)
  • 256b data width
  • Fully pipeline

Impact on code generation

Zero

Checklist

• Unit tests were added
• API changes are or will be documented:
  • using Scaladoc comments: /** */?
  • on RTD?
  • thanks to a new tracking issue on RTD?

TODO

• Redesign Rx module control logic
• Add ARP request module
• Add ICMP module
• I/O data support 384b/512b
• Use cocotb for verification

[Dolu1990]

rotate operation could be added to the Bits data type directly :)
Maybe in a more general form ?
data: Bits, bias: UInt, sliceWidth : BitCount ?

[jjyy-Huang]

Ummm...

Actually, there is rotateLeft() in BitVector,

def rotateLeft(that: UInt): T = {
    ...
}

I wonder if it would be better to use switch instead of bits shift one by one.

[Dolu1990]

I wonder if it would be better to use switch instead of bits shift one by one.

Hmm, the main challenge is to ensure the synthesis tool can infer a proper barrel shifter using log2up(width) stages, that's why it is done in shifts sequence.

I would say the main limitation of the current implementation is that there is now parameter to specify how many bits to rotate per unit.

[Dolu1990]

Hi ^^

So, i think for the doc, as it is a specific thing with quite a few abstraction, it would need to have some on the RTD

[jjyy-Huang]

Hi ^^

So, i think for the doc, as it is a specific thing with quite a few abstraction, it would need to have some on the RTD

Sorry for the late reply.

The doc will be added with more details of implementation in the next commit

[jjyy-Huang]

Hi ^^
So, i think for the doc, as it is a specific thing with quite a few abstraction, it would need to have some on the RTD

I'm sorry for waiting on this document for a long time.

The following link is the doc about this module design.

https://github.com/jjyy-Huang/SpinalHDL-ethernet/blob/udp/README.md

[Dolu1990]

Thanks :)
I will check it, just have quite a high stack of work at the moment

[Dolu1990]

Hi,

Sorry for the delay, i'm running with toooo many thing on hands XD

So, in some ways, i a bit scared integrating too much things in the spinal.lib, especialy fresh things.
What's about keeping https://github.com/jjyy-Huang/SpinalHDL-ethernet and adding a reference to it in :
https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Introduction/Projects%20using%20SpinalHDL.html#repositories

This maybe more scalable in terms of project management ? That way, poeple have the freedom to do things without having to worry to much about SpinalHDL upstream, while still having some visibility via the documentation pointers.
On my side It solve the maintenance issue i currently have with so many things now being in the Spinal lib :)

One thing, is that in your repo, you can extends the already existing spinal.lib package, for instance :
https://github.com/SpinalHDL/NaxRiscv/tree/main/src/main/scala/spinal/lib/bus/cmb

That way, it provide a forward way for easy integration when things are very stable / extended :)

Let's me know if that sounds good for you ?

[jjyy-Huang]

Hi,

Sorry for the late reply, I changed my email and can't receive news from GitHub.

I appreciate your suggestion. I will integrate it into my work process and continue to make improvements as I move forward.

Thanks again for your input, and please let me know if you have any further suggestions or feedback.