Verilog generated when using synchronous resets is not understood by SymbiYosys - remove "assert() else begin end"-block generation for now

[janschiefer]

See issue #1314

Remove "assert() else begin end"-block generation for now.

[Readon]

This "else begin" strings is used for assert otherthan formal verification.
There two use case of assert now.

1. assert in simulation.
2. assert in formal verification.