[regif] feature upgrade refactoring #1409

jijingg · 2024-05-08T08:19:20Z

This update is based on practical feedback from real projects, and the changes are quite significant. In addition to adding some important features, many factory functions have been added, and common register file reuse scenarios have been solved. suggestions from software usage have been adopted to optimize..h file.
Despite such significant refactoring modifications, backward compatibility should be maintained in principle, and it will not affect old code.

Checklist

Unit tests were added done
API changes are or will be documented: TODO

1. remove BusIfVistor mode instead directly access for simplify 2. add RegInstGrp layer 3. refactor BusIf Document, but keep old api 4. add usefull Factory method(Interrupt, SCR etc..) 5. localbus

andreasWallner · 2024-05-10T01:10:41Z

I know this is still a draft, but a few thoughts:

what is lbus/mbus - I couldn't find any spec; is this some company internal bus that you are using? Should it be in spinal.lib?
removing the visitor breaks current users of the library - we should not do that
in general many of these changes seem to break existing users (ones with custom output generators, by moving classes, etc.)
this seems to only support FIFO writes, not reads, when adding FIFO access it should allow for both; the current design can't be easily extended for read

possibly more to follow, have to look at it some more

jijingg · 2024-05-10T05:04:12Z

removing the visitor breaks current users of the library - we should not do that
@andreasWallner

Although there isn't a standard, it's basically an unwritten but widely used bus approach, which may have some naming differences, but the logic is the same. Since every team will use it, I suggest providing an implementation in Spinal to avoid everyone reinventing the wheel. （Of course, we can discuss naming further. I also don't think "lbus" or "mbus" is a good idea. That includes their signal names as well.）
Secondly, maintaining backward compatibility as the first priority for open-source projects, which is not violated here. The original method can still be used, and API conversion can be used to accomplish this seamlessly, without impacting users.
Same as 2, it is insensitive to existing users and cannot cause crashes of existing code
Regarding the logic behind bus.readata, there is still work to be done, which is why it's currently in draft status. However, the FIFO reading you mentioned is indeed a good idea, even though I haven't encountered such a scenario yet. I believe FIFO reading could have potential use, and I will consider implementing it.

…s_rdata/bus_rderr compare reg_rdata/bus_rderr

Readon · 2024-05-23T16:04:14Z

FIFO is really a special case, when writing to a FIFO it should be tested if it is writable first. So the data and status of FIFO might need to be added separately, which is a little bit different from the existing regif interface.

On the other hand, before read, the host should check if there is data in the FIFO.

jijingg · 2024-05-24T02:11:18Z

FIFO is really a special case, when writing to a FIFO it should be tested if it is writable first. So the data and status of FIFO might need to be added separately, which is a little bit different from the existing regif interface.

yes the FIFO port cannot strictly guarantee no data loss,
if the user scenario is sensitive to operation loss, there are two ways for users to solve it

Calculate the maximum throughput per unit time and choose the issuance operation to ensure that the FIFO does not overflow per unit time.
The status information of FIFO can be hung on registers for software to read, and the software's issuance operation needs to refer to the FIFO's status as handshake

On the other hand, before read, the host should check if there is data in the FIFO.

right, If it is an effective read operation, the software does need to first determine whether there is data. to be honest,
FIFO reading may have use-case , but I haven't encountered them yet. I'm still on the fence about whether it's necessary to implement the read functionality of a FIFO.
So the functionality of reading from a FIFO seems to have too many limitations and is somewhat redundant. It has to worry about HW-write overflows and also consider the possibility of SW-read miss

Readon · 2024-05-24T03:46:46Z

n the fence about whether it's necessary to implement the read functionality of a FIFO.
So the functionality of reading from a FIFO seems to have too many limitations and is somewhat redundant. It has to worry about HW-write overflows and also consider the possibility of SW-read miss

Ahhh，We use a lot while designing an instrument.
On common case is that a streamlized SPI or UART controller might want to use FIFO to cache the data to be transmitted.

jijingg · 2024-05-24T06:55:19Z

Ahhh，We use a lot while designing an instrument.
On common case is that a streamlized SPI or UART controller might want to use FIFO to cache the data to be transmitted.

i got it, so now If we sensitive to packet loss, we may need some peripheral auxiliary circuits or handshake to ensure data. Since that's the case, it's necessary to add this feature , but the specific data caching correctness needs to be guaranteed by the user themselves, is it OK?

Readon · 2024-05-24T09:54:35Z

Ahhh，We use a lot while designing an instrument.
On common case is that a streamlized SPI or UART controller might want to use FIFO to cache the data to be transmitted.

i got it, so now If we sensitive to packet loss, we may need some peripheral auxiliary circuits or handshake to ensure data. Since that's the case, it's necessary to add this feature , but the specific data caching correctness needs to be guaranteed by the user themselves, is it OK?

Yes, I think they should guarantee the correctness by software. We can only provide the option.

…e add

lib/src/main/scala/spinal/lib/bus/regif/AccessType.scala

jijingg · 2024-05-29T03:17:20Z

At present, I think it ready for merge The update of the document is still in progress it will completed within this week. do you guys have any comments @andreasWallner @Readon @mrberman87 @Dolu1990

Dolu1990 · 2024-05-29T08:08:23Z

For me, you can merge you feel it.

andreasWallner · 2024-05-29T21:51:35Z

@jijingg
comment are coming up, just takes a while to get through 66 files ...

jijingg · 2024-05-31T06:53:37Z

@jijingg comment are coming up, just takes a while to get through 66 files ...

hi, Let me merge first. If there are any issue need improvement, we will continue to initiate the PR

andreasWallner

Sorry for the long time, but since this is nearly a rewrite I had to copy code to an external editor to have useful diffs - a PR of this size is not reviewable.

andreasWallner · 2024-06-01T00:11:20Z

lib/src/main/scala/spinal/lib/bus/localbus/MemBus.scala

+
+case class MemBusConfig(aw: Int, dw: Int)
+
+case class MemBus(c: MemBusConfig) extends Interface with IMasterSlave {


MemBus is a near duplicate of the BRAM bus (slight difference in WE, which would actually be a reasonable future feature request to support) and the AsyncMemoryBus (which can stall) - I think we should extend one of those with a parameter instead of adding yet another new Bus that is not reasonably different.

andreasWallner · 2024-06-01T00:14:01Z

lib/src/main/scala/spinal/lib/bus/localbus/MinBus.scala

+  val sw  = dw >> 3
+}
+
+case class MinBus(c: MinBusConfig) extends Interface with IMasterSlave {


I hope you'll describe the meaning (and timing) of these signals somewhere - its really hard to know what some of them are supposed to be (e.g. the difference between rvld and rdy, what prot does).
Apart from that this is a slight extension of AsyncMemoryBus and would maybe be better as some parameters there?

andreasWallner · 2024-06-01T00:19:02Z

lib/src/main/scala/spinal/lib/bus/localbus/sim/MemVIP.scala

+import spinal.core._
+import spinal.core.sim._
+class MemVIP{
+  private val mem = scala.collection.mutable.HashMap[Long, BigInt]()


it would make sense if this would reuse SparseMemory

andreasWallner · 2024-06-01T00:19:41Z

lib/src/main/scala/spinal/lib/bus/localbus/sim/MemBusDriver.scala

+import spinal.core._
+import spinal.core.sim._
+
+case class MemBusDriver(bus : MemBus, clockdomain : ClockDomain) {


All other bus drivers initialize the bus when constructed - this one should do this as well.

andreasWallner · 2024-06-01T00:20:26Z

lib/src/main/scala/spinal/lib/bus/localbus/sim/MemBusDriver.scala

+    bus.ce #= true
+    bus.wr #= false
+    bus.addr #= address
+    bus.wdat #= 1234 //.randomize()


this should use randomize like in the comment?

andreasWallner · 2024-06-01T00:23:45Z

lib/src/main/scala/spinal/lib/bus/localbus/sim/MemVIP.scala

+    }
+  }
+
+  def hang(bus: MinBus, delay: Int = 10)(cd: ClockDomain): MemVIP = {


what does hang mean - the only thing that comes to my mind is that it gets stuck which doesn't appear to be the case - looking at this and the one above shouldn't these just be apply methods?

andreasWallner · 2024-06-01T00:27:30Z

lib/src/main/scala/spinal/lib/bus/regif/Block/FifoInst.scala

+  val hitDoRead: Bool
+  val hitDoWrite : Bool
+
+  val bus = Stream(Bits(bi.busDataWidth bit))


Having a Stream here creates an issue for WrFifoInst where it's lying to the user: Stream implies that backpressure can be applied, which is not the case there. So for write this should be a Flow instead. This would correctly indicate that it can't stall the bus, and the user can use toStream(overflow: Bool) to convert to a stream with an overflow check (or use toStream if they don't care).

In short: this should be moved to WrFifoInst (as a Flow) and RdFifoInst (kept as a Stream)

andreasWallner · 2024-06-01T00:38:40Z

lib/src/main/scala/spinal/lib/bus/regif/BusIf.scala

+    res
+  }
+
+  def creatRAM(name: String, addr: BigInt, size: BigInt, doc: String, grp: GrpTag = null) = {


why leave out a single character in create? typing this I always have to remind myself to make this mistake.
I see that creatReg existed for the old API - we should deprecate that one and fix the spelling.

andreasWallner · 2024-06-01T00:50:39Z

lib/src/main/scala/spinal/lib/bus/regif/BusIfAdapter/AhbLite3BusInterface.scala

  val wstrb: Bits = withStrb generate (Bits(strbWidth bit))
  val wmask: Bits = withStrb generate (Bits(busDataWidth bit))
  val wmaskn: Bits = withStrb generate (Bits(busDataWidth bit))
  initStrbMasks()
  override def getModuleName = moduleName.name

-  val readError = Bool()


these were one of the changes that I was referring to when I said that the PR can't be backwards compatible: since you are changing the name of a public field every code referring to it is broken after this

andreasWallner · 2024-06-01T00:52:42Z

lib/src/main/scala/spinal/lib/bus/regif/BusIfBase.scala


-  val readData: Bits


This was one of the changes I was referring to when I said this PR is not backwards compatible. This change breaks ever custom bus implementation a user of the library has

jijingg added 2 commits May 8, 2024 16:11

regif refactor

9dc67a7

1. remove BusIfVistor mode instead directly access for simplify 2. add RegInstGrp layer 3. refactor BusIf Document, but keep old api 4. add usefull Factory method(Interrupt, SCR etc..) 5. localbus

[regif] remove deadcode

501d913

jijingg marked this pull request as draft May 8, 2024 17:54

[regif] type issue fix

e02d1dd

jijingg added 17 commits May 15, 2024 11:00

Merge branch 'dev' of https://github.com/SpinalHDL/SpinalHDL into reg

f767448

[regif] support reuse part lead chead define with function

0901ea2

[regif] deadcode fix

e1eca59

[regif] regif reusePart example

0877f33

[regif] readData logic refactor support ram.rdata

df01251

Merge branch 'reg' of github.com:jijingg/SpinalHDL into reg

3b50577

[regif] fix wishbon/bmb regout issue. rename readData/readError to bu…

7e34d22

…s_rdata/bus_rderr compare reg_rdata/bus_rderr

Merge branch 'reg' of github.com:jijingg/SpinalHDL into reg

da9f986

[regif] CHead issue fix

4dc4557

[regif] add 'cg_en' trait, DocJson fix

6f9eace

[regif] MemBus/MinBus rename ..

ffea8c9

[regif] remove ApbBusInterface selID

5f0df3a

[regif] fix MemBus connect

fd74a68

[regif] ralf memory fix

4408596

[regif] ralf fix

eec2c7e

[regif] add W1CHS/W1SHS type

438a823

[regif] busif.genBaseDocs

59a4184

[regif] partTag rename to BlockTag

54ddac6

[regif] Html support ReUseBlock Tree

7998700

jijingg added 3 commits May 27, 2024 11:16

[regif] BusInterface match

99a09df

[regif] 1.CHeader/SVHeader optimize 2.MemBus/MinBus Driver and simcas…

0a3c5e1

…e add

[regif] support RdFifo/WrFifo feature

386986f

jijingg marked this pull request as ready for review May 27, 2024 15:50

jijingg added 2 commits May 28, 2024 10:04

Merge branch 'dev' of https://github.com/SpinalHDL/SpinalHDL into reg

9f0316f

[regif] RAM/RdFifo/WrFifo simluation case added

d3a1337

mrberman87 reviewed May 28, 2024

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lib/src/main/scala/spinal/lib/bus/regif/AccessType.scala Show resolved Hide resolved

jijingg added 2 commits May 29, 2024 09:39

[regif] fix typo

edc1505

[regif] fix simluation issue

15c0a80

jijingg added 2 commits May 29, 2024 20:46

[regif] MinBus strb width always on

305278a

[regif] add NS(NonSec bit) trait on BusIf for security access use

29ca293

jijingg added 3 commits May 31, 2024 10:19

[regif] Interrupt Factory not only support Bool also multi Bits

b76c6cb

[regif] little fix

d8aeaf4

[regif] Intr offset issue fix, maxSize recorrected

fbc9cbb

jijingg merged commit 9f74204 into SpinalHDL:dev May 31, 2024
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andreasWallner reviewed Jun 1, 2024

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[regif] feature upgrade refactoring #1409

[regif] feature upgrade refactoring #1409

jijingg commented May 8, 2024 •

edited

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Readon commented May 23, 2024

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edited

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		case class MemBusConfig(aw: Int, dw: Int)

		case class MemBus(c: MemBusConfig) extends Interface with IMasterSlave {

[regif] feature upgrade refactoring #1409

[regif] feature upgrade refactoring #1409

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jijingg commented May 8, 2024 • edited

Checklist

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Readon commented May 23, 2024

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jijingg commented May 8, 2024 •

edited

jijingg commented May 24, 2024 •

edited