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148 Open 792 Closed
148 Open 792 Closed
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Issues list

Power in metrics.csv doesn't match with power in multi_corner_sta.power
#2125 opened May 23, 2024 by Lukemagik
Yosys ABC Tool crashes with exit code 139
#2124 opened May 22, 2024 by Fabbboy
Error: multi_corner.tcl line 43
#2123 opened May 20, 2024 by fazliemre
Make test and make openlane fail bug Something isn't working documentation Improvements or additions to documentation
#2122 opened May 12, 2024 by ssooffiiaannee
10
Generating the PDN fails at the "Hierarchical chip design (with macros)" tutorial
#2121 opened May 7, 2024 by kietuan
Clock Network Delay is 0.0 in timing reports after CTS
#2120 opened Apr 26, 2024 by Jaswanth-Pappula
2
Enable rtl_macro_placer feature enhancement New feature or request OpenLane 2 Scheduled for next gen OpenLane
#2117 opened Apr 12, 2024 by vijayank88
Error in step-17 Running Detailed Routing
#2112 opened Apr 2, 2024 by Sanchit-Gupta10
7
ldpcEncDec Step 18 18-resizer_design.log failed
#2104 opened Mar 21, 2024 by manish03
7
No via inserted -> Unconnected PDN node OpenROAD An issue with an OpenROAD component
#2102 opened Mar 11, 2024 by scorbetta
3
issues in using the floorplan core utilization command question The user needs help waiting on op Information has been requested from the Issue Author
#2101 opened Mar 11, 2024 by Ashutosh-3107
4
Max fanout violation
#2097 opened Feb 29, 2024 by MuhammadWamiq003
unable to view the floorplan def files in klayout of oprn lane bug Something isn't working Klayout waiting on op Information has been requested from the Issue Author workaround A workaround exists for this issue
#2095 opened Feb 26, 2024 by Ashutosh-3107
21
Unbalanced buffer insertion on high fanout designs question The user needs help
#2090 opened Feb 6, 2024 by Dolu1990
3
flow succeeds even if clock signal wire is unconnected / doesn't exist Yosys This issue is related to yosys
#2083 opened Jan 10, 2024 by mattvenn
4
Getting -from and -to are no longer supported bug Something isn't working documentation Improvements or additions to documentation
#2081 opened Jan 2, 2024 by ShankarSNP
2
ERROR]: Synthesis failed. Signal not matching port size. Search for 'Resizing cell port' waiting on op Information has been requested from the Issue Author
#2078 opened Dec 28, 2023 by alishan1213
1
Command 'make test' not working after installing OpenLane bug Something isn't working
#2064 opened Dec 11, 2023 by srichandrasrii
4
[ERROR STA-0026] unterminated string constant bug Something isn't working OpenROAD An issue with an OpenROAD component
#2063 opened Dec 10, 2023 by thesourcerer8
2
Add a max capacitance variable enhancement New feature or request
#2057 opened Nov 21, 2023 by donn
PDN pitch error question The user needs help waiting on op Information has been requested from the Issue Author
#2053 opened Nov 21, 2023 by kirubakaran-g
1
Documentation Cleanup enhancement New feature or request
#2043 opened Nov 12, 2023 by donn
CURRENT_ODB is unset when follow Designing a chip with an OpenRAM (sky130) bug Something isn't working documentation Improvements or additions to documentation
#2032 opened Oct 30, 2023 by PeterBorisenko
1
Using Openlane for symmetric routing
#2031 opened Oct 30, 2023 by jchin2
1
Metal Spacing violation between interconnect and macro (sky130) bug Something isn't working OpenROAD An issue with an OpenROAD component
#2030 opened Oct 30, 2023 by Dolu1990
9
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