EEP206-Verilog

This repository contains IIT Ropar's EEP206 - Digital Circuits Laboratory's Verilog Codes for various circuits.

Instructions

For running these you can use the Icarus Verilog compiler (iverilog), After installing compile:

iverilog -o and_out and_test.v and.v

and run usingIcarus Verilog runtime engine(vvp)

vvp and_out

Structure

• Experiment 2: (Basic Gates) and, or, not, xor, xnor
• Experiment 3: Full adder, Full subtractor, Half Adder and Half Subtractor
• Experiment 4: 4-bit ripple carry adder
• Experiment 5: 4-bit x 3-bit multiplier
• Experiment 6: BCD to binary, BCD to excess-3, binary to gray code conversions.