Mealy_2019_Free Range VHDL

As part of study program Systems Engineering with Embedded Systems https://www.usn.no/studier/studie-og-emneplaner/#/studyplan/MASEMBSYS_2018H

Name		Name	Last commit message	Last commit date
Latest commit History 20 Commits
4.1_Listing_4_1_LOGIC_GATES.vhd		4.1_Listing_4_1_LOGIC_GATES.vhd
4_3_Eg_1_NAND_3input.vhd		4_3_Eg_1_NAND_3input.vhd
4_3_Eg_2_simple_function.vhd		4_3_Eg_2_simple_function.vhd
4_3_Eg_4_4_to_1_MUX.vhd		4_3_Eg_4_4_to_1_MUX.vhd
4_3_Eg_4_4_to_1_MUX_CONDITIONAL.vhd		4_3_Eg_4_4_to_1_MUX_CONDITIONAL.vhd
4_5_Eg_7_decoder_circuit_SELECT.vhd		4_5_Eg_7_decoder_circuit_SELECT.vhd
4_5_Eg_8_simple_function_SELECT.vhd		4_5_Eg_8_simple_function_SELECT.vhd
4_Ex_1_a_CONCURRENT.vhd		4_Ex_1_a_CONCURRENT.vhd
4_Ex_1_b_CONCURRENT.vhd		4_Ex_1_b_CONCURRENT.vhd
4_Ex_1_c_CONCURRENT.vhd		4_Ex_1_c_CONCURRENT.vhd
4_Ex_1_d_CONCURRENT.vhd		4_Ex_1_d_CONCURRENT.vhd
4_Ex_1_e_CONCURRENT.vhd		4_Ex_1_e_CONCURRENT.vhd
4_Ex_1_f_CONCURRENT.vhd		4_Ex_1_f_CONCURRENT.vhd
4_Ex_2_a_CONDITONAL_SELECTED.vhd		4_Ex_2_a_CONDITONAL_SELECTED.vhd
4_Ex_2_b_CONDITONAL_SELECTED.vhd		4_Ex_2_b_CONDITONAL_SELECTED.vhd
4_Ex_2_c_CONDITONAL_SELECTED.vhd		4_Ex_2_c_CONDITONAL_SELECTED.vhd
4_Ex_2_d_CONDITONAL_SELECTED.vhd		4_Ex_2_d_CONDITONAL_SELECTED.vhd
4_Ex_3_8INPUT_AND_CONCURRENT CONDITIONAL AND SELECTED.vhd		4_Ex_3_8INPUT_AND_CONCURRENT CONDITIONAL AND SELECTED.vhd
4_Ex_4_8INPUT_MUX_ CONDITIONAL__SELECTED.vhd		4_Ex_4_8INPUT_MUX_ CONDITIONAL__SELECTED.vhd
4_Ex_5_8INPUT_MUX_ CONDITIONAL_SELECTED.vhd		4_Ex_5_8INPUT_MUX_ CONDITIONAL_SELECTED.vhd
4_Ex_6_3t8_DECODER CONDITIONAL_SELECTED_ACTIVE HIGH.vhd		4_Ex_6_3t8_DECODER CONDITIONAL_SELECTED_ACTIVE HIGH.vhd
4_Ex_7_3t8_DECODER CONDITIONAL_SELECTED_ACTIVE LOW.vhd		4_Ex_7_3t8_DECODER CONDITIONAL_SELECTED_ACTIVE LOW.vhd
5_Eg_10_3t8_MUX_IF PROCESS_statement.vhd		5_Eg_10_3t8_MUX_IF PROCESS_statement.vhd
5_Eg_11_8t1_MUX_PROCESS_with CE_IF PROCESS.vhd		5_Eg_11_8t1_MUX_PROCESS_with CE_IF PROCESS.vhd
5_Eg_12_SIMPLE FUNCTION as CASE statement.vhd		5_Eg_12_SIMPLE FUNCTION as CASE statement.vhd
5_Eg_13_S8t1_MUX as a CASE statement.vhd		5_Eg_13_S8t1_MUX as a CASE statement.vhd
5_Ex_1_a_SIMPLE FUNCTION as CASE and IF statement.vhd		5_Ex_1_a_SIMPLE FUNCTION as CASE and IF statement.vhd
5_Ex_1_b_SIMPLE FUNCTION as CASE and IF statement.vhd		5_Ex_1_b_SIMPLE FUNCTION as CASE and IF statement.vhd
5_Ex_2_SIMPLE FUNCTION as CASE and IF statement.vhd		5_Ex_2_SIMPLE FUNCTION as CASE and IF statement.vhd
5_Ex_3_SIMPLE FUNCTION as CONCURRENTand CONDITIONAL WHEN ELSE and SELECTED WITH SELECT.vhd		5_Ex_3_SIMPLE FUNCTION as CONCURRENTand CONDITIONAL WHEN ELSE and SELECTED WITH SELECT.vhd
5_Ex_4_8_input_AND_GATE_with PROCESS statement.vhd		5_Ex_4_8_input_AND_GATE_with PROCESS statement.vhd
5_Ex_5_8_input_OR_GATE_with PROCESS statement.vhd		5_Ex_5_8_input_OR_GATE_with PROCESS statement.vhd
5_Ex_6_8to1_MUX_PROCESS statements_IF THEN and CASE WHEN .vhd		5_Ex_6_8to1_MUX_PROCESS statements_IF THEN and CASE WHEN .vhd
5_Ex_7_3to8_DECODER_ACTIVE LOW_PROCESS statements_IF THEN and CASE WHEN.vhd		5_Ex_7_3to8_DECODER_ACTIVE LOW_PROCESS statements_IF THEN and CASE WHEN.vhd
5_Simple_FUNCTION_as IF_PROCESS_statement.vhd		5_Simple_FUNCTION_as IF_PROCESS_statement.vhd
5_USE OF_PROCESS_STATEMENT.vhd		5_USE OF_PROCESS_STATEMENT.vhd
7 Eg 14 Simple FLIP-FLOP.vhd		7 Eg 14 Simple FLIP-FLOP.vhd
7 Eg 15 FLIP-FLOP with ACTIVE LOW SYNCHRONOUS SET INPUT.vhd		7 Eg 15 FLIP-FLOP with ACTIVE LOW SYNCHRONOUS SET INPUT.vhd
7 Eg 16 FLIP-FLOP with ACTIVE HIGH ASYNCHRONOUS RESET INPUT.vhd		7 Eg 16 FLIP-FLOP with ACTIVE HIGH ASYNCHRONOUS RESET INPUT.vhd
7 Eg 17 FLIP FLOP with ACTIVE LOW ASYNCHRONOUS SET INPUT.vhd		7 Eg 17 FLIP FLOP with ACTIVE LOW ASYNCHRONOUS SET INPUT.vhd
7 Ex_1_SR FLIP FLOP ASYNCHRONOUS.vhd		7 Ex_1_SR FLIP FLOP ASYNCHRONOUS.vhd
7 Ex_2_SR FLIP FLOP ACTIVE LOW ASYNCHRONOUS.vhd		7 Ex_2_SR FLIP FLOP ACTIVE LOW ASYNCHRONOUS.vhd
7 Ex_3_SR FLIP FLOP ACTIVE LOW SYNCHRONOUS.vhd		7 Ex_3_SR FLIP FLOP ACTIVE LOW SYNCHRONOUS.vhd
7 Ex_4_SR FLIP FLOP ACTIVE LOW ASYNCHRONOUS.vhd		7 Ex_4_SR FLIP FLOP ACTIVE LOW ASYNCHRONOUS.vhd
7 Ex_5_SR FLIP FLOP ACTIVE LOW ASYNCHRONOUS_need help.vhd		7 Ex_5_SR FLIP FLOP ACTIVE LOW ASYNCHRONOUS_need help.vhd
7 Ex_6_T FLIP FLOP ACTIVE LOW ASYNCHRONOUS.vhd		7 Ex_6_T FLIP FLOP ACTIVE LOW ASYNCHRONOUS.vhd
8_Eg_18_BASIC_FSM_.vhd		8_Eg_18_BASIC_FSM_.vhd
8_Eg_18_BASIC_FSM_STATE variable as OUTPUT.vhd		8_Eg_18_BASIC_FSM_STATE variable as OUTPUT.vhd
8_Eg_19_FSM_w_STATE variable as OUTPUT.vhd		8_Eg_19_FSM_w_STATE variable as OUTPUT.vhd
9 Alternative architecture for 3 bit adder.vhd		9 Alternative architecture for 3 bit adder.vhd
9 Listing 9_1_Entity and Architecture definitions for discrete gates.vhd		9 Listing 9_1_Entity and Architecture definitions for discrete gates.vhd
9_design_hierarchy_3_bit_comparator.vhd		9_design_hierarchy_3_bit_comparator.vhd
Free Range Chap2 VHDL Invariants,		Free Range Chap2 VHDL Invariants,
Free Range Chap3 VHDL Design Units		Free Range Chap3 VHDL Design Units
README.md		README.md

etonw/Mealy_2019_Free-Range-VHDL

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