Skip to content

ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor

Notifications You must be signed in to change notification settings

ghosh17/DualCoreProcessor

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

11 Commits
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

DualCoreProcessor

ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor

The Computer Architecture & Processor Prototyping Lab project uses Computer Design and Prototyping. The goal of this project is to build a Dual Core MIPS processor that is pipelined, cached and multicored usng modern CAD tools, logic simulation, logic synthesis using hardware description languages and design hierarchy. I used System Verilog and an FPGA based prototyping board to rapidly develop and test prototypes of CPU designs.

Please Refer to report.pdf for more information on the design, comparison of the different designs, as well the detailed structure of all the blocks.

About

ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor

Topics

Resources

Stars

Watchers

Forks

Releases

No releases published

Packages

No packages published