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My Master's project thesis and a reference manual for AJIT FPGA system

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My Master's project thesis

.
|-- My_Thesis
|   |-- Latex_Code
|   |   |-- appendices
|   |   |-- bib
|   |   |-- chapters
|   |   |-- code_snippets
|   |   |-- eps_pdf_sources
|   |   |-- Forms
|   |   |-- images
|   |   |-- Makefile
|   |   |-- preamble
|   |   |-- setup
|   |   |-- thesis.synctex.gz
|   |   |-- thesis.tex
|   |   |-- tmp
|   |   |-- to_do.md
|   |   `-- Trash
|   `-- README.md
|-- README.md
`-- Reference_Manual_FPGA_System
    |-- Latex_Code
    |   |-- chapters
    |   |-- img
    |   |-- Makefile
    |   |-- preamble
    |   |-- references.bib
    |   |-- ref_manual.tex
    |   |-- setup
    |   `-- tmp
    |-- Notes
    |   `-- parts.md
    |-- README.md
    `-- RST_Code
        |-- accessing_general_slave_registers_on_axi.rst
        |-- adding_a_custom_peripheral.rst
        |-- adding_a_new_ajit_core.rst
        |-- basic_usage.rst
        |-- ddr_access.rst
        |-- designing_a_custom_peripheral.rst
        |-- design_of_system.rst
        |-- interfaces.rst
        |-- introduction.pdf
        |-- introduction.rst
        |-- need_for_a_system.rst
        |-- results.rst
        |-- setup_of_the_system.rst
        |-- tools.rst
        |-- tools_used_and_their_constraints.rst
        |-- understanding_the_pcie_interface_for_the_setup.rst
        `-- xsct_access.rst

22 directories, 28 files

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