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These labs were conducted during our Digital systems elective course were we were instructed to build Verilog code for specific logic design and verify it on Quartus modalism and on the FPGA. Skills developed: writing Verilog code structurally and behaviorally, testing, simulation, writing test benches and using the FPGA

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Name		Name	Last commit message	Last commit date
Latest commit History 14 Commits
Lab 3		Lab 3
Lab 4		Lab 4
Lab 5		Lab 5
Lab 6		Lab 6
.DS_Store		.DS_Store
README.md		README.md

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engr378-lab

All of the lab stuff is stored here

Alvin Guan

Sara Kalaf

San Francisco State University

ENGR 378-04

Spring 2020

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These labs were conducted during our Digital systems elective course were we were instructed to build Verilog code for specific logic design and verify it on Quartus modalism and on the FPGA. Skills developed: writing Verilog code structurally and behaviorally, testing, simulation, writing test benches and using the FPGA

design fpga digital simulation verilog testbenches modelsim altera-fpga fpga-programming digitallogic verilog-code

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