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Haskell to VHDL/Verilog/SystemVerilog compiler
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May 23, 2024 - Haskell
Efficient Library software for Miners and Pools
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May 23, 2024 - Rust
📉 Providing enhanced visibility into short positions on the Australian Stock Exchange
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May 23, 2024 - Jupyter Notebook
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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May 22, 2024 - SystemVerilog
VUnit is a unit testing framework for VHDL/SystemVerilog
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May 23, 2024 - VHDL
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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May 22, 2024 - VHDL
Allo: A Programming Model for Composable Accelerator Design
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May 21, 2024 - Python
A simplified and standardized interface for Bitcoin ASICs.
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May 20, 2024 - Python
This repository hosts the code for an FPGA based accelerator for convolutional neural networks
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May 20, 2024 - Verilog
DFiant HDL (DFHDL): A Dataflow Hardware Descripition Language
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May 23, 2024 - Scala
A Heterogeneous Platform Deep Learning Compiler Framework from EdgeCortix
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May 19, 2024 - Python
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
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May 23, 2024 - SystemVerilog
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