一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
-
Updated
Sep 15, 2023 - Bluespec
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
HDL support for VS Code
Bluespec System Verilog language extension for Visual Studio Code
Bluespec SystemVerilog Package for Sublime Text
Domain Specific Hardware Accelerators - VLSI CAD Project
Bluespec SystemVerilog extension for VS Code
Forth CPU J1 in Bluespec SystemVerilog (BSV)
Bluespec implementation of PG routing algorithm on a network on chip running a SMIPS
Quark is a single cycle RV32I RISC-V core, The RTL is written in BlueSpec System Verilog (BSV)
Implementação do protocolo TCP para a disciplina de Redes de Computadores da Universidade Federal de São Carlos - UFSCar
A collection of activation functions implemented in Bluespec for integration with hardware designs, ensuring IEEE 754 compliance
To toy around with Bluespec-SystemVerilog and my Basys3 board
Bluespec System Verilog syntax highlighting for Notepad++
Wishbone/Bluespec Systemverilog Transactors
Hardware implementation of floating point unit (IEEE-754 compliant) for RISC-V architecture
Learning bluespec with bunch of tutorials and example codes
Add a description, image, and links to the bluespec-systemverilog topic page so that developers can more easily learn about it.
To associate your repository with the bluespec-systemverilog topic, visit your repo's landing page and select "manage topics."