An abstraction library for interfacing EDA tools
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Updated
May 17, 2024 - Python
An abstraction library for interfacing EDA tools
HDL support for VS Code
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
Repurposing existing HDL tools to help writing better code
The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.
Tutorial de instalação do Quartus Prime no Linux
A Python-based IP Core Management Infrastructure.
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
A simulation to PDP-11 microprocessor with modelsim, The design is a micro-programmed based with an average of 9 clock cycles per instruction.
Single-Cycle RISC-V Processor in systemverylog
💻 Simulation for the architecture of a processor inspired by the ideas of PDP-11 processor
VHDL , ModelSIM, Quartus, FPGA, Image Processing
An 8-bit RISC based processor designed in verilog with x86 instructions.
simple read/write pcap tasks for SystemVerilog test
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