Verilator open-source SystemVerilog simulator and lint system
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Updated
Jun 1, 2024 - C++
Verilator open-source SystemVerilog simulator and lint system
QEMU libsystemctlm-soc co-simulation demos.
A modeling library with virtual components for SystemC and TLM simulators
The repository contains the coursework in the EE6470 course of NTHU's Electronic System Level Design and Synthesis.
A SystemC productivity library: https://minres.github.io/SystemC-Components/
SystemC/TLM-2.0 Co-simulation framework
SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
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