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soc: espressif: refactor clock and RTC subsystems #72701

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merged 5 commits into from
May 27, 2024

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LucasTambor
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The RTC subsystem in Espressif's SOCs, among other tasks, is responsible for clock selection for CPU and for low power domain clocks such as RTC_SLOW and RTC_FAST.

This commit allows for proper clock source and rate selection for CPU, using the espressif,riscv and espressif,xtensa-lx6/7 bindings.

It also enables clock selection for RTC_FAST and RTC_SLOW, that impacts some peripherals, such as rtc_timer.

It adds also changes for making the clock control api tests generic for any board.
All the device subsys definitions were moved to its own folder according to the clock compatible.
If the clock's async feature is not supported by the target, the test is skipped instead of failed.

Finally, it add tests for the rtc clk subsystem itself.

@zephyrbot zephyrbot added area: Xtensa Xtensa Architecture area: RISCV RISCV Architecture (32-bit & 64-bit) area: Clock Control platform: ESP32 Espressif ESP32 area: Counter area: Devicetree Binding PR modifies or adds a Device Tree binding area: Timer Timer labels May 13, 2024
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zephyrbot commented May 13, 2024

The following west manifest projects have been modified in this Pull Request:

Name Old Revision New Revision Diff
hal_espressif zephyrproject-rtos/hal_espressif@c495811 zephyrproject-rtos/hal_espressif@b5f5fa6 (zephyr) zephyrproject-rtos/hal_espressif@c4958117..b5f5fa6d

Note: This message is automatically posted and updated by the Manifest GitHub Action.

decsny
decsny previously requested changes May 13, 2024
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all the default values of properties in the DT bindings need justifications for why they are the default value in the descriptions

@LucasTambor
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all the default values of properties in the DT bindings need justifications for why they are the default value in the descriptions

@decsny there is no need indeed for this default values, it can depend mostly on the application and power requirements. I removed the default values and added required: true so no one misses them.

Add changes to comply with rtc refactor.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
The RTC subsystem in espressif's SOCs, among other tasks
is responsible for clock selection for CPU and for low
power domain clocks such as RTC_SLOW and RTC_FAST.

This commit allows for proper clock source and rate
selection for CPU, using the espressif,riscv and
espressif,xtensa-lx6/7 bindings.

It also enables clock selection for RTC_FAST and RTC_SLOW,
that impacts some peripherals, such as rtc_timer.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Changes for making the clock control api tests generic for
any board.
All the device subsys definitions were moved to its own folder
according to the clock compatible.
Also if the clock's async feature is not supported by the target,
the test is skipped instead of failed.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add support for rtc timer node in the test.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add tests for the rtc clk subsystem.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
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@nashif, can you take a look please?

@carlescufi carlescufi merged commit 4684b19 into zephyrproject-rtos:main May 27, 2024
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area: Clock Control area: Counter area: Devicetree Binding PR modifies or adds a Device Tree binding area: RISCV RISCV Architecture (32-bit & 64-bit) area: Timer Timer area: Xtensa Xtensa Architecture manifest manifest-hal_espressif platform: ESP32 Espressif ESP32
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8 participants