Superscalar_Pipeline_Processor

Finished design for a superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predictor, and a 2-way superscalar pipeline processor issuing two instructions at a time. The project was to be completed over a course of an academic quarter and the design is intended for Yiming Gan and Dylan Vanmali, the creators of the project.

Check out the report located under the file final_report.pdf for a visual of this design and report of our findings!

Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
LICENSE		LICENSE
README.md		README.md
adder.v		adder.v
alu.v		alu.v
aludec.v		aludec.v
branchhistory_test.v		branchhistory_test.v
branchhistorytable.v		branchhistorytable.v
cache_test.v		cache_test.v
cache_wb.v		cache_wb.v
decode.v		decode.v
execute.v		execute.v
fetch.v		fetch.v
final_report.pdf		final_report.pdf
flop.v		flop.v
flopenr.v		flopenr.v
flopr.v		flopr.v
globalbranchpredictor.v		globalbranchpredictor.v
hazardcontroller.v		hazardcontroller.v
instrmem.v		instrmem.v
mainmem.v		mainmem.v
mem.v		mem.v
memfile.dat		memfile.dat
memfile2.dat		memfile2.dat
memfile3.dat		memfile3.dat
memory.v		memory.v
memory_system.v		memory_system.v
mips_test3.v		mips_test3.v
mipspipeline.v		mipspipeline.v
multiplier.v		multiplier.v
multiplier_test.v		multiplier_test.v
mux2.v		mux2.v
mux3.v		mux3.v
mux4.v		mux4.v
mux5.v		mux5.v
mux6.v		mux6.v
pipeem.v		pipeem.v
pipefd.v		pipefd.v
pipelinecontrol.v		pipelinecontrol.v
pipelinedec.v		pipelinedec.v
pipemw.v		pipemw.v
regfile.v		regfile.v
sl2.v		sl2.v
sl226.v		sl226.v
testcache.v		testcache.v
write.v		write.v

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dvanmali/Superscalar_Pipeline_Processor

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