Non-Temporal Memory Transfers for ARM #961
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Make ldnp load 64-bit registers (instead of 32-bit-wide registers)
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Works on my M2. I tried a convergence test (Snell's law) and achieved the same error for both this branch and master. Performance difference is hart to quantify. As this is a laptop, the difference between runs with the same settings is smaller than the difference between the settings. |
Codecov ReportAll modified and coverable lines are covered by tests ✅
❗ Your organization needs to install the Codecov GitHub app to enable full functionality. Additional details and impacted files@@ Coverage Diff @@
## master #961 +/- ##
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Coverage 13.82% 13.82%
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Files 268 268
Lines 14984 14984
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Hits 2071 2071
Misses 12913 12913 ☔ View full report in Codecov by Sentry. |
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@jwjeremy do you have capacity to test this branch and the master branch on your macbook before the training next week? |
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This PR adds non-temporal loads/stores for ARM processors.
In principle functional, but not yet completely tested through. Especially the memory ordering for the pure-AARCH64 may need more verification.
PR for better visibility