-
Implement basic operations ( <<, x10, +(-), &)
-
Implement testbench for basic operations
-
Implement CORDIC algorithm to
cordic.v
file -
Implement testbench of CORDIC algorithm
-
FPGA test
-
Apply sequential logics (@ least 6 states)
-
(Jun 01) Multiplication algorithm debugged.
-
(Jun 02) FPGA board test done.
- with TA's reference code for constraints.
-
(Jun 10) FPGA Test w/ Sequential logic done.
- Now we can watch each steps of CORDIC algorithm (as a state).
Debug Multiplier as 32bit multipliers with given format :- Issue Fixed: Addition carry propagate direction.